JPS63292270A - Layout system for inter-drawing connection information on logic circuit diagram - Google Patents

Layout system for inter-drawing connection information on logic circuit diagram

Info

Publication number
JPS63292270A
JPS63292270A JP62127452A JP12745287A JPS63292270A JP S63292270 A JPS63292270 A JP S63292270A JP 62127452 A JP62127452 A JP 62127452A JP 12745287 A JP12745287 A JP 12745287A JP S63292270 A JPS63292270 A JP S63292270A
Authority
JP
Japan
Prior art keywords
inter
information
connection information
logic circuit
drawing connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62127452A
Other languages
Japanese (ja)
Inventor
Soichi Ishikawa
石川 惣一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62127452A priority Critical patent/JPS63292270A/en
Publication of JPS63292270A publication Critical patent/JPS63292270A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To solve such problems where a wiring route is closed due to the complication of inter-drawing connection information or a drawing is not easily read, by arranging the inter-drawing connection information at the output side where the complication is easily produced in particular with proper blank spaces secured in accordance with the state of said complication. CONSTITUTION:The information whose size is larger than the size of an element frame and continuous in the direction of said frame size is arranged with preference and alternate shifts given inside and outside every field of a single element frame among those inter-drawing connection information on the output side. While other information is arranged with preference at the most outside adjacent position where these information can be connected with the elements to be connected on a straight line. Thus it is possible to reduce the complication in terms of the layout of the inter-drawing connection information in order to avoid the closure of a wiring route. In such a way, a logic circuit diagram which can be easily read is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、論理回路のCADシステムに利用される図面
間接続情報の配置方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for arranging inter-drawing connection information used in a CAD system for logic circuits.

従来の技術 電子計算機システムを用いて行う論理回路のCADでは
、ディジタル処理装置の自動論理設計が行われ、この結
果として論理回路図の図面情報が作成される。この図面
情報には、論理回路図内の素子情報と図面内及び図面間
接続情報が含まれている。この図面間及び図面内接続情
報は、接続対象の素子の図面内位置や端子番号などから
構成される。
2. Description of the Related Art In logic circuit CAD performed using a conventional electronic computer system, automatic logic design of a digital processing device is performed, and as a result, drawing information of a logic circuit diagram is created. This drawing information includes element information within the logic circuit diagram and connection information within and between drawings. This inter-drawing and intra-drawing connection information includes the position within the drawing of the element to be connected, the terminal number, and the like.

従来の図面間接続情報の配置方式によれば、第10図に
例示するように、斜線と小文字のアルファベットが付さ
れた図面間接続情報が大文字のアルファベットが付され
た接続対象の素子の最短位置に配置されるようになって
いる。
According to the conventional arrangement method of inter-drawing connection information, as illustrated in FIG. 10, the inter-drawing connection information marked with diagonal lines and lowercase letters is the shortest position of the connected elements marked with uppercase letters. It is designed to be placed in

発明が解決しようとする問題点 上記従来の図面間接枝情報の配置方式では、これらを接
続対象素子の最短位置に配置しているだけであるから、
図面間接枝情報の錯綜によって接続経路が塞がれたり、
判読が困難になるなどの問題がある。
Problems to be Solved by the Invention In the above-mentioned conventional method for arranging branch information between drawings, these are simply arranged at the shortest positions of the connected elements.
Connection routes may be blocked due to confusion in drawing indirect branch information,
There are problems such as making it difficult to read.

問題点を解決するための手段 本発明に係わる論理回路図の図面間接枝情報の配置方式
は、入力側の図面間接枝情報のうち接続対象の素子と1
対1の関係にあるものについてはこの素子と直線上で接
続できかつこの素子との間に1素子枠フィールド分の空
きスペースを介在させる位置に優先的に配置し、接続対
象の素子と1対複数の関係にあるものについては最も外
側の素子と直線上で接続できかつこれとの間に1素子枠
フィールド分の空きスペースを介在させる位置に優先的
に配置するように構成されている。
Means for Solving the Problems The method of arranging the drawing-direction branch information of the logic circuit diagram according to the present invention is such that the drawing-direction branch information on the input side is arranged such that one element and one element to be connected are connected.
For those that have a one-to-one relationship, they are placed preferentially in a position where they can be connected in a straight line to this element and there is an empty space for one element frame field between them, and one pair is placed with the element to be connected. Those having a plurality of relationships are arranged preferentially at a position where they can be connected to the outermost element on a straight line and have an empty space of one element frame field between them.

また、出力側の図面間接枝情報のうちそのサイズが素子
枠サイズ以上でかつこのサイズの方向に連続しているも
のについてはこのサイズの方向に交互に1素子枠フィー
ルド分ずつ内側と外側にずらしながら優先的に配置し、
その他のものについては接続対象の素子と直線上で接続
できる外側の最隣接位置に優先的に配置することにより
、図面間接枝情報の配置の錯綜を軽減して、配線経路の
閉塞を避けると共に、判読の容易な論理回路図を作成す
るように構成されている。
Also, among the drawing-to-drawing branch information on the output side, those whose size is greater than or equal to the element frame size and are continuous in the direction of this size are alternately shifted inward and outward by one element frame field in the direction of this size. while placing priority on
By preferentially arranging other items at the outermost adjacent position where they can be connected in a straight line with the element to be connected, the confusion in the arrangement of indirect branch information in the drawing can be reduced, and the blockage of the wiring route can be avoided. It is configured to create an easily readable logic circuit diagram.

以下、本発明の作用を実施例と共に詳細に説明する。Hereinafter, the operation of the present invention will be explained in detail together with examples.

実施例 第1図は、本発明の一実施例を適用するCADシステム
の構成を示すブロック図であり、1は主記憶装置、2は
処理装置、3は自動図面入力装置、4は端末装置、5は
外部記憶ファイル、6はプリンタなどの図面出力装置で
ある。
Embodiment FIG. 1 is a block diagram showing the configuration of a CAD system to which an embodiment of the present invention is applied, in which 1 is a main storage device, 2 is a processing device, 3 is an automatic drawing input device, 4 is a terminal device, 5 is an external storage file, and 6 is a drawing output device such as a printer.

主記憶装置1は、処理装置2によって実行される各種の
処理プログラムの格納エリアに加えて、図面情報格納エ
リア11、生成図面名情報格納エリア12、素子情報格
納エリア13、図面内接続情報格納エリア14、図面間
接枝情報格納エリア15及び論理回路図イメージ格納エ
リア16を備えている。
In addition to storage areas for various processing programs executed by the processing device 2, the main storage device 1 includes a drawing information storage area 11, a generated drawing name information storage area 12, an element information storage area 13, and an intra-drawing connection information storage area. 14, a drawing branch information storage area 15, and a logic circuit diagram image storage area 16.

第2図は、第1図の処理装置2によって実行される論理
回路図イメージ作成処理の流れを示すフローチャートで
ある。
FIG. 2 is a flowchart showing the flow of the logic circuit diagram image creation process executed by the processing device 2 of FIG.

本発明の一実施例に係わる図面間接枝情報の配置処理は
、上記フローチャート中にステップ27と28として含
まれており、これらのステップの詳細な内容はそれぞれ
第3図と第4図のフローチャートに示されている。
The arrangement process of drawing indirect branch information according to an embodiment of the present invention is included as steps 27 and 28 in the above flowchart, and detailed contents of these steps are shown in the flowcharts of FIGS. 3 and 4, respectively. It is shown.

まず、第2図のフローチャートを参照すると、処理装置
2は、自動図面入力装置3や端末装置4から図面情報が
人力されると最初のステップ21において、入力された
図面情報を素子情報と接続情報とに分離しつつ外部記憶
ファイル5に格納する。処理装置2は、端末装置4から
入力される生成画面名のページによる指定をステップ2
2で受取るとステップ23に進み、指定ページの図面情
報を外部記憶ファイル5から横築、抽出し、素子情報、
図面的接続情報、図面間接枝情報を対応の格納エリア1
3〜15に格納する。
First, referring to the flowchart in FIG. 2, when drawing information is input manually from the automatic drawing input device 3 or terminal device 4, the processing device 2 converts the input drawing information into element information and connection information in the first step 21. The data is stored in the external storage file 5 while being separated into two parts. The processing device 2 specifies the generation screen name input from the terminal device 4 in step 2.
When received in step 2, the process proceeds to step 23, where the drawing information of the designated page is extracted from the external storage file 5, and the element information,
Storage area 1 for drawing connection information and drawing indirect branch information
3 to 15.

次のステップ24では、素子情報格納エリア13内の素
子情報が論理回路図イメージ格納エリア16内に素子枠
のイメージとして展開される。ステップ25では、図面
間接枝情報格納エリア15から図面間接枝情報が抽出さ
れ、この抽出された図面間接枝情報が入力側のものであ
るが出力側のものであるかがステップ26で検査される
。抽出された図面間接枝情報が入力側のものであればス
テップ27で入力側の配置処理が行われ、出力側のもの
であればステップ28で出力側の配置処理が行われる。
In the next step 24, the element information in the element information storage area 13 is expanded into the logic circuit diagram image storage area 16 as an image of an element frame. In step 25, drawing indirect branch information is extracted from the drawing indirect branch information storage area 15, and in step 26 it is checked whether the extracted drawing indirect branch information is from the input side or the output side. . If the extracted drawing indirect branch information is on the input side, an input side placement process is performed in step 27, and if it is on an output side, an output side placement process is performed in step 28.

第3図は、第2図のステップ27で実行される入力側の
配置処理の手順を示すフローチャートである。
FIG. 3 is a flowchart showing the procedure of the input side placement process executed in step 27 of FIG.

最初のステップ31で図面間接枝情報と接続対象の素子
数とが1対1に対応するか否がが検査され、1対工の対
応関係にあればこの配置処理はステップ32に進む。ス
テップ32では、第5図に例示するように、接続対象の
素子Flと水平に接続できかつこの素子との間に1素子
枠フィールド分の空きスペースを介在できる左側の位置
に図面間接枝情報fが優先的に配置される。なお、第5
図の右下に例示するように上記優先位置が既に他の情報
で専有されている場合には、この位置を中心に上下1行
ずつにわたって空きスペースが探索され、そのような空
きスペースに図面接続情報が配置される。
In the first step 31, it is checked whether there is a one-to-one correspondence between the drawing indirect branch information and the number of elements to be connected, and if there is a one-to-one correspondence, the arrangement processing proceeds to step 32. In step 32, as illustrated in FIG. 5, the inter-drawing branch information f is placed on the left side where it can be connected horizontally to the element Fl to be connected and where an empty space for one element frame field can be interposed between the element and this element. are placed preferentially. Furthermore, the fifth
As illustrated in the lower right of the figure, if the above priority position is already occupied by other information, an empty space is searched for one line above and below the other, centering on this position, and the drawing is connected to such an empty space. Information is placed.

一方、第3図のステップ31で図面間接枝情報と接続対
象の素子とが1対複数の関係にあることが検出されると
、入力側の配置処理はステップ33に進む。ステップ3
3では、第6図に例示するように、接続対象の3個の素
子AI、Bl及びC1のうち図面内の高さが最大の素子
A1と水平に接続できかつこれとの間に1素子枠フィー
ルド分の空きスペースを介在させる左側の位置に図面間
接枝情報fが優先的に配置される。
On the other hand, if it is detected in step 31 of FIG. 3 that there is a one-to-many relationship between the drawing-direction branch information and the elements to be connected, the input-side arrangement processing proceeds to step 33. Step 3
3, as illustrated in FIG. 6, it is possible to connect horizontally to the element A1, which has the largest height in the drawing among the three elements AI, Bl, and C1 to be connected, and there is one element frame between them. The inter-drawing branch information f is preferentially arranged on the left side with an empty space for the field interposed therebetween.

第4図は、第2図のステップ28で実行される出力側の
図面間接枝情報の配置処理の手順を示すフローチャート
である。
FIG. 4 is a flowchart showing the procedure for arranging inter-drawing branch information on the output side, which is executed in step 28 of FIG.

最初のステップ41において、1素子から出力される図
面間接枝情報が素子枠サイズ以上であるか否かが検査さ
れ、そうでなければこの配置処理はステップ42に進む
。一方、l素子から出力される図面間接枝情報が素子枠
サイズ以上であれば、ステップ43で上記の条件が縦方
向に連続して成立しているか否かが検査され、成立して
いなければ配置処理は上述のステップ42に進む。ステ
ップ42では、第7図に例示するように、接続対象の素
子と水平に接続できる右側の隣接位置に各図面間接枝情
報が優先的に配置される。
In the first step 41, it is checked whether the drawing indirect branch information output from one element is equal to or larger than the element frame size, and if not, the arrangement processing proceeds to step 42. On the other hand, if the drawing indirect branch information output from the l element is equal to or larger than the element frame size, it is checked in step 43 whether the above conditions are continuously satisfied in the vertical direction, and if not, the arrangement is performed. Processing continues to step 42 described above. In step 42, as illustrated in FIG. 7, each piece of inter-drawing branch information is preferentially arranged at an adjacent position on the right side where it can be horizontally connected to the element to be connected.

一方、1素子から出力される図面間接枝情報が素子枠サ
イズ以上でかつこの条件が縦方向に連続して成立してい
ることがステップ43で判定されると、配置処理はステ
ップ44に進む。ステップ44では、第8図に例示する
ように、図面間接枝情報が高さ方向に交互に1素子枠分
ずつ左右にずらされながら右側の位置に優先的に配置さ
れる。
On the other hand, if it is determined in step 43 that the drawing indirect branch information output from one element is equal to or larger than the element frame size and that this condition is continuously satisfied in the vertical direction, the arrangement process proceeds to step 44. In step 44, as illustrated in FIG. 8, the inter-drawing branch information is alternately shifted to the left and right by one element frame in the height direction, and is preferentially placed at the right position.

第3図と第4図で説明した第2図のステップ27又はス
テップ28のそれぞれにおいて上述した入力側又は出力
側の図面間接枝情報の配置処理が終了すると、第2図の
ステップ29において1ペ一ジ分の処理が終了したか否
かが判定され、未終了であれば、ステップ25に戻り新
たな図m1間接続情報が抽出され、これについて上述の
配置処理が繰り返される。
When the above-mentioned placement process of inter-drawing branch information on the input side or output side is completed in step 27 or step 28 of FIG. 2 explained in FIG. 3 and FIG. It is determined whether or not one page's worth of processing has been completed, and if it has not been completed, the process returns to step 25 and new connection information between diagrams m1 is extracted, and the above-described placement process is repeated for this.

ステップ29で1ペ一ジ分の処理の終了が判定されると
、ステップ30において、図面間接枝情報と素子間、ま
た素子相互間の接続パターンの発生による結線が行われ
、1ペ一ジ分の論理回路図イメージが完成する。
When it is determined in step 29 that the processing for one page has been completed, in step 30, connections are performed based on the drawing indirect branch information and the generation of connection patterns between elements and between elements. The logical circuit diagram image is completed.

完成した論理回路図のイメージは、プリンタなどで構成
される図面出力装置6によって出力される。
The image of the completed logic circuit diagram is outputted by a drawing output device 6, which may include a printer or the like.

従来方式によって作成した第10図の論理回路図を本発
明によって作成し直すと、第9図に例示するようなもの
となる。
When the logic circuit diagram of FIG. 10 created by the conventional method is re-created according to the present invention, it becomes as illustrated in FIG. 9.

本発明の配置方式によれば、図面間接枝情報どうしが錯
綜して接続経路を閉塞し合ったり、図面の判読が困難に
なるというような事態が回避される。
According to the arrangement method of the present invention, it is possible to avoid a situation in which drawing-related branch information becomes intertwined with each other and blocks a connection path or makes it difficult to read the drawing.

以上、論理回路図を左右に接続する場合を例示したが、
上下に接続する場合についても本発明の方式を適用でき
る。
Above, we have illustrated the case where the logic circuit diagram is connected to the left and right, but
The method of the present invention can also be applied to the case of vertical connection.

発明の効果 以上詳細に説明したように、本発明に係わる図面間接枝
情報の配置方式によれば、入力側についても出力側につ
いても適当な空きスペースを持たせつつ、特に錯綜の生
じ易い出力側についてはその錯綜状況に応じて適当な空
きスペースを持たせつつ図面間接枝情報を配置する構成
であるから、図面間接枝情報の錯綜によって配線経路が
閉塞されたり図面の判読が困難になるなどの問題が有効
に解決される。
Effects of the Invention As explained in detail above, according to the arrangement method of drawing indirect branch information according to the present invention, an appropriate amount of free space is provided on both the input side and the output side, while the output side, where confusion is particularly likely to occur, is Since the configuration is such that drawing indirect branch information is arranged with appropriate free space according to the complicated situation, it is possible to avoid problems such as wiring routes being blocked or drawings becoming difficult to read due to confusing drawing indirect branch information. Problems are resolved effectively.

この結果、各種論理回路の設計、製造、検査、保守の工
程を通して品質と生産性の向上が図られるという効果が
ある。
As a result, quality and productivity can be improved through the processes of designing, manufacturing, inspecting, and maintaining various logic circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を適用するCADシステムの
関連部分の構成を示すブロック図、第2図は第1図の処
理装置2によって実行される論理回路図イメージ作成処
理の流れを示すフローチャート、第3図と第4図はそれ
ぞれ第2図のステップ27と28における入力側と出力
側の図面間接続情報の配置処理の手順を示すフローチャ
ート、第5図と第6図は入力側の図面間接続情報の配置
処理の具体例を示す概念図、第7図と第8図は出力側の
図面間接続情報の配置処理の具体例を示す概念図、第9
図と第10図はそれぞれ上記実施例と従来方式によって
作成された論理回路図の一例を対比させて示す概念図で
ある。 l・・・主記憶装置、2・・・処理装置、3・・・図面
入力装置、4・・・端末装置、5・・・外部記憶ファイ
ル、6・・・図面出力装置。
FIG. 1 is a block diagram showing the configuration of related parts of a CAD system to which an embodiment of the present invention is applied, and FIG. 2 shows the flow of logic circuit image creation processing executed by the processing device 2 of FIG. 1. Flowcharts, FIGS. 3 and 4 are flowcharts showing the procedure for arranging inter-drawing connection information on the input side and output side in steps 27 and 28 of FIG. 2, respectively. FIGS. 7 and 8 are conceptual diagrams showing a specific example of arrangement processing of inter-drawing connection information; FIG. 9 is a conceptual diagram showing a specific example of arrangement processing of inter-drawing connection information on the output side;
This figure and FIG. 10 are conceptual diagrams showing an example of a logic circuit diagram created by the above-mentioned embodiment and a conventional method, respectively. 1... Main storage device, 2... Processing device, 3... Drawing input device, 4... Terminal device, 5... External storage file, 6... Drawing output device.

Claims (1)

【特許請求の範囲】 入力側の図面間接続情報のうち接続対象の素子と1対1
の関係にあるものについてはこの素子と直線上で接続で
きかつこの素子との間に1素子枠フィールド分の空きス
ペースを介在させる位置に優先的に配置し、接続対象の
素子と1対複数の関係にあるものについては最も外側の
素子と直線上で接続できかつこれとの間に1素子枠フィ
ールド分の空きスペースを介在させる位置に優先的に配
置し、 出力側の図面間素子情報のうちそのサイズが素子枠サイ
ズ以上でかつこのサイズの方向に連続しているものにつ
いてはこのサイズの方向に交互に1素子枠フィールド分
ずつ内側と外側にずらしながら優先的に配置し、その他
のものについては接続対象の素子と直線上で接続できる
外側の最隣接位置に優先的に配置することを特徴とする
論理回路図の図面間接続情報の配置方式。
[Claims] One-to-one with the element to be connected among the inter-drawing connection information on the input side.
For devices with a relationship of Those that are in a relationship are placed preferentially in a position where they can be connected to the outermost element on a straight line and have an empty space of one element frame field between them, and among the inter-drawing element information on the output side. Items whose size is greater than or equal to the element frame size and are continuous in the direction of this size are placed preferentially while being alternately shifted inward and outward by one element frame field in the direction of this size, and other items are placed preferentially. is a method for arranging inter-drawing connection information in logic circuit diagrams, which is characterized in that it is preferentially placed at the outermost adjacent position where it can be connected in a straight line with the element to be connected.
JP62127452A 1987-05-25 1987-05-25 Layout system for inter-drawing connection information on logic circuit diagram Pending JPS63292270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62127452A JPS63292270A (en) 1987-05-25 1987-05-25 Layout system for inter-drawing connection information on logic circuit diagram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62127452A JPS63292270A (en) 1987-05-25 1987-05-25 Layout system for inter-drawing connection information on logic circuit diagram

Publications (1)

Publication Number Publication Date
JPS63292270A true JPS63292270A (en) 1988-11-29

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ID=14960273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62127452A Pending JPS63292270A (en) 1987-05-25 1987-05-25 Layout system for inter-drawing connection information on logic circuit diagram

Country Status (1)

Country Link
JP (1) JPS63292270A (en)

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