CN110472340A - A kind of modeling method and device of wire structures - Google Patents
A kind of modeling method and device of wire structures Download PDFInfo
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- CN110472340A CN110472340A CN201910759282.6A CN201910759282A CN110472340A CN 110472340 A CN110472340 A CN 110472340A CN 201910759282 A CN201910759282 A CN 201910759282A CN 110472340 A CN110472340 A CN 110472340A
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Abstract
The invention discloses a kind of modeling method of wire structures and devices.This method comprises: determining FPGA series information, FPGA series information includes FPGA basic module wire structures information and FPGA basic module interconnection information；The set for constituting the basic module of FPGA device is determined according to FPGA series information；Set based on basic module establishes FPGA device information.What this method provided is namely based on the FPGA device arrangement information of serial (Series) information of FPGA and customization to establish entire fpga chip interconnection resource figure information (Routing Resource Graph, RRG a kind of method), it does not need to generate the complete domain structure of fpga chip or netlist information, the wire structures information of desired FPGA device directly can be obtained by " splicing " mode.
Description
Technical field
The present embodiments relate to the software design arts of programmable logic device (FPGA) more particularly to a kind of wire bonds
The modeling method and device of structure.
Background technique
Current live programmable gate array (FPGA) has become a kind of indispensable realization means in digital circuit field,
There is apparent advantage in terms of development cycle and programmable flexibility, application field also increasingly extensively, is related to communication, boat
It, medical treatment, mathematical computations, image procossing, the numerous areas such as consumer products.In terms of international market, in decades, Xilinx and
Altera two giants have almost monopolized all core technologies, have captured almost 90% market share, and patent is up to more than 6000
, Xilinx also remains the leading position of global FPGA.It reviews domestic FPGA industry and is faced with that technical barrier is higher, opens
Difficulties, the software configuration modeling methods of FPGA such as the hair period is long, capital investment is big are nearly at technological gap state at home, by
Links all rely on the support of FPGA structure data in FGPA CAD process, so making the development one of FGPA cad tools
Determine to have received limitation in degree.
Summary of the invention
The present invention provides a kind of modeling method of wire structures, with realize solve FGPA CAD process in links according to
Rely in the support of FPGA structure data, so the problem of making the development of FGPA cad tools have received limitation to a certain extent.
In a first aspect, the embodiment of the invention provides a kind of modeling methods of wire structures, comprising:
Determine that FPGA series information, the FPGA series information include FPGA basic module wire structures information and FPGA base
This module interconnection information；
The set for constituting the basic module of FPGA device is determined according to the FPGA series information；
The wire structures information of the FPGA device is determined based on the set of the basic module.
Second aspect, the embodiment of the invention also provides a kind of model building devices of wire structures, comprising:
Information determination module, for determining that FPGA series information, the FPGA series information include FPGA basic module cloth
Cable architecture information and FPGA basic module (Tile) interconnection information；
Gather determining module, for determining the collection for constituting the basic module of FPGA device according to the FPGA series information
It closes；
Information establishes module, determines that the wire structures of the FPGA device are believed for the set based on the basic module
Breath.
The present invention is based on serial (Series) information of FPGA and the FPGA device arrangement information of customization are entire to establish
A kind of method of fpga chip interconnection resource figure information (Routing Resource Graph, RRG) does not need to generate FPGA
The complete domain structure of chip or netlist information directly can obtain the wire structures of desired FPGA device by " splicing " mode
Information (Routing Resource Graph, RRG).
Detailed description of the invention
Fig. 1 is a kind of flow chart of the modeling method of wire structures provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram that corresponding two groups of available points connection is established according to two groups of Port Connection Informations in table one；
Fig. 3 is the coordinate system schematic diagram on the chip that the present invention defines；
Fig. 4 is device arrangement result schematic diagram；
Fig. 5 is the schematic diagram of generating device interconnection resource figure process of the invention；
Fig. 6 is a kind of model building device of wire structures provided by Embodiment 2 of the present invention.
Specific embodiment
Embodiment one
Fig. 1 is a kind of flow chart of the modeling method of wire structures provided in an embodiment of the present invention.The present embodiment is applicable
The modeling for carrying out in generating device information based on customized information and to device wire structures, provides the field of interconnection resource figure information
Scape.This method is executed by a kind of model building device of wire structures, is specifically comprised the following steps:
S100, FPGA series information is determined.
In this implementation, chip generic series (Series) determine the basic module that creation fpga chip is capable of calling
(Tile) type, so determining that FPGA device generic series (Series) information to be customized is to create the premise of FPGA device
Condition.FPGA series (Series) information includes two aspects altogether, is FPGA basic module (Tile) wire structures information respectively
It with FPGA basic module (Tile) interconnection information, is respectively used to establish information above, includes following two process:
(1) basic module (Tile) wire structures software modeling.
The step may include following mode:
S110, the net meter file for determining basic module.
S120, the net meter file is parsed to determine the input information of basic module wire structures software modeling.
The step may include following sub-step:
S1201, program of being increased income by iverilog carry out netlist (netlist) parsing.
S1202, believe the parsing result of the parsing as the input of basic module (Tile) wire structures software modeling
Breath, the input information includes port (Port) information of basic module (Tile), gauze (Wire) information, module instance
(Instance) information.
It is basic for establishing the input file that basic module (Tile) wire structures information selects in the embodiment of the present invention
Netlist (netlist) file --- the hardware description file of verilog syntax format of module (Tile) selects netlist
(netlist) file as input file the reason is that extract netlist (netlist) file high reliablity and be easy to get.As showing
Example, verilog formatted file can be described as most popular hardware description language in the world, therefore can be by many open source c++
Program is parsed, and the present invention carries out netlist (netlist) by iverilog open source program and parses, and parsing result includes basic
Port (Port) information, gauze (Wire) information, module instance (Instance) information of module (Tile), information above is made
For the input information of basic module (Tile) wire structures software modeling.
The form of the verilog format input file of the basic module (Tile) of the embodiment of the present invention is as follows:
It is configurable logic block that above-mentioned example code, which describes basic module (Tile) type,
The part-structure of (ConfigurableLogic Block, CLB) forms, and the module (module) of CLB type is entitled in file
" BLK_CELL_LIB ", module output port (Port) include " blk_cout, blk_rcascout " etc., module gauze (Wire)
Include " Icb_lab_cout0, Icb_lab_cout1, Icb_lab_led, Icb_lab_lec, Icb_lab_leb, Icb_lab_
Lea " etc., the example (Instance) that module is called include " Ile_S0, Ile_S1, Ile_S2, Ile_S3, Ile_S4, Ile_
S5, Ile_S6, Ile_S7, Ile_S8, Ile_S9, Icb_lab_Ilab_Ictlgic_S10, Iclab_Itiehi_0__
Itiehi_hvt, Iclab_Itielo_0__Itielo, Iswb_Isw_N13_U0 " etc..
Table 1 is the section ports link information schematic table of the invention extracted in the verilog file of CLB.
Table 1
The starting point of two signals is described to the connection of end point as shown in table 1, is signal " Icb_lab_ respectively
The starting point of cout0 [9] " is the output port " cout0 " of example " Icb_lab_Ilab_Ile_S9 ", and terminal is example " Icb_
The input port " le9cout0 " of lab_Ilab_Ictlgic_S10 ", the other is signal " Icb_lab_cout1 [9] " rises
Initial point is the output port " cout1 " of example " Icb_lab_Ilab_Ile_S9 ", and terminal is example " Icb_lab_Ilab_
The input port " le9cout1 " of Ictlgic_S10 ".
Fig. 2 is the schematic diagram that corresponding two groups of available points connection is established according to two groups of Port Connection Informations in table one.Pass through
The module type of example " Icb_lab_Ilab_Ile_S9 " is LE_CELL_LIB known to the net meter file of CLB, from arc_
The cloth line attribute that LE_CELL_LIB can be looked into guide.xml is " FUNCTION ", sentence " < ROUTING key=" source_
1 " value=" cout0 "></ROUTING>" show that the port " cout0 " needs to establish a SOURCE type available point, it is denoted as
S1, similarly, the port " cout1 " establish a SOURCE type available point, are denoted as S2；It can similarly look into, " Icb_lab_Ilab_
The module type of Ictlgic_S10 " be " contrlogic_cfgcell ", type of wiring be " CONNECTION ", sentence <
ROUTING key=" input_1 " value=" le9cout0, le9cout1 "></ROUTING><ROUTING key="
Output_1 " value=" labcout "></ROUTING></MODULE>show input port " le9cout0, le9cout1 "
One group of connection relationship corresponding with output port labcout should establish a CHAN type available point, be denoted as C1, and because signal
" Icb_lab_cout0 [9] " are connected to the output port " cout0 " and example " Icb_ of example " Icb_lab_Ilab_Ile_S9 "
The input port " le9cout0 " of lab_Ilab_Ictlgic_S10 ", has respectively corresponded available point S1 and available point C1, therefore
An effective edge will be established in digraph between S1 and C1.Similarly, an effective edge is established between available point S2 and available point C1.
After this, can also include following sub-step:
S130, the functions of modules by cloth line attribute according to basic module divide, to determine belonging to a basic module
Module type, and then determine the cloth line attribute of the basic module, the module type includes top-level module, representation function mould
Block describes reconfigurable interconnection attribute modules and is directly connected to effort module.
This implementation can introduce an xml format input file as the wire structures information for establishing basic module
Secondary file --- arc_guide.xml, file are subordinated to current series, and content mainly defines under current series (Series)
The module (module) occurred in netlist (netlist) file of all basic modules (Tile) is establishing interconnection resource figure
(RRG) definition rule of cloth line attribute and available point during.
The cloth line attribute of module (module) is exactly that module is literary in arc_guide.xml during establishing interconnection resource figure
The attribute tags of Manual definition in part.The present invention defines netlist with MODULE sentence in arc_guide.xml file
(netlist) the wiring attribute information of each module (module) of the appearance in file, wherein in MODULE sentence
" name " attribute-bit module name, " route_type " attribute-bit cloth line attribute in MODULE sentence.
Lower section code is the file format of arc_guide.xml input file of the invention,
As shown in code, all modules in configurable logic block (ConfigurableLogic Block, CLB) are defined
(module) definition rule of cloth line attribute and available point, wherein " route_type " attribute of BLK_CELL_LIB module be
HIE is represented as top-level module；" route_type " attribute of LE_CELL_LIB module is to define two SOURCE types to have
Imitate point, respectively correspond two output ports " cout0, cout1 " define four SINK type available points, respectively correspond four it is defeated
Inbound port " lea, leb, lec, led "；" route_type " attribute of TIEHI_CELL_LIB module is FUNCTION, is defined
One CONSTHIGH type available point, corresponding output port " y "；" route_type " attribute of TIELO_CELL_LIB module
For FUNCTION, a CONSTLOW type available point, corresponding output port " y " are defined；Contrlogic_cfgcell mould
" route_type " attribute of block is CONNECTION, defines a CHAN type available point, corresponding input port
" le9cout0, le9cout1 ", output port " labcout "；Available point is not established for RES_CELL_LIB module type.
Cloth line attribute is divided into four kinds according to functions of modules by the embodiment of the present invention, is respectively as follows:
" HIE " for identifying netlist (netlist) top-level module, i.e., in netlist with basic module (Tile) module of the same name
(module) route_type " attribute is written as " HIE ".
Table 2 is that the cloth line attribute of foundation available point said module of the invention determines that available point typing rule shows table.
Table 2
HIE type block as shown in table 2 is defined without available point, and HIE type represents module as top-level module i.e. Tile,
Summation of the definition of available point from the available point for calling example creation in the interconnection resource figure of Tile.FUNCTION class pattern
The output port of block is defined as SOURCE type or CONSTHIGH type available point, input port be defined as SINK type or
Person's CONSTLOW type, only when module type be low and high level when, available point type definition be CONSTHIGH type and
CONSTLOW type, remaining is defined as SOURCE type or SINK type；CONNECTION type block is one group of input
The connection relationship of output is defined as a CHAN point, and connection relationship can correspond to multiple input ports and an output port.
Definition of the BRIDGE type block without available point, during establishing interconnection resource figure effect for establish two available points it
Between indirect connection relationship.
" FUNCTION " is for modules such as representation function modules, such as low and high level module, logical block (LE).
" CONNECTION " is for describing reconfigurable interconnection attribute modules, such as switch enclosure (SwitchBox, SB), connection
The modules such as box (ConnectionBox, CB).
" BRIDGE " is indicated to be directly connected to the modules such as effort module, such as resistance, phase inverter, buffer, be recognized for describing
It is unrelated with interconnection resource figure (RRG) is established for remaining function type module in netlist, it does not need to carry out wiring attribute definition.Effectively
Point is the node in the digraph of storage wire resource map (RRG) information.Available point is divided into five kinds by the present invention by type, point
It is not SOURCE type, SINK type, CONSTHIGH type, CONSTLOW type and CHAN type.
The available point that module (module) is established is substantially one-to-one with the physical port of module, and effective vertex type takes
Certainly in the cloth line attribute of the physical port attribute of mapping and locating module.
The present invention defines base with the mode for creating ROUTING sentence under MODULE sentence in arc_guide.xml file
Each module (module) in the net meter file of this module (Tile) should establish available point information, module name MODULE
It is specified in " name " attribute of sentence, ROUTING sentence is used to describe the available point information that the module needs to create, multiple effective
Point is described with multiple ROUTING sentences, the currently active vertex type of " key " attribute description in each ROUTING sentence and effective
The id of point, the corresponding port list of the currently active point of " value " attribute description.
S140, available point is divided by type, to truly have effect vertex type, effective vertex type includes SOURCE class
Type, SINK type, CONSTHIGH type, CONSTLOW type and CHAN type.
Wherein, SOURCE type available point is the starting point of routing path, can be by the output port of FUNCTION type block
It is defined as this type；SINK type available point is the terminal of routing path, can determine the input port of FUNCTION type block
Justice is at this type；CONSTHIGH type available point refers exclusively to fixed high level, is the starting point of routing path, by high level module
Output port is defined as this type；CONSTLOW type refers exclusively to fixed low level, is the terminal of routing path, by low level mould
The output port of block is defined as this type；CHAN type available point is the intermediate node on routing path, by CONNECTION class
One group of connection of pattern block is defined as a CHAN type available point, and CHAN type available point is relatively special, be not it is corresponding certain
A port, but corresponding one group of connection relationship, so the port that is related to while including input and output.
S150, the port connection relationship of example is called to determine effective edge based in the basic module.
S160, the available point and effective edge are stored into the data structure of digraph, to establish interconnection resource figure
(RRG) information.
(2) basic module (Tile) connection relationship models.
Determine the input file for establishing the selection of basic module (Tile) link information, the input file includes basic module
(Tile) refer to the formatted file of current series (Series) other basic module (Tile) connection relationships, the connection relationship
It is connected between the current output port (Outport) of basic module (Tile) and the input port (Inport) of other basic modules
Relationship.
The embodiment of the present invention establishes the input file that basic module (Tile) link information selects to describe basic module
(Tile) with the xml formatted file of current series (Series) other basic module (Tile) connection relationships.Connection relationship refers to
It is connected between the current output port (Outport) of basic module (Tile) and the input port (Inport) of other basic modules
Relationship.For specifying current basic module (Tile) name, OUTPORT sentence successively arranges " name " attribute of the TILE sentence of file
The connection of all output ports (Outport) relevant to routing path of current basic module (Tile) out, OUTPORT
It include port name, port width attribute information in sentence, CONNEXION sentence describes output port (Outport) and can connect
One group of connection relationship of the input port (Inport) of the basic module (Tile) connect, attribute successively describe the basic module of connection
(Tile) relative co-ordinate information, type information, input port name, port width information.
S200, the set for constituting the basic module of FPGA device is determined according to the FPGA series information.
After the affiliated FPGA of selected creation device serial (Series), it is equivalent to and obtains the basic of composition FPGA device
The set of module (Tile) need to only provide the arrangement information of customization FPGA device, " can both splice " and go out a complete FPGA device
Part wire structures, and obtain FPGA device interconnection resource figure (RRG).FPGA device arrangement information includes chip-scale and every
The type information for the basic module (Tile) placed under a coordinate position.
S300, the wire structures information that the FPGA device is determined based on the set of the basic module.
Wherein, which may include following sub-step:
S310, the input file for determining fpga chip arrangement information.
S320, FPGA device arrangement information is obtained according to the input file.
S330, correspondence is chosen from series information library according to basic module (Tile) type under each coordinate in arrangement information
Basic module (Tile) simultaneously obtains its wire structures.
S340, interconnection resource figure (RRG) information that complete FPGA device is obtained based on the wire structures.
Wherein, which may include following sub-step:
S3401, available point and effective edge are copied to FPGA device interconnection resource figure (RRG) digraph.
S3402, determine FPGA device whole coordinate position, with obtain FPGA device interconnection resource figure (RRG) it is oriented
Whole available points and effective edge in figure.
The link information of basic module (Tile), which is established, in S3403, serial (Series) information of foundation FPGA determines connection
Relationship.
Binding relationship between S3404, foundation port and available point, converts connection relationship between port between available point
Connection.
S3405, interconnection resource figure (RRG) information that complete FPGA device is constructed based on connection between the available point.
The input file for describing fpga chip arrangement information is appointed as XML format by the present invention, and file is entitled
arrangement.xml.DEVICE sentence is for describing FPGA device correlation attribute information, wherein " series " attribute is specified
The affiliated FPGA of device is serial (Series), and the FPGA device name of the specified customization of " name " attribute, " size_x " attribute specifies device
Horizontal direction scale, " size_y " attribute specify device vertical direction scale.Under DEVICE sentence includes multiple TILE sentences
The Tile type called for outlines device.TILE sentence includes " name " attribute for specified used basic mould
Block (Tile) type.It is used to describe the example information of basic module under TILE sentence comprising multiple TILE_INS sentences.TILE_
INS sentence " loc_x, loc_y " attribute are used to specify the coordinate position on chip of Tile example.
After obtaining FPGA device arrangement information, according in arrangement information under each coordinate basic module (Tile) type from being
Choose corresponding basic module (Tile) in column information library and obtain its wire structures, i.e., comprising basic module (Tile) available point and
The digraph of effective edge all copies to available point and effective edge in the digraph of interconnection resource figure (RRG) of FPGA device,
After traversal terminates FPGA device whole coordinate position, it can obtain in the digraph of interconnection resource figure (RRG) of FPGA device
Whole available points and effective edge.Then the link information according to basic module (Tile) in serial (Series) information of FPGA is established
The example (instance) of basic module (Tile) under FPGA device whole coordinate position and surrounding basic module (Tile)
Connection relationship between the port of example (Instance), then according to binding relationship between port and available point, will connect between port
It connects transformation to connect between available point, is finally obtained with interconnection resource figure (RRG) information of complete FPGA device.
Lower section code is that the link information of basic module (Tile) of the invention illustrates code.
" name " attribute of TILE sentence is BLK as known to code, is shown to be configurable logic block
The definition of (ConfigurableLogic Block, CLB) type and the link information of current series Tile.First OUTPORT
" name " attribute of sentence is " blk_cout ", show describe CLB " blk_cout " output port and current series its
The link information of his Tile, " width " attribute are 1 bit wide for describing " blk_cout " output port.Current OUTPORT language
Sentence under have a CONNEXION sentence, show under current series, " blk_cout " output port of CLB with other modules
Only a kind of connection type.The type of the Tile of the specified connection of " type " attribute of CONNEXION sentence, " delta_x,
Delta_y " attribute respectively specifies that the relative coordinate in chip coordinate system of connection BLK module and current block, " port_
The input port name of the specified connection of name " attribute, therefore current CONNEXION sentence sentence describes the " blk_ of CLB
Cout " output port and relative position are " blk_cin " input port connection (relative coordinates of the BLK type block of (0, -1)
(0, -1) indicate that horizontal direction is constant, vertical direction reduces the position of a coordinate).Similarly, Article 2 OUTPORT sentence describes
Be BLK " channel_bottomlink " output port link information, as figure shows, current OUTPORT sentence includes
Three CONNEXION sentences show to share three groups of link informations in the current series (Series), and first group is and relative coordinate
For the connection of the input port " toplink " of the CLB of (0, -1) position, it is (0, -1) position that second group, which is with relative coordinate,
The connection of the input port " dlink " of IOB_B, third group are the input ports with the IOB_B that relative coordinate is (- 1, -1) position
The connection of " rdlink ".It should be noted that link information described herein is all possibility of current series (Series)
The case where connection, depending on where actual use organizes link information according to the actual situation.
Fig. 3 is the coordinate system schematic diagram on the chip that the present invention defines.Using the chip lower left corner as coordinate origin, coordinate refers to
It is set to (0,0), is horizontally to the right X-axis positive direction, is vertically upward Y-axis positive direction.Assuming that core horizontal direction scale is
Scale_x, vertical direction scale is scale_y, since core surrounding has input/output module, so chip X-coordinate maximum value
For scale_x+1, Y-coordinate maximum value scale_y+1.
Lower section code is that description of the invention device arrangement message file shows code.
File includes a DEVICE sentence, and obtaining device generic series by the attribute value of DEVICE sentence is iStar-
07, device entitled iStar-07-IP, device scale 8*8.Include altogether five TILE sentences under DEVICE sentence, passes through TILE
Current device known to " name " attribute of sentence calls five kinds of TILE types, be respectively " BLK ", " IOB_T ", " IOB_B ",
" IOB_L ", " IOB_R " respectively represents configuration logic (CLB), top input/output module, lower part input/output module, a left side
Portion's input/output module, right part input/output module.It wherein include a TILE_INS sentence under the corresponding TILE sentence of BLK,
" loc_x " attribute value of TILE_INS sentence is " 1:8 ", indicates that the coordinate range of X-direction is 1 to 8, similarly, the coordinate of Y-direction
Range is 1 to 8, describes a zonal coordinate range, has instantiated 64 Tile examples altogether.The corresponding TILE of IOB_T
Include a TILE_INS sentence under sentence, " loc_x " attribute value of TILE_INS sentence be " 1,3,5,7 ", indicate X-direction
Coordinate value includes 1,3,5,7, and the coordinate value of Y-direction is 9, describes multiple discrete coordinate positions, has instantiated (1,9) altogether,
(3,9), (5,9), the Tile example of (7,9) four coordinate positions.
Fig. 4 is device arrangement result schematic diagram.Device core part includes 64 BLK examples, and device periphery includes 16 altogether
A IO example.
The pseudocode of lower section code generating device interconnection resource figure process of the invention.
If local_graph is the digraph for describing the interconnection resource figure (RRG) of current device, it is initially empty.The first step,
Each two-dimensional coordinate position on chip is looped through by for, one of coordinate is obtained and is set as (i, j).It is arranged by device
Information DeviceArrangement obtains the Tile type tile_name under the position (i, j), searches device by tile_name
Generic series library series library (having built up in advance) obtains the interconnection resource figure information routing for storing corresponding Tile
The digraph sub_graph of resource graph.Being recycled in successively traversal digraph sub_graph by for again all has
Point node and effective edge edge is imitated, obtained whole available point effective edges are all copied into having for memory device interconnection resource figure
Into figure local_graph.Second step loops through each two-dimensional coordinate position on chip again by for, obtains wherein one
A coordinate is set as (i, j).The same Tile class arranged under information DeviceArrangement acquisition position (i, j) by device
Type tile_name searches device generic series library series library (having built up in advance) by tile_name, is deposited
Store up the link information tile_conn of corresponding Tile.The single output port of the Tile in tile_conn is looped through by for
Link information port_conn.Output port name current_port_name is being obtained from port_conn information, in local_
The some available point source_nodes for having connection signal with current_port_name are searched in graph.Again from port_
Conn information obtains current output port current_port_name a series of link information a list under current series
Ofconnection loops through a list ofconnection by for, obtains one of link information conn.From even
Meet the input port name connected_port_name connected in information conn, similarly in local_graph search with
Connected_port_name has some available point target_nodes of connection signal.It is established finally, being recycled by for
In source_nodes set in each available point s_node and target_nodes set between each available point t_node
Effective edge edge establishes the connection of the available point two-by-two in source_nodes and target_nodes, finally obtained
Local_graph is the connection relationship for including whole available points.
Fig. 5 is the schematic diagram of generating device interconnection resource figure process of the invention.The pseudocode description of Zuo Bantu description
The interconnection resource figure of each Tile is corresponded into the wiring money that available point and effective edge in digraph copy to Device in the first step
Process in the figure of source.Right half figure, which describes to establish in second step, establishes having for adjacent Tile by the link information between Tile
Connection procedure between effect point.
The present invention provides a kind of software modeling methods for customized FPGA wire structures.The wiring of this FPGA
The software modeling method of structure is that the fpga chip structure based on current main-stream is essentially all compiling by several reuses
Journey module composition, these programmable modules reused are referred to as basic module (Tile).Provided by the invention is exactly base
Information is arranged in the FPGA device of serial (Series) information of FPGA and customization to establish entire fpga chip interconnection resource figure
A kind of method of information (Routing Resource Graph, RRG) does not need to generate the complete domain structure of fpga chip
Or netlist information, the wire structures information (Routing of desired FPGA device directly can be obtained by " splicing " mode
Resource Graph, RRG).
Embodiment two
Fig. 6 is a kind of model building device of wire structures provided by Embodiment 2 of the present invention, comprising:
Information determination module 21, for determining that FPGA series information, the FPGA series information include FPGA basic module
Wire structures information and FPGA basic module interconnection information；
Gather determining module 22, for determining the collection for constituting the basic module of FPGA device according to the FPGA series information
It closes；
Information establishes module 23, determines that the wire structures of the FPGA device are believed for the set based on the basic module
Breath.
The embodiment of the invention provides a kind of software modeling methods for customized FPGA wire structures.This FPGA
The software modeling methods of wire structures be the fpga chip structure based on current main-stream be essentially all by several reuses
Programmable module constitute, these reuse programmable modules be referred to as basic module (Tile).Basic module
(Tile) it is through basic conception of the invention.The wire structures information of basic module (Tile) and the summation of interconnection information are constituted
Serial (Series) information of FPGA.The FPGA provided by the invention for being namely based on serial (Series) information of FPGA and customization
Device arranges information to establish the one of entire fpga chip interconnection resource figure information (Routing Resource Graph, RRG)
Kind method is not needed to generate the complete domain structure of fpga chip or netlist information, can directly be obtained by " splicing " mode
The wire structures information (Routing Resource Graph, RRG) of desired FPGA device.
On this basis, the information determination module 21 further include:
Net meter file determines submodule, for determining the net meter file of basic module；
Input information determines submodule, for parsing the net meter file to determine basic module wire structures software modeling
Input information.
On this basis, the parsing net meter file is believed with the input for determining basic module wire structures software modeling
Breath, comprising:
The net meter file is parsed；
Using the parsing result of the parsing as the input information of basic module wire structures software modeling, the input letter
Breath includes the port information of basic module, gauze information, module instance information.
On this basis, the parsing net meter file is believed with the input for determining basic module wire structures software modeling
After breath, further includes:
Functions of modules by cloth line attribute according to basic module divides, to determine module class belonging to a basic module
Type, and then determine the cloth line attribute of the basic module, the module type includes top-level module, representation function module, retouches
It states reconfigurable interconnection attribute modules and is directly connected to effort module；
Available point is divided by type, to truly have effect vertex type, effective vertex type include SOURCE type,
SINK type, CONSTHIGH type, CONSTLOW type and CHAN type；
The port connection relationship of example is called to determine effective edge based in the basic module；
By the available point and effective edge storage into the data structure of digraph, to establish interconnection resource figure information.
On this basis, the functions of modules by cloth line attribute according to basic module divides, to determine that one is basic
Module type belonging to module, and then determine the cloth line attribute of the basic module, comprising:
The wiring attribute information of each module of the appearance in net meter file is defined,
The functional attributes of judgment module；
When the functional attributes belong to the first attribute, determine that the module type of the module is to determine top-level module；
When the functional attributes belong to the second attribute, determine that the module type of the module is representation function module；
When the functional attributes belong to third attribute, determine the module type of the module for description reconfigurable interconnection
Matter module；
When the functional attributes belong to four attributes, determine that the module type of the module is to be directly connected to effect mould
Block.
On this basis, effective vertex type includes at least following one kind:
SOURCE type, the SOURCE type available point are the starting point of routing path；
SINK type, the SINK type available point are the terminal of routing path；
CONSTHIGH type, the CONSTHIGH type available point are fixed high level, are the starting point of routing path；
CONSTLOW type, the CONSTLOW type available point are fixed low level, are the terminal of routing path；
CHAN type, the CHAN type available point are the intermediate node on routing path, the CHAN type available point
Corresponding one group of connection relationship, one group of connection relationship are one group of connection of CONNECTION type block.
On this basis, serial (Series) information of the determining FPGA, comprising:
Determine the input file for establishing the selection of basic module link information, the input file includes basic module and current
The formatted file of other serial basic module connection relationships, it is described connect relationship refer to current basic module output port and other
Connection relationship between the input port of basic module
On this basis, the wire structures information that the FPGA device is determined based on the set of the basic module,
Include:
Determine the input file of fpga chip arrangement information；
FPGA device arrangement information is obtained according to the input file；
Corresponding basic module is chosen from series information library simultaneously according to basic module type under each coordinate in arrangement information
Obtain its wire structures；
Interconnection resource figure (RRG) information of complete FPGA device is obtained based on the wire structures.
On this basis, the wire structures include the digraph of basic module available point and effective edge；
The interconnection resource figure information that complete FPGA device is obtained based on the wire structures, comprising:
Available point and effective edge are copied to the digraph of the interconnection resource figure of FPGA device；
Determine FPGA device whole coordinate position, in the digraph to obtain the interconnection resource figure of FPGA device all effectively
Point and effective edge；
Link information according to basic module in FPGA series information, which is established, determines that connection relationship, the connection relationship are
Connection relationship between the port of the example of the example and basic module of basic module under FPGA device whole coordinate position；
According to binding relationship between port and available point, converts connection relationship between port between available point and connect；
Interconnection resource figure (RRG) information of complete FPGA device is constructed based on connection between the available point.
A kind of model building device of wire structures provided in this embodiment can be used for executing a kind of wiring of the offer of embodiment one
The modeling method of structure has corresponding function and beneficial effect.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of modeling method of wire structures characterized by comprising
Determine that FPGA series information, the FPGA series information include FPGA basic module wire structures information and the basic mould of FPGA
Block interconnection information；
The set for constituting the basic module of FPGA device is determined according to the FPGA series information；
The wire structures information of the FPGA device is determined based on the set of the basic module.
2. the method according to claim 1, wherein the determining FPGA series information, comprising:
Determine the net meter file of basic module；
The net meter file is parsed to determine the input information of basic module wire structures software modeling.
3. according to the method described in claim 2, it is characterized in that, the parsing net meter file is to determine basic module cloth
The input information of cable architecture software modeling, comprising:
The net meter file is parsed；
Using the parsing result of the parsing as the input information of basic module wire structures software modeling, the input packet
Include port information, the gauze information, module instance information of basic module.
4. according to the method in claim 2 or 3, which is characterized in that the parsing net meter file is with the basic mould of determination
After the input information of block wire structures software modeling, further includes:
Functions of modules by cloth line attribute according to basic module divides, to determine module type belonging to a basic module,
And then determining the cloth line attribute of the basic module, the module type includes that top-level module, representation function module, description can
Programming connects attribute modules and is directly connected to effort module；
Available point is divided by type, to truly have effect vertex type, effective vertex type includes SOURCE type, SINK class
Type, CONSTHIGH type, CONSTLOW type and CHAN type；
The port connection relationship of example is called to determine effective edge based in the basic module；
By the available point and effective edge storage into the data structure of digraph, to establish interconnection resource figure information.
5. according to the method described in claim 4, it is characterized in that, effective vertex type includes at least following one kind:
SOURCE type, the SOURCE type available point are the starting point of routing path；
SINK type, the SINK type available point are the terminal of routing path；
CONSTHIGH type, the CONSTHIGH type available point are fixed high level, are the starting point of routing path；
CONSTLOW type, the CONSTLOW type available point are fixed low level, are the terminal of routing path；
CHAN type, the CHAN type available point are the intermediate node on routing path, and the CHAN type available point is corresponding
One group of connection relationship, one group of connection relationship are one group of connection of CONNECTION type block.
6. the method according to claim 1, wherein the determining FPGA series information, comprising:
Determine the input file for establishing the selection of basic module link information, the input file includes basic module and current series
The formatted file of other basic module connection relationships, the relationship that connects refer to that the output port of current basic module is basic with other
Connection relationship between the input port of module.
7. the method according to claim 1, wherein described in the set based on the basic module is determining
The wire structures information of FPGA device, comprising:
Determine the input file of fpga chip arrangement information；
FPGA device arrangement information is obtained according to the input file；
Corresponding basic module is chosen from series information library according to basic module type under each coordinate in arrangement information and is obtained
Its wire structures；
The interconnection resource figure information of complete FPGA device is obtained based on the wire structures.
8. the method according to the description of claim 7 is characterized in that the wire structures are comprising basic module available point and effectively
The digraph on side；
The interconnection resource figure information that complete FPGA device is obtained based on the wire structures, comprising:
Available point and effective edge are copied to the digraph of the interconnection resource figure of FPGA device；
Determine FPGA device whole coordinate position, in the digraph to obtain the interconnection resource figure of FPGA device whole available points and
Effective edge；
Link information according to basic module in FPGA series information, which is established, determines connection relationship, and the connection relationship is FPGA device
Connection relationship between the port of the example of the example and basic module of basic module under part whole coordinate position；
According to binding relationship between port and available point, converts connection relationship between port between available point and connect；
The interconnection resource figure information of complete FPGA device is constructed based on connection between the available point.
9. a kind of model building device of wire structures characterized by comprising
Information determination module, for determining that FPGA series information, the FPGA series information include FPGA basic module wire bond
Structure information and FPGA basic module interconnection information；
Gather determining module, for determining the set for constituting the basic module of FPGA device according to the FPGA series information；
Information establishes module, and the wire structures information of the FPGA device is determined for the set based on the basic module.
10. device according to claim 9, which is characterized in that the information determination module includes:
Net meter file determines submodule, for determining the net meter file of basic module；
Input information determines submodule, for parsing the net meter file to determine the defeated of basic module wire structures software modeling
Enter information.
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| CN201910759282.6A CN110472340B (en) | 2019-08-16 | 2019-08-16 | Modeling method and device for wiring structure |
| PCT/CN2020/079332 WO2021031554A1 (en) | 2019-08-16 | 2020-03-13 | Method and device for modeling routing structure |
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| CN201910759282.6A CN110472340B (en) | 2019-08-16 | 2019-08-16 | Modeling method and device for wiring structure |
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| CN110472340B CN110472340B (en) | 2023-11-03 |
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| CN111414725A (en) * | 2020-03-13 | 2020-07-14 | 中科亿海微电子科技（苏州）有限公司 | Software wiring structure modeling method and device for FPGA (field programmable Gate array) capable of being dynamically expanded |
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| WO2021031554A1 (en) * | 2019-08-16 | 2021-02-25 | 中科亿海微电子科技（苏州）有限公司 | Method and device for modeling routing structure |
| WO2021169303A1 (en) * | 2020-02-28 | 2021-09-02 | 福州大学 | Multi-stage fpga wiring method for optimizing time division multiplexing technology |
| CN114282474A (en) * | 2021-11-16 | 2022-04-05 | 山东芯慧微电子科技有限公司 | FPGA wiring resource data compression method |
| CN115204103A (en) * | 2022-09-19 | 2022-10-18 | 中科亿海微电子科技（苏州）有限公司 | Fast wiring method and device based on CB classification |
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Also Published As
| Publication number | Publication date |
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| CN110472340B (en) | 2023-11-03 |
| WO2021031554A1 (en) | 2021-02-25 |
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