CN114282474A - FPGA wiring resource data compression method - Google Patents
FPGA wiring resource data compression method Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention relates to a method for compressing FPGA wiring resource data, which comprises the following steps: defining an object, defining an array, searching through key value pairs and the like. The FPGA wiring resource data compression method provided by the invention takes the Type information as an index and searches for Wire information; therefore, the occupation of the memory can be greatly reduced. Memory usage is also significantly slowed as FPGA scales grow.
Description
Technical Field
The invention relates to a method for compressing FPGA wiring resource data, and belongs to the technical field of integrated circuit design.
Background
At present, ten million gate-level FPGAs are mainstream, and the wiring resource scale is large. For example, a total of 32568 Tile 95t in the xilinx v5 series; each Tile has hundreds to thousands of different interconnection points (Wire points), tiles and PIPs in the whole FPGA form a huge graph, and the tiles are all communicated. Therefore, the corresponding routing software is required to quickly find the most available path, and meanwhile, more severe requirements are provided for modeling of routing resources.
In the layout and routing software, if each Tile in the FPGA is mapped into an object instance, a large memory overhead is caused. Assuming that a Wire object contains string and bolt flag bits, it is estimated that each Tile contains 700 wires and id of a string type. In a 64-bit operating system, the string variable is 32 bytes in size and the bootean variable is 1byte in size. Taking v 595 t as an example, the memory overhead for instantiating all tiles is about 700 MB; and the memory overhead of the actual running of the software can exceed 1GB by adding intermediate variables in the process of laying out and wiring. For a larger 240t, the memory overhead of the routing resources may approach 2 GB.
In the actual production process, considering the factors of time delay and power consumption, the wiring resource occupied by the circuit designed by the user is usually lower than 50% of the total wiring resource. Therefore, in the wiring process, the large memory overhead means the waste of memory resources.
Disclosure of Invention
The invention aims to solve the technical problems that: the defects of the technology are overcome, and a modeling method is provided, so that the wiring resources are compressed to a certain extent on the premise of not reducing the query speed, and the aim of saving the memory is fulfilled.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: an FPGA wiring resource data compression method comprises the following steps:
step 1: defining an object Tile, wherein the coordinate, the binary bit stream wireUsage and the type index TileTypeIndex of each Tile in the FPGA are stored;
step 2: defining a two-dimensional array TileMap, wherein each array element corresponds to the coordinate of each TILE in the FPGA one to one;
and step 3: defining an array WirelList, and identifying interconnection information of tiles and channels;
and 4, step 4: defining an array TileTypeToWirelList, and storing the WirelLists corresponding to all TileTypes;
and 5: the position of Tile and the position of Wire endpoint can be uniquely positioned through the key-value pair TW; through a group of key value pairs TW, a metal interconnection line can be uniquely determined;
step 6: the WireaUsage length in the object Tile is consistent with the WirelList length, and the initial values are all 0; in the wiring process, when a certain Wire of the Tile is selected, the corresponding binary position in the WireaUage is set to be 1; indicating that the current Wire is occupied.
The scheme is further improved in that: the memory estimation formula under a 64-bit system is:
wherein L iswireListDenotes the length, L, of a wireListTileTypeListDenotes the length of TileTypeList, NTileIs the total number of tiles.
The scheme is further improved in that: searching information by using an array subscript; the lookup time complexity is O (1).
The scheme is further improved in that: the same type of Tile, the coordinates may be different but the Wire information is identical, and a certain Wire endpoint of the Tile may be indexed by its WireList subscript.
The scheme is further improved in that: the type index TileTypeIndex in step 1 is an index of the Tile type in the array.
The FPGA wiring resource data compression method is suitable for island-type FPGAs, the module structure inside the FPGA is more regular and suitable for compression, and tiles can be classified according to function and position distribution; because the Type information and the Wire information have strong association and the Wire information occupies a memory, the Wire information is shared by the tiles of the same Type, and the Tile object only stores a small number of fields such as coordinates, types and the like. Searching for Wire information by taking the Type information as an index; therefore, the occupation of the memory can be greatly reduced. Memory usage is also significantly slowed as FPGA scales grow.
Detailed Description
Examples
The FPGA wiring resource data compression method of the present embodiment is suitable for island FPGAs, and therefore, the FPGA type needs to be determined first. After the FPGA hardware framework information is acquired, whether the FPGA hardware framework information is an island type is judged, and if the FPGA hardware framework information is the island type, the method continues. Defining basic classes of Tile, TileMap, Wire and WirelList according to requirements; define API GetSegment (TileIndex, WireIndex), GetSource (WireIndex), GetSinks (WireIndex), GetWireInfo (TileTypeIndex).
The wiring algorithm can frequently search the Tile and Wire information; so this scheme uses array subscripts to lookup information. The lookup time complexity is O (1).
Modeling a routing resource as follows:
step 1: defining an object Tile, wherein the coordinate, the binary bit stream wireUsage and the type index TileTypeIndex of each Tile in the FPGA are stored;
step 2: defining a two-dimensional array TileMap, wherein each array element corresponds to the coordinate of each TILE in the FPGA one to one;
and step 3: defining an array WirelList, and identifying interconnection information of tiles and channels; the coordinates of the tiles of the same type may be different but the Wire information is completely the same, and a certain Wire endpoint of the Tile may be indexed by its WireList subscript (WireIndex);
and 4, step 4: defining an array TileTypeToWirelList, and storing the WirelLists corresponding to all TileTypes; the type index TileTypeIndex in step 1 is the index of the Tile type in the array.
And 5: the position of the Tile and the position of the Wire endpoint can be uniquely located through a key-value pair TW (WireIndex @ Tile); through a group of key value pairs TW, a metal interconnection line can be uniquely determined; for example, Segment [ TW0(ES2BEG0@ INT _ X5Y10), TW1(ES2MID0@ INT _ X6Y10), TW2(ES2END0@ INT _ X6Y9) ] represents an interconnect where a Begin node is located at INT _ X5Y10, a Middle node is located at INT _ X6Y10, and an END node is located at INT _ X6Y 9;
step 6: the WireaUsage length in the object Tile is consistent with the WirelList length, and the initial values are all 0; in the wiring process, when a certain Wire of the Tile is selected, the corresponding binary position in the WireaUage is set to be 1; indicating that the current Wire is occupied.
The memory estimation formula under a 64-bit system is:
wherein L iswireListDenotes the length, L, of a wireListTileTypeListDenotes the length of TileTypeList, NTileIs the total number of tiles. For v 595 t as an example, the total number of tiles is 32568; the number of Tile types is 111; estimating the average wireList length to be 700; the memory occupied by the wiring resources is calculated by substituting the formula to be about 6.2MB, and the memory occupation is greatly reduced compared with the prior method for establishing the WirelList for each Tile.
The present invention is not limited to the above-described embodiments. All technical solutions formed by equivalent substitutions fall within the protection scope of the claims of the present invention.
Claims (5)
1. An FPGA wiring resource data compression method is characterized by comprising the following steps:
step 1: defining an object Tile, wherein the coordinate, the binary bit stream wireUsage and the type index TileTypeIndex of each Tile in the FPGA are stored;
step 2: defining a two-dimensional array TileMap, wherein each array element corresponds to the coordinate of each TILE in the FPGA one to one;
and step 3: defining an array WirelList, and identifying interconnection information of tiles and channels;
and 4, step 4: defining an array TileTypeToWirelList, and storing the WirelLists corresponding to all TileTypes;
and 5: the position of Tile and the position of Wire endpoint can be uniquely positioned through the key-value pair TW; through a group of key value pairs TW, a metal interconnection line can be uniquely determined;
step 6: the WireaUsage length in the object Tile is consistent with the WirelList length, and the initial values are all 0; in the wiring process, when a certain Wire of the Tile is selected, the corresponding binary position in the WireaUage is set to be 1; indicating that the current Wire is occupied.
2. The FPGA wiring resource data compression approach of claim 1, wherein: the memory estimation formula under a 64-bit system is:
wherein L iswireListDenotes the length, L, of a wireListTileTypeListDenotes the length of TileTypeList, NTileIs the total number of tiles.
3. The FPGA wiring resource data compression approach of claim 1, wherein: searching information by using an array subscript; the lookup time complexity is O (1).
4. The FPGA wiring resource data compression approach of claim 1, wherein: the same type of Tile, the coordinates may be different but the Wire information is identical, and a certain Wire endpoint of the Tile may be indexed by its WireList subscript.
5. The FPGA wiring resource data compression approach of claim 1, wherein: the type index TileTypeIndex in step 1 is an index of the Tile type in the array.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366029A (en) * | 2012-03-31 | 2013-10-23 | 中国科学院微电子研究所 | On-site programmable gate array chip layout method |
| CN110472340A (en) * | 2019-08-16 | 2019-11-19 | 中科亿海微电子科技（苏州）有限公司 | A kind of modeling method and device of wire structures |
| CN111414725A (en) * | 2020-03-13 | 2020-07-14 | 中科亿海微电子科技（苏州）有限公司 | Software wiring structure modeling method and device for FPGA (field programmable Gate array) capable of being dynamically expanded |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366029A (en) * | 2012-03-31 | 2013-10-23 | 中国科学院微电子研究所 | On-site programmable gate array chip layout method |
| CN110472340A (en) * | 2019-08-16 | 2019-11-19 | 中科亿海微电子科技（苏州）有限公司 | A kind of modeling method and device of wire structures |
| CN111414725A (en) * | 2020-03-13 | 2020-07-14 | 中科亿海微电子科技（苏州）有限公司 | Software wiring structure modeling method and device for FPGA (field programmable Gate array) capable of being dynamically expanded |
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Denomination of invention: A Data Compression Method for FPGA Cabling Resources Effective date of registration: 20231226 Granted publication date: 20220809 Pledgee: Rizhao Bank Co.,Ltd. Jinan Branch Pledgor: Shandong Xinhui Microelectronics Technology Co.,Ltd. Registration number: Y2023370000137 |
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