CN115204103B - Fast wiring method and device based on CB classification - Google Patents

Fast wiring method and device based on CB classification Download PDF

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CN115204103B
CN115204103B CN202211134525.5A CN202211134525A CN115204103B CN 115204103 B CN115204103 B CN 115204103B CN 202211134525 A CN202211134525 A CN 202211134525A CN 115204103 B CN115204103 B CN 115204103B
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resource units
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cbs
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CN115204103A (en
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李玉洁
刘洋
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Ehiway Microelectronic Science And Technology Suzhou Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

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Abstract

The invention provides a fast wiring method and a fast wiring device based on CB classification, which classify different ports of each CB in a logic cluster connected to a logic resource unit and classify the end point type of a signal, so that the end point type of the signal corresponds to the port type of the CB connected to the logic resource unit in the wiring process, and the selected CB is not selected any more.

Description

Fast wiring method and device based on CB classification
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a fast wiring method and device based on CB classification.
Background
The FPGA is provided with a plurality of configurable logic units, and one or more logic units are interconnected through switches, so that a specific circuit function is realized. The FPGA has abundant hardware resources, strong parallel processing and flexible reconfigurable capability. The method is not only suitable for the field of semi-customized circuits, but also is widely applied in many fields such as data processing, communication, network, medical treatment, image acquisition and the like.
With the expansion of the size of the FPGA chip, the requirement for the wiring speed is also higher and higher. The time consumption of routing mainly consists in the competition of different nets for routing resources. To avoid congestion, it is currently common practice to route the wiring through using a strategy of route negotiation using cost marking for used points.
Disclosure of Invention
The invention aims to solve the technical problem of how to quickly perform wiring, and provides a quick wiring method and device based on CB classification.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a fast wiring method based on CB classification comprises the following steps:
step 1, obtaining a netlist file after a user design circuit is synthesized;
step 2: analyzing the netlist file to obtain logic resources needed by the user circuit;
and step 3: packing a specified amount of logic resources of the same kind into a logic cluster;
and 4, step 4: mapping a plurality of logic clusters formed by a plurality of packed different logic resources to the physical resources of the FPGA for layout, and obtaining the position and the coordinate from a signal starting point to a signal ending point;
and 5: when each net in a user designed circuit is wired, sequentially wiring each logic cluster, judging whether CBs on one logic cluster are in non-full connection, if so, entering port types of all logic resource units in the logic cluster according to the end point of a current signal, and selecting the CBs corresponding to the corresponding CB types for connecting, wherein the CB types are used for classifying the CBs in the logic clusters according to the port types of the logic resource units in the CB connection logic cluster;
step 6: if there is net needed to be wired, and the CB in a certain logic cluster needs to be used in the process of wiring the net, but all the CBs in the logic cluster are selected, a user is prompted to fail to wire.
Further, the step 5 of classifying the CBs in the logical cluster according to the port types of the logical resource units in the logical cluster connected by the CBs means:
the CB is a connection-box connecting the outside of the logic cluster to the ports of the logic resource units, a plurality of CBs are arranged on one logic cluster, one CB is connected to a plurality of ports appointed by all the logic resource units in the logic cluster, and the CBs are divided into different types according to the difference of the ports of the logical resource units connected by the CBs.
Further, the step 5 of entering the port types of all the logical resource units in the logical cluster by the end point of the current signal refers to outputting a signal to several ports of the logical resource units in the logical cluster, and corresponding to several port types of the CB connected to the logical resource units in the logical cluster, if the port type of the end point of the signal output to the logical resource units is consistent with the several port types of the CB connected to the logical resource units, selecting the CB of the type for net wiring.
Further, different CB types are formed into a CB type set, each CB type has a plurality of available CBs, each CB of one type is selected for wiring, the CB is deleted from the CB type set, and when the CBs of the type are all deleted, the CB type is deleted.
Further, in step 5, when the CB corresponding to the corresponding CB type is selected, if there is no CB type meeting the requirement, finding out the CB combinations in the CB types meeting the requirement in the minimum number from the CB type set, and combining the CB combinations together to meet the connection requirement.
The invention also provides a rapid wiring device based on CB classification, which comprises the following modules:
a netlist file obtaining module: the netlist file is used for obtaining a netlist file after a user design circuit is synthesized;
an analysis module: the netlist file is used for analyzing the netlist file to obtain logic resources needed by the user circuit;
a packaging module: the system is used for packing a specified number of logic resources of the same kind into a logic cluster;
a layout module: the system comprises a plurality of logic clusters, a plurality of FPGA and a plurality of logic resources, wherein the logic clusters are formed by a plurality of packed different logic resources and are mapped to physical resources of the FPGA for layout, and the positions and coordinates from a signal starting point to a signal finishing point are obtained;
a wiring module: the device comprises a plurality of logic clusters, a plurality of CB groups and a plurality of ports, wherein the CB groups are used for sequentially wiring each logic cluster when each net in a user design circuit is wired, judging whether the CB on one logic cluster is in non-full connection, if so, entering the port types of all logic resource units in the logic cluster according to the terminal point of a current signal, and selecting the CB corresponding to the corresponding CB type for wiring, wherein the CB type is used for classifying the CB in the logic cluster according to the port type of the logic resource unit in the CB connection logic cluster;
a prompt module: when there is a net that needs to be wired, if the CB in a certain logic cluster needs to be used in the process of wiring the net, but all the CBs in the logic cluster are selected, a user is prompted to fail to wire.
By adopting the technical scheme, the invention has the following beneficial effects:
according to the rapid wiring method and device based on CB classification provided by the invention, different ports of each CB in a logic cluster connected to a logic resource unit are classified, and different port types of signals output to the logic resource unit are also classified, so that the terminal point of the signal corresponds to the port type of the logic resource unit connected to the CB in the wiring process, and the selected CB is not selected any more; by using the method, the CB used by the signal can be reasonably distributed in advance, and the call completing rate is improved.
Drawings
FIG. 1 is a flow chart of the system of the present invention;
FIG. 2 is a schematic diagram of a CB in a CLB structure connecting a logic resource unit LE.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 shows a specific embodiment of a fast wiring method based on CB (Connection-Box) classification according to the present invention, which includes the following steps:
step 1, obtaining a netlist file after a user design circuit is synthesized;
step 2: analyzing the netlist file to obtain logic resources needed by the user circuit;
and step 3: a prescribed number of logical resource units of the same kind are packed into one logical cluster. For example, a plurality of most basic logical resource units LE form a logical cluster CLB, and a plurality of logical resource units MAC _ OUT/MAC _ MULT form a logical cluster DSP;
and 4, step 4: and mapping a plurality of logic clusters formed by a plurality of packed different logic resources to the physical resources of the FPGA for layout, and obtaining the position and the coordinate from the starting point to the end point of the signal. The FPGA consists of many logic clusters, such as DSP/M4K/M9K/CLB. The CLBs are the most basic logical resource units and the most numerous. In this embodiment, CLB is taken as an example for explanation.
And 5: when each net in a user designed circuit is wired, each logic cluster is wired in sequence, whether CB on one logic cluster is in non-full connection or not is judged, if yes, the CB enters port types of all logic resource units in the logic cluster according to the end point of a current signal, the CB corresponding to the corresponding CB type is selected for connection, and the CB type is used for classifying the CBs in the logic clusters according to the port types of the logic resource units in the CB connection logic cluster.
In this embodiment, the CB is a connection-box connecting the outside of the logical cluster to the ports of the logical resource units, and the wiring manner using the CB type is only for the case where the CB is not completely connected, that is, the CB is not connected to N ports of all the logical resource units, and how many ports and which ports of the logical resource units the CB is connected to are determined by hardware design. If the connection is full, the method cannot be used, and only the common wiring process can be used for wiring.
The CB is connected to a plurality of different ports designated by all the logic resource units in the logic cluster, and the CB is divided into different types according to the types of the different ports of the logic resource units connected by the CB. The reason for this classification is that a CB is only connected to different ports assigned to each logical resource unit, and the CB can be connected to one or more different ports of a logical resource unit, and the specific combination manner is determined by a hardware designer. The port combinations of one CB in one logical cluster to all logical resource units are the same. Therefore, it is reasonably feasible to classify CBs in a logical cluster. Taking the example that the logical cluster is a CLB, as shown in fig. 2, CB1 may be connected to odd ports of all logical resource units in the CLB; CB2 may be connected to even ports of all logical resource units.
In addition, multiple end points of the same signal may exist in the same logic cluster, and the entry of the end point of the current signal into the port types of all the logic resource units in the logic cluster in step 5 means that several ports of one signal output to the logic resource units in the logic cluster correspond to several ports of a CB connected to the logic resource units, so that the end point type of the signal can correspond to the port type of the CB connected to the logic resource units, and if the port type of the signal output to the logic resource units by the end point of the signal is consistent with several port types of the CB connected to the logic resource units, the CB of the type is selected for net wiring. In the embodiment, analyzing the port types of all logic resource units of which the end point of the current signal enters the logic cluster is equivalent to analyzing the signal combination type supported by the structure in advance, and then directly matching wiring, because a CB is connected with a signal, and the CB is classified to analyze which ports of the logic resource units the CB is connected with, which port types of the logic resource units the CB is connected with can correspond to which port types of the logic resource units the signal is output to.
Step 6: if net needs to be wired, and a CB in a certain logic cluster needs to be used in the net wiring process, but after all the CBs in the logic cluster are selected, a user is prompted to fail in wiring. In this embodiment, one CB is connected to one signal, and if the CB is selected and there is net not wired, it indicates that the wiring has failed.
In this embodiment, different CB types are formed into a CB type set, each CB type has a plurality of available CBs, each CB type is selected for wiring, and then the CB is deleted from the CB type set. And during wiring, selecting a corresponding CB from the CB type set according to the end point type of the current signal. Using the CB type set, it is convenient to know which CB types remain and several CBs under the corresponding CB types can be used. In addition, when the corresponding CB type is selected according to the end point type of the current signal, no CB type meeting the requirement exists, and the CB type in the CB types meeting the requirement in the minimum number is found from the CB type set and combined together to meet the wiring requirement. For example, a CB type connected to 1,2, 3, and 4 ports of a logical resource unit is needed, but only two types of CBs 12 and 34 connected to the 1 st and 2 nd ports of the logical resource unit and the 3 rd and 4 th ports of the logical resource unit remain in the CB type set, and then the connection requirements are satisfied by using the combinations of the corresponding CBs in the two CB types.
Since the CB types need to be counted, in this embodiment, the connection condition of each CB needs to be counted and stored by using binary coding. Assuming that a logical resource unit has m input ports, m bits are used to indicate the type to which the CB can be connected. If the logical resource unit has 8 input ports and the first CB can be connected to the 1/2 th port of the logical resource unit, the binary code of the CB is 00000011; if the 1/3 th port of a logical resource unit can be connected, the binary encoding of the CB is 00000101. The statistics is carried out on n CB types contained in a logic cluster, and the total number is 2 n 1 CB type.
Before the implementation process, the embodiment also needs to traverse the signal set in advance, and count the types of the logical resource unit ports that need to be connected to all the end points of each signal. The statistical method is that a binary number digital _ bit with n bit width (n bits are consistent with the number of input ports of the logic resource unit) is initialized to be all zero, and if a signal is connected with which ports, the connected port bit is 1 to represent the connection type of the signal. If a logic resource unit has 8 input ports, a signal is respectively connected to the 1,3,5 ports of the logic resource unit, the connection type of the signal is represented as 00010101, and a signal is respectively connected to the 1,2,4,6 ports of the logic resource unit, the connection type of the signal is represented as 00101011.
In the embodiment, the corresponding relation between the connection type of the CB and the end point type of the signal is considered from the hardware structure, the connection type of the CB is counted, and the end point type of the signal is also counted in advance, so that the end point type of each signal corresponds to the CB type, a suitable CB point can be quickly found for wiring, and since the CB used for signal wiring is pre-judged in advance in the wiring process, the competition of different nets on wiring resources in the actual wiring process is reduced, the wiring blockage is avoided, and the wiring speed is increased; by using the method, the CB used by the signal can be reasonably distributed in advance, and the call completing rate is improved. When the CB does not meet the requirement, the conventional wiring can be iterated to the specified times only, and the failure of wiring is prompted.
The invention also provides a rapid wiring device based on CB classification, which comprises the following modules:
a netlist file obtaining module: the netlist file is used for obtaining a netlist file after a user design circuit is synthesized;
an analysis module: the netlist file is used for analyzing the netlist file to obtain logic resources needed by the user circuit;
a packaging module: the system comprises a plurality of logic resources, a plurality of logic clusters and a controller, wherein the logic resources are used for packing a specified number of logic resources of the same kind into one logic cluster;
a layout module: the system comprises a plurality of logic clusters, a plurality of FPGA and a plurality of logic resources, wherein the logic clusters are formed by a plurality of packed different logic resources and are mapped to physical resources of the FPGA for layout, and the positions and coordinates from a signal starting point to a signal finishing point are obtained;
a wiring module: the device comprises a plurality of logic clusters, a plurality of CB groups and a plurality of ports, wherein the CB groups are used for sequentially wiring each logic cluster when each net in a user design circuit is wired, judging whether the CB on one logic cluster is in non-full connection, if so, entering the port types of all logic resource units in the logic cluster according to the terminal point of a current signal, and selecting the CB corresponding to the corresponding CB type for wiring, wherein the CB type is used for classifying the CB in the logic cluster according to the port type of the logic resource unit in the CB connection logic cluster;
a prompt module: when there is a net to be wired, if the CB in a certain logical cluster needs to be used in the process of routing the net, but all CBs in the logical cluster are selected, the user is prompted that the routing fails.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (4)

1. A fast wiring method based on CB classification is characterized by comprising the following steps:
step 1, obtaining a netlist file after a user design circuit is synthesized;
step 2: analyzing the netlist file to obtain logic resources needed by the user circuit;
and step 3: packing a specified number of logic resources of the same kind into a logic cluster;
and 4, step 4: mapping a plurality of logic clusters formed by a plurality of packed different logic resources to the physical resources of the FPGA for layout to obtain the position and the coordinate from the starting point to the end point of the signal;
and 5: when each net in a user designed circuit is wired, sequentially wiring each logic cluster, judging whether CBs on one logic cluster are in non-full connection, if so, entering port types of all logic resource units in the logic cluster according to the end point of a current signal, and selecting the CBs corresponding to the corresponding CB types for connecting, wherein the CB types are used for classifying the CBs in the logic clusters according to the port types of the logic resource units in the CB connection logic cluster;
the classification of the CBs in the logical cluster according to the port types of the logical resource units in the logical cluster connected by the CBs refers to:
the CB is a connection-box connecting the outside of the logic cluster to the ports of the logic resource units, a plurality of CBs are arranged on one logic cluster, one CB is connected to a plurality of ports appointed by all the logic resource units in the logic cluster, and the CBs are divided into different types according to the difference of the ports of the logical resource units connected by the CBs;
the port types of all the logic resource units entering the logic cluster according to the end point of the current signal mean that one signal is output to a plurality of ports of the logic resource units in the logic cluster, and correspond to a plurality of port types of the CB connected to the logic resource units in the logic cluster, if the port type of the end point of the signal output to the logic resource units is consistent with the plurality of port types of the CB connected to the logic resource units, the CB of the type is selected to carry out net wiring;
step 6: if net needs to be wired, and a CB in a certain logic cluster needs to be used in the net wiring process, but after all the CBs in the logic cluster are selected, a user is prompted to fail in wiring.
2. The fast wiring method according to claim 1, wherein different CB types are formed into a CB type set, each CB type has a plurality of available CBs, each CB of one type is selected for wiring, the CB is deleted from the CB type set, and when all the CBs of the type are deleted, the CB type is deleted.
3. The fast wiring method according to claim 2, wherein in step 5, when selecting the CB corresponding to the corresponding CB type, if there is no CB type meeting the requirement, finding out the smallest number of CBs in the CB types meeting the requirement from the CB type set and combining them together to meet the connection requirement.
4. A fast wiring device based on CB classification is characterized by comprising the following modules:
a netlist file acquisition module: the netlist file is used for obtaining a netlist file after a user design circuit is synthesized;
an analysis module: the netlist file is analyzed to obtain logic resources needed by the user circuit;
a packaging module: the system comprises a plurality of logic resources, a plurality of logic clusters and a controller, wherein the logic resources are used for packing a specified number of logic resources of the same kind into one logic cluster;
a layout module: the system comprises a plurality of logic clusters, a plurality of logic resources and a plurality of FPGA, wherein the logic clusters are formed by a plurality of packed different logic resources and are mapped to physical resources of the FPGA for layout, and the positions and coordinates from a signal starting point to a signal ending point are obtained;
a wiring module: the device comprises a plurality of logic clusters, a plurality of CB groups and a plurality of ports, wherein the CB groups are used for sequentially wiring each logic cluster when each net in a user design circuit is wired, judging whether the CB on one logic cluster is in non-full connection, if so, entering the port types of all logic resource units in the logic cluster according to the terminal point of a current signal, and selecting the CB corresponding to the corresponding CB type for wiring, wherein the CB type is used for classifying the CB in the logic cluster according to the port type of the logic resource unit in the CB connection logic cluster;
the classification of the CB in the logic cluster according to the port type of the logic resource unit in the CB connection logic cluster in the wiring module is as follows:
the CB is a connection box connection-box for connecting the outside of the logic cluster to the ports of the logic resource units, a plurality of CBs are arranged on one logic cluster, one CB is connected to a plurality of ports appointed by all the logic resource units in the logic cluster, and the CBs are divided into different types according to the difference of the ports of the logical resource units connected by the CBs;
the port types of all the logic resource units in the wiring module entering the logic cluster according to the end point of the current signal mean that a signal is output to a plurality of ports of the logic resource units in the logic cluster, and are connected to a plurality of port types of the logic resource units corresponding to the CB in the logic cluster, if the port type of the end point of the signal output to the logic resource units is consistent with the port types of the CB connected to the logic resource units, the CB of the type is selected to carry out net wiring;
a prompt module: when there is a net to be wired, if the CB in a certain logical cluster needs to be used in the process of routing the net, but all CBs in the logical cluster are selected, the user is prompted that the routing fails.
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CN112131813B (en) * 2020-09-25 2022-02-18 无锡中微亿芯有限公司 FPGA wiring method for improving wiring speed based on port exchange technology
CN114282471A (en) * 2021-11-19 2022-04-05 中科亿海微电子科技（苏州）有限公司 Boxing method for FPGA adaptive logic module
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CN107895087A (en) * 2017-11-29 2018-04-10 中科亿海微电子科技（苏州）有限公司 The method and system that the emulation of PLD module level automatically generates with code
CN110472340A (en) * 2019-08-16 2019-11-19 中科亿海微电子科技（苏州）有限公司 A kind of modeling method and device of wire structures
CN113919272A (en) * 2021-10-26 2022-01-11 无锡中微亿芯有限公司 FPGA wiring method for improving wiring efficiency by utilizing vacant logic resources

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