JPH02178775A - Layout supporting device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize the optimum layout of the cell of a floor plan, and to give a designer the designing environment of high degree of freedom by using a data base to correlate the logical hierarchical structure information of a circuit with physical layout information. CONSTITUTION:The data base 11 in which data to correlate the logical hierarchical structure information of the semiconductor integrated circuit with the physical layout information is stored, and a means 14 to display the logical hierarchical structure information 16 and the physical layout information 17 simultaneously on different areas on a display screen based on the contents of said data base 11 are provided. Thus, information compatible with both a picture 16 showing the logical hierarchical structure information and the picture 17 showing the physical layout information can be displayed, and an instruction necessary for the floor plan can be executed from either pictures.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit layout support device for arranging circuit cells, blocks, etc. in a semiconductor integrated circuit within a chip, and particularly relates to a semiconductor integrated circuit layout support device for arranging circuit cells, blocks, etc. in a semiconductor integrated circuit. The present invention relates to a semiconductor integrated circuit layout support device having a function of simultaneously displaying logical hierarchical structure information and physical layout information of an integrated circuit.

(Prior Art) Floor planning devices (layout support devices) for semiconductor integrated circuits generally map rectangular circuit cells or blocks (hereinafter simply referred to as cells) having logic and memory functions to specific areas within a chip. Intended for automatic or interactive placement. This work is often used in combination with automatic and interactive parts,
For example, interactive processing may be used on its own, or for setting initial values for an automatic processing section, modifying the results of an automatic processing section, and the like.

There are two main configurations of the interactive processing section.
One is a top-down method that focuses on the logical hierarchical structure of the circuit, in which the circuit is divided on a screen showing the logical hierarchical structure of the circuit and placed in each area. in this way,
The logical hierarchy information screen is the main one, and various screens may be displayed to display information during the work, but these screens only have the function of displaying, and it is not possible to work on the screen. I can't.

Another configuration is a bottom-up method in which each cell is moved to a desired area on a screen on which physical layout information of a circuit is displayed. This method focuses on the physical layout screen. Regarding the work screen, various screens may be displayed to display information as described above, but these screens only have the function of displaying, and it is not possible to work on these screens.

The characteristics of each floor plan are that top-down methods are effective in realizing a floor plan by arranging a large number of cells by taking advantage of the hierarchy, but they are effective at the cell level, which ignores the hierarchy in detail. It is not suitable for optimizing floor plans. On the other hand, the bottom-up method is suitable for optimizing the floor plan at the cell level, but cannot efficiently reflect the hierarchical information of the original circuit and place a large number of cells. In other words, in either method, it was not possible to realize the optimal floor plan intended by the designer.

(Problems to be Solved by the Invention) Conventionally, floor planning devices for semiconductor integrated circuits have been configured mainly with either a screen that displays the logical hierarchical structure of the circuit or a screen that displays information about the physical layout of the circuit. Because of this, floor planning work can only be done top-down from the logical hierarchy screen or bottom-up from the physical layout screen, making it impossible to use both methods together for floor planning. There was a problem in that it was not possible to obtain the optimal floor plan intended by the designer.

The present invention has been made in consideration of the above circumstances, and its purpose is to be able to execute floor planning from both top-down and bottom-up methods.
Semiconductor+A enables optimal placement of cells in the floor plan and provides designers with a highly flexible design environment.
An object of the present invention is to provide a precision circuit layout support device.

[Configuration of the Invention (Means for Solving the Problems) The gist of the present invention is to provide a screen that displays logical hierarchical structure information by using a database that associates logical hierarchical structure information of a circuit with physical layout information. and a screen displaying physical layout information.

That is, the present invention provides a semiconductor integrated circuit layout support device for arranging circuit cells or blocks constituting a semiconductor integrated circuit in a specific area within a chip, which uses logical hierarchical structure information and physical layout information of a semiconductor integrated circuit. A database storing associated data, a means for simultaneously displaying logical hierarchical structure information and physical layout information in different areas on both sides of a display based on the contents of this database, and inputting instructions necessary for layout of a semiconductor integrated circuit. The system is configured to include means for deciphering and executing commands manually entered by this means, and means for updating the contents of the database based on the work results executed by this means.

(Operation) According to the present invention, by using a database that associates logical hierarchical structure information and physical layout information of a circuit, a screen that displays logical hierarchical structure information and a screen that displays physical layout information can be separated. Consistent information can be displayed on both screens, and instructions necessary for floor planning can be executed from either screen.

Therefore, it is possible to provide the designer with an environment in which he or she can perform floor planning from any stage of the floor planning, either top-down or bottom-up.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a schematic configuration diagram showing a floor planning device for a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, 11 is a database storing data that associates logical hierarchical structure information and physical layout information of a semiconductor integrated circuit, 12 is a screen display control mechanism that controls a cathode ray tube display section, and 13 is a human-powered This is a command decoding/execution mechanism that decodes and executes commands input from the device. 13
The instructions decoded and executed change the contents of the database 11 based on the execution results. 14 is a cathode ray tube display, and 15 is an input device such as a keyboard.

Further, 16 is a first screen that displays logical hierarchical structure information of the semiconductor integrated circuit, and the hierarchical structure is expressed and displayed as a tree structure. A second screen 17 displays physical layout information of the semiconductor integrated circuit, and displays the shape of the cell, the external shape of the chip, etc. Both screens are configured to display corresponding information through a screen display mechanism based on the contents of the database.

FIG. 2 is a schematic diagram showing more specifically the first screen 16 that displays logical hierarchical structure information of a semiconductor integrated circuit and the second screen 17 that displays physical layout information. In FIG. 2, hierarchical information of semiconductor integrated circuits is displayed in a tree structure on the first screen 16, and in front of the circuit hierarchical name is a rectangle a that indicates by color in which area the hierarchical layer is placed. is displayed. On the second screen 17, the external shape, area, cells, etc. of the chip are displayed. These displays are all based on data stored in the database 11 that associates the logical hierarchical structure information and physical layout information shown in FIG.

In such a configuration, an instruction to place block 1 in area 1 is received from the operator through input device 15.
When executed on the first screen 16 displaying logical hierarchical structure information, 1. The database 11 is updated through the instruction decoding/execution mechanism 13. As a result, through the screen display control mechanism 12, the color of the four corners indicating the color of the area arranged on the first screen 16 becomes the color of area l, and at the same time, the color of the second screen displaying the physical layout information is changed to the color of the area l. Cell 1 on screen 17.
Cell 2 moves from cell 2 to b/ and c/ in area 1.

In addition, when a command to move cell 2 placed in area 1 to area 2 d on the second screen 17 is subsequently executed through the human power device 15, cell 2 on the second screen 17 is moved. In addition, the color indicating the area of cell 2 on the first screen 16 is updated to the color of area 2. As a result, the two cells below the block 1 hierarchy are placed in separate areas.

By using a database that associates logical hierarchical structure information and physical layout information in this way, it is possible to always display consistent screens on two screens, and it is possible to display information necessary for floor planning from either screen. It becomes possible to execute commands. Therefore, the designer can execute floor planning using both top-down and bottom-up methods, making it possible to optimally arrange cells during floor planning, and increasing the degree of freedom in floor planning.

Furthermore, it is possible to shorten the design period and, by extension, the product development period.

By the way, automatic layout design CAD for semiconductor integrated circuits
The main purpose of the system is to improve the degree of integration of automatically designed semiconductor integrated circuits, but each placement and wiring processing strategy is uniformly determined within the system and is common to all types of integrated circuits. It was difficult to achieve a good degree of integration.

In order to solve this problem, in this embodiment, the layout CA
When arranging a plurality of logic circuit modules or cells on a semiconductor substrate in the D system and processing wiring between each logic circuit module or cell, the arrangement state and wiring state at each processing step are sequentially changed as the zero-motion layout processing progresses. The present invention includes means for displaying and means for selecting automatic placement and wiring processing after each placement and wiring state, and displays the layout result at that point on a CRT display.

This makes it possible to check the layout status at each step of placement and wiring on a CRT display, and in that state, select the next placement and wiring strategy that is most effective for increasing the degree of integration, thereby improving the integration of semiconductor integrated circuits. This improvement can be achieved in common for different types of circuits.

Next, this example will be specifically explained.

FIG. 3 is a block diagram showing a schematic configuration of a layout status display system according to this embodiment, and this device is a CRT display system.
Display 30. Command interpretation interface 31
．． A group of placement/routing programs that execute each strategy 32. It is composed of a database 33 that stores layout states, a display interface 34, and the like. When a command is input by the operator based on the display state of the CRT display 30, a strategy for this command is executed by the program group 32 via the command interpretation interface 31.

The execution results are stored in the database 33. The layout state stored in the database 33 is displayed on the CRT display 3 through the display interface 34.
0 is displayed.

Figure 4 shows the CRT at a certain time during placement and wiring processing.
It is a figure showing an example of a display. In the figure, CRT display 30
The upper part is divided into four windows, each of which displays the layout status on the chip;
It consists of a selection menu window 42 for the next placement/routing process, a window 43 for executing the selected strategy, and a window 44 for setting the time to interrupt the next process after executing the placement/routing process according to the selected strategy. ing. These windows are displayed on the CRT display 30 at the same time.

FIG. 5 is a detailed diagram of the window 41 that displays the layout state of FIG. 4. The layout state here is the state at a certain time of global wiring processing. Figure 5(a)
As shown in the figure, the top of the LSI chip 45 is divided into regions 46, and the wiring routes between the terminals a to c are allocated to each region and displayed. Here, the degree of wiring congestion in each area is displayed for each area, and it is displayed that if the wiring between the terminals dind2 is allocated to the area on the chip using the shortest route, the wiring capacity that can pass through the area will be exceeded. ing.

Therefore, in order to allocate routes without exceeding the wiring capacity, a strategy is determined from the strategy menu 42 in FIG. 4 and executed in the execution window 43. At this time, the next execution interruption point is set in the interruption point setting window 44. As a result, as shown in FIG. 5(b), the wiring route between the terminals dl and d2 is assigned a detour route (solid line in the figure) that avoids the crowded wiring area. By repeating these processes, efficient wiring routes are allocated, and effective placement and wiring processing for improving the degree of integration is performed.

This process will be explained in more detail with reference to the flowchart in FIG. First, global wiring is executed for the purpose of shortening the wiring length (execution of 'ill 1). The layout state resulting from the execution of this strategy 1 is displayed in the window 41. Next, the next strategy is determined by looking at the layout state. If the next strategy is necessary, global wiring is executed again for the wiring route allocated in excess of the wiring capacity in order to equalize the wiring route in the entire area (strategy 2 is executed).

After this, the layout state is displayed in the same manner as before, and the strategies or the order of strategies are changed and executed one after another as necessary.

For example, when strategy 1 is executed, as shown in FIG. 5(a),
As shown in FIG. 2, since the wiring routes are concentrated and allocated in the central part, the wiring capacity of the central part is exceeded. Therefore, by executing Strategy 2, the wiring routes are uniformly allocated to the area as shown in FIG. 5(b).
The route of d is changed to bypass the empty surrounding area. By combining strategies in this way, effective global wiring can be performed with the shortest distance and without exceeding the wiring capacity.

Thus, according to this embodiment, when a layout design for an integrated circuit is performed using a CAD system, placement and wiring strategies that are difficult to uniformly determine depending on the type of each circuit can be interactively performed using a display system. A good degree of integration can be achieved regardless of the type of

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, the display for displaying the logical hierarchical structure information and physical layout information may be CR.
The display device is not limited to T, and a liquid crystal display or other display device can be used.

[Effects of the Invention] As detailed above, according to the present invention, by using a database that associates logical hierarchical structure information and physical layout information of a circuit, a screen displaying logical hierarchical structure information and a physical Dynamic related processing can be performed between two screens displaying layout information. Therefore, floorplanning can be executed from both top-down and bottom-up methods, making it possible to optimally place floorplan cells, giving designers a design environment with a high degree of freedom. .

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing a floor planning device for a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing an example of a screen display of the device, and FIG. 3 is a diagram related to another embodiment. FIG. 4 is a schematic diagram showing an example of the display display of the system in FIG. 3, FIG. 5 is a schematic diagram showing an example of detailed display of the layout state, and FIG. FIG. 4 is a flowchart for explaining the operation of the device shown in FIG. 3; FIG. DESCRIPTION OF SYMBOLS 11... Database, 12... Screen display control mechanism, 13... Instruction decoding/execution mechanism, 14... Cathode ray tube display (display), 15... Keyboard (
input device), 16... Screen (first screen) for displaying logical hierarchical structure information; 17... Screen (second screen) for displaying physical layout information. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure Figure Figure

Claims (1)

[Scope of Claims] A semiconductor integrated circuit layout support device for arranging circuit cells or blocks constituting a semiconductor integrated circuit in specific areas within a chip, comprising: logical hierarchical structure information and physical layout information of the semiconductor integrated circuit; means for simultaneously displaying the logical hierarchical structure information and the physical layout information in different areas on both sides of the display based on the contents of the database; and means necessary for the layout of the semiconductor integrated circuit. means for inputting a command, means for decoding and executing the command input by the means, and means for updating the contents of the database based on the results of the work executed by the means. A semiconductor integrated circuit layout support device characterized by the following.