JP2766284B2 - Layout support device for semiconductor integrated circuit - Google Patents

Description

Description: Object of the Invention (Industrial Application Field) The present invention relates to a layout support device for a semiconductor integrated circuit in which circuit cells, blocks, and the like in a semiconductor integrated circuit are arranged in a chip, and particularly relates to a semiconductor device. The present invention relates to a layout support device for a semiconductor integrated circuit, which has a function of simultaneously displaying logical hierarchical structure information and physical layout information of an integrated circuit.

(Prior Art) A floor plan apparatus (layout support apparatus) for a semiconductor integrated circuit generally includes a rectangular circuit cell or block (hereinafter simply referred to as a cell) having a logical function and a storage function in a specific area in a chip. It is intended for automatic or interactive placement. In many cases, this operation is used in a combination of the automatic processing part and the interactive processing. For example, the interactive processing is used alone or for setting initial values to the automatic processing part or correcting the result of the automatic processing part.

The configuration of the interactive processing unit is roughly classified into two types. One is a top-down method that focuses on the logical hierarchical structure of the circuit, and the circuit is divided on a screen showing the logical hierarchical structure of the circuit and arranged in each area. It is a way to do it. In this method, the screen of the logical hierarchy information is the center, and various screens may be displayed in the sense that the information is displayed during the work, but these screens have only a function of displaying, and the screen has only a function of displaying. I can't work.

Another configuration is a bottom-up method of moving to a desired area in units of cells on a screen on which physical layout information of a circuit is displayed. In this method, work proceeds mainly on the physical layout screen. As for the work screen, various screens may be displayed in the sense that information is displayed as described above. However, these screens have only a display function and cannot perform work on these screens.

As a feature of each floor plan, the top-down method is effective for realizing a floor plan by arranging a large number of cells by taking advantage of the hierarchy, but at the cell level ignoring the hierarchy in the details Is not suitable for optimizing floor plans. On the other hand, the bottom-up method is suitable for optimizing the floor plan at the cell level, but cannot efficiently arrange the hierarchical information of the original circuit and arrange a large number of cells. That is, in either case,
The optimal floor plan intended by the designer could not be realized.

(Problems to be Solved by the Invention) As described above, conventionally, a floor plan apparatus for a semiconductor integrated circuit mainly includes a screen for displaying a logical hierarchical structure of a circuit or a screen for displaying physical layout information of a circuit. Since the floor plan work is performed only from the logical hierarchy screen to the top down or from the physical layout screen to the bottom up, floor plan cannot be performed using both methods. There has been a problem that an optimum floor plan intended by the designer cannot be obtained.

The present invention has been made in consideration of the above circumstances, and a purpose thereof is to perform a floor plan from either a top-down method or a bottom-up method, and to optimally arrange cells in the floor plan. It is an object of the present invention to provide a semiconductor integrated circuit layout support device which can provide a designer with a high degree of freedom in a design environment.

[Configuration of the Invention] (Means for Solving the Problems) The gist of the present invention is a screen for displaying logical hierarchical structure information by using a database that associates logical hierarchical structure information of circuits with physical layout information. And a screen for displaying physical layout information.

That is, the present invention provides a layout support apparatus for a semiconductor integrated circuit in which circuit cells or blocks constituting a semiconductor integrated circuit are arranged in a specific area in a chip, wherein the logical hierarchical structure information and the physical layout information of the semiconductor integrated circuit are compared. A database storing data to be associated, means for simultaneously displaying logical hierarchical structure information and physical layout information in different areas on the display screen based on the contents of the database, and an instruction necessary for the layout of the semiconductor integrated circuit are input. And means for decoding and executing the command input by the means, and means for updating the contents of the database based on the work result executed by the means.

(Operation) According to the present invention, a screen for displaying the logical hierarchical structure information and a screen for displaying the physical layout information are provided by using a database that associates the logical hierarchical structure information of the circuit with the physical layout information. Information consistent with both can be displayed, and it is possible to execute a command necessary for floor plan from any screen. Therefore, from every stage of the floor plan,
It is possible to provide an environment where a floor plan can be made from any of the top-down and bottom-up methods.

(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples.

FIG. 1 is a schematic configuration diagram showing a floor plan apparatus for a semiconductor integrated circuit according to one embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a database storing data for associating logical hierarchical structure information of a semiconductor integrated circuit with physical layout information, 12 denotes a screen display control mechanism for controlling a CRT display unit, and 13 denotes an input. An instruction decoding / executing mechanism that decodes and executes an instruction input from the device. The instruction decoded and executed by 13 changes the contents of database 11 based on the execution result. 14 is a cathode ray tube display (display), and 15 is an input device such as a keyboard.

Reference numeral 16 denotes a first screen for displaying the logical hierarchical structure information of the semiconductor integrated circuit, which displays the hierarchical structure in a tree structure. Reference numeral 17 denotes a second screen for displaying physical layout information of the semiconductor integrated circuit, which displays a cell shape, a chip outer shape, and the like. Both screens are configured to display corresponding information through a screen display mechanism based on the contents of the database.

FIG. 2 is a schematic diagram more specifically showing a first screen 16 displaying the logical hierarchical structure information of the semiconductor integrated circuit and a second screen 17 displaying the physical layout information. Second
In the figure, on a first screen 16, hierarchical information of a semiconductor integrated circuit is displayed in a tree structure, and a square a indicating in which area the hierarchical level is arranged is displayed in front of the hierarchical level of the circuit. Have been. On the second screen 17, the outer shape, area, cells and the like of the chip are displayed. These displays are
All of them are based on the data stored in the database 11 associating the logical hierarchical structure information and the physical layout information shown in FIG.

In such a configuration, an instruction from the operator through the input device 15 to place the block 1 in the area 1 is given by
When executed on the first screen 16 displaying the logical hierarchical structure information, the database is passed through the instruction decoding / executing mechanism 13.
11 is updated. As a result, through the screen display control mechanism 12, the square color indicating the color of the area arranged on the first screen 16 becomes the color of the area 1, and at the same time, the second color displaying the physical layout information. The cells 1 and 2 on the screen 17 move from b and c to b 'and c' in the area 1. Also, in the reverse,
When the command to move the cell 2 arranged in the area 1 to the d in the area 2 on the screen 17 is executed through the input device 15,
Not only does cell 2 on the second screen 17 move,
The color indicating the area of the cell 2 on the screen 16 is updated to the color of the area 2. As a result, 2 which was below the hierarchy of block 1
The two cells are arranged in different areas.

By using a database that associates the logical hierarchical structure information with the physical layout information in this way, it is possible to always display a consistent screen on two screens, and to use a floor plan from either screen. Instructions can be executed. Therefore, the designer can execute the floor plan from both the top-down and bottom-up methods, and the cells can be optimally arranged in the floor plan, and the degree of freedom in the floor plan increases.
Further, it is possible to shorten the design period and, consequently, the product development period.

By the way, automatic layout design CAD for semiconductor integrated circuits
Although the main purpose of the system is to improve the degree of integration of automatically designed semiconductor integrated circuits, the processing strategies for each layout and wiring are determined uniformly in the system, and are common to all types of integrated circuits. It was difficult to achieve a good degree of integration.

In order to solve this, in the present embodiment, the layout CA
In a D system, a plurality of logic circuit modules or cells are arranged on a semiconductor substrate, and when processing wiring between logic circuit modules or cells, the arrangement state and wiring state at each processing step are sequentially displayed according to the progress of the automatic layout processing. Means for selecting automatic placement and wiring processing after each placement and wiring state, and displays the layout result at that time on a CRT display.

This makes it possible to check the layout state at each step of placement and wiring on a CRT display, and in that state, it is possible to select the next placement and wiring strategy that is most effective in improving the degree of integration, and to integrate the semiconductor integrated circuit. The enhancement can be achieved in common for different types of circuits.

 Next, this embodiment will be described specifically.

FIG. 3 is a block diagram showing a schematic configuration of a layout state display system according to this embodiment.
The display 30 includes a display 30, a command interpretation interface 31, a group of placement / wiring programs 32 for executing each strategy, a database 33 for storing layout states, a display interface 34, and the like. When a command is input from the operator based on the display state of the CRT display 30, a program group 32 is input via a command interpretation interface 31.
Executes the strategy for the command. The execution result is stored in the database 33. The layout state stored in the database 33 is displayed on the CRT display 30 through the display interface 34.

Fig. 4 shows the CRT at a certain time in the placement and wiring process.
It is a figure showing an example of a display. In the figure, the CRT display 30 is divided into four windows, each of which is a window 41 for displaying a layout state on a chip, a menu window 42 for selecting a next placement / wiring process, and executing a selected strategy. The window 43 includes a window 44 for setting a time at which the processing is interrupted after the placement / routing processing is executed according to the selected strategy. These windows are displayed on the CRT display 30 at the same time.

FIG. 5 is a detailed view of a window 41 for displaying the layout state of FIG. The layout state here is a state at a certain time of the global wiring processing. Fig. 5 (a)
As shown in the figure, the area on the LSI chip 45 is divided into the respective areas 46, and the wiring paths between the terminals a to c are assigned to the respective areas and displayed. Here, the wiring congestion degree of each area is displayed for each area, and if the wiring between the terminals d ₁ and d ₂ is assigned to the area on the chip by the shortest path, the wiring capacity exceeding the area can be exceeded. It is displayed.

In order to allocate a route without exceeding the wiring capacity, a strategy is determined from the strategy menu 42 shown in FIG. At this time, the next execution interruption point is set in the interruption point setting window 44. As a result, as shown in FIG. 5B, the wiring route between the terminals d ₁ and d ₂ is a route bypassing the wiring congested area (solid line in the drawing).
Is assigned. By repeating these processes, an efficient wiring route is allocated, and a placement / wiring process effective for improving the degree of integration is performed.

This processing will be described in more detail with reference to the flowchart of FIG. First, global wiring is executed for the purpose of shortening the wiring length (execution of strategy 1). The layout state by executing this strategy 1 is displayed in the window 41. Next, the next strategy is determined by looking at the layout state. If the next strategy is necessary, global wiring is executed again for the purpose of making the wiring paths uniform over the entire area with respect to the wiring paths that have been assigned over the wiring capacity (execution of strategy 2). After that, the layout state is displayed in the same manner as described above, and the strategies or the order of the strategies are changed one after another as necessary.

For example, in the state where strategy 1 is executed, as shown in FIG. 5 (a), the wiring paths are concentratedly allocated to the central portion, so that the wiring capacity in the central portion is exceeded. For this reason, by executing the strategy 2, the wiring route is uniformly allocated to the region as shown in FIG. 5 (b), and the route of d is changed so as to bypass the neighboring region. Is done. By combining the strategies in this way, effective global wiring is performed with the shortest distance and the wiring capacity does not exceed.

Thus, according to the present embodiment, when the layout design is performed on the integrated circuit by the CAD system, the layout / wiring strategy, which is difficult to determine uniformly depending on the type of each circuit, is interactively performed by the display system, and thus the circuit is designed. And a good degree of integration that does not depend on the type.

Note that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention. For example, the display for displaying the logical hierarchical structure information and the physical layout information is CR.
The display is not limited to T, and a liquid crystal or other display device can be used.

[Effects of the Invention] As described above in detail, according to the present invention, by using a database for associating logical hierarchical structure information of a circuit with physical layout information, a screen displaying logical hierarchical structure information and a physical Screen 2 for displaying layout information
Dynamic related processing can be performed between the two.
Therefore, the floor plan can be executed from both the top-down method and the bottom-up method, the cells can be optimally arranged in the floor plan, and the designer can be provided with a highly flexible design environment. .

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a floor plan apparatus for a semiconductor integrated circuit according to one embodiment of the present invention, FIG. 2 is a schematic diagram showing an example of a screen display of the same apparatus, and FIG. 3 is related to another embodiment. FIG. 4 is a block diagram showing a schematic configuration of the layout state display system, FIG. 4 is a schematic view showing a display example of the system of FIG. 3, FIG. 5 is a schematic view showing a detailed display example of the layout state, and FIG. 4 is a flowchart for explaining the operation of the apparatus shown in FIG. 11 ... Database, 12 ... Screen display control mechanism, 13 ...
Command decoding / executing mechanism, 14 CRT display device (display), 15 keyboard (input device), 16 screen for displaying logical hierarchical structure information (first screen), 17 ...
... Screen for displaying physical layout information (second screen).

Claims (1)

(57) [Claims] 1. A layout support apparatus for a semiconductor integrated circuit in which circuit cells or blocks constituting a semiconductor integrated circuit are arranged in a specific area in a chip, wherein logical hierarchical structure information and physical layout information of the semiconductor integrated circuit are provided. A database storing data for associating the logical hierarchical structure information and physical layout information in different areas on a display screen based on the contents of the database, and a layout required for the semiconductor integrated circuit. Means for inputting an instruction, means for decoding and executing the instruction input by the means, and means for updating the contents of the database based on a work result executed by the means. A layout support device for a semiconductor integrated circuit, comprising: