JPH04147379A - Method for correcting network list for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To automatically carry out such correction as newly defining intermediate stage blocks between the lower stage blocks and the upper stage blocks by extracting block data one by one node from a list of original upper stage block. CONSTITUTION:Block data defined for upper stage blocks is extracted one by one node. In this example, since block TOP is a upper stage block, from a list of TOP, block data is extracted one by one line. New terminals of intermediate stage block SUB to be newly prepared are generated, and further two block data items that shows the connecting relationship between a part of a plurality of terminals included in extracted data and the newly prepared terminals are generated. Furthermore, by one of these block data items extracted data in a list of upper stage blocks is replaced, while the processing of adding the other block data item to a list to be newly prepared is implemented. With this, the operator has only to carry out input work for specifying an object block.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for modifying a netlist for a semiconductor integrated circuit, and in particular, a method for modifying a netlist for a semiconductor integrated circuit, and in particular, a method for modifying a netlist for a semiconductor integrated circuit. The present invention relates to a modification method that can automatically perform modifications such as defining a new middle block between blocks using a computer.

[Conventional technology]

In designing a semiconductor integrated circuit, a logic design is first performed, a logic simulation is performed on the designed logic circuit, and then a specific layout design is performed. At the time of logic design and layout design, information about each component of a semiconductor integrated circuit (for example, logic elements such as AND circuits and NOR circuits) is classified into blocks with a hierarchical structure. It is expressed as a tane sotorist. Normally, the netlist created during logic design is also used as is during layout design.

[Problems to be Solved by the Invention] However, there are few cases in which a netlist used in logical design can be used in layout design in its exact form, and some modifications are usually required. For example, it may be necessary to make a modification such as defining a new middle-layer block between a plurality of target lower-layer blocks and an upper-layer block defined in a hierarchy above the lower-layer blocks. If the netlist is given as graphical data,
This kind of modification can be done relatively easily, or if the data is provided as character data, it can be extremely difficult and an error-prone task.

Therefore, the present invention uses a computer to automatically make corrections such as defining a new middle-layer block between a plurality of target lower-layer blocks and an upper-layer block defined in the hierarchy above the lower-layer blocks. An object of the present invention is to provide a method for modifying a netlist for a semiconductor integrated circuit.

[Means to solve the problem]

The present invention classifies each component of a semiconductor integrated circuit into blocks with a hierarchical structure, and defines for each block block data indicating connection relationships within the block. In this method, a new middle-layer block is defined between a plurality of lower-layer blocks and an upper-layer block defined in the hierarchy above the lower-layer blocks. A step of inputting a modification command that specifies an upper layer block defined in the hierarchy above the lower layer block, a step of extracting block data defined for the input upper layer block for each node, and a step of extracting this extracted data. Focusing on multiple terminals whose connection relationships are indicated by If the terminal is for the target lower block, it is determined to be in the second state, and if none of the terminals is for the target lower block, it is determined to be in the third state; and when it is determined to be in the first state. Next, the extracted data is moved from the list for the upper block to the newly created list for the middle block, and when the second state is determined, a new terminal is generated and the extracted data is used to move the extracted data to the newly created list for the middle block. Create two block data indicating the connection relationship between some of the multiple terminals whose connection relationships are indicated and this new terminal, and replace the extracted data in the list regarding the upper layer block with one of the block data, The following steps are performed: a step of adding the other block data to the newly created list; and a step of not modifying the list when the third state is determined.

[For production]

When making a modification such as defining a new middle block between multiple target lower blocks and an upper block defined in the hierarchy above the lower block, make the correction to the list for the upper block. At the same time, a new list of middle-layer blocks must be created.

In the method according to the present invention, block data for each node is extracted from the original list of upper layer blocks,
The above operations are performed based on this extracted data.

The work contents can be divided into three types depending on which block the plurality of terminals included in the extracted data belong to.

These three types of tasks are all simple logical tasks, so they can be automatically processed by a computer. Since the process is automated in this way, the operator only has to perform input work to specify the target block.

〔Example〕

The present invention will be described in detail below based on an illustrated embodiment. FIG. 1 is a flowchart showing the steps of a method for modifying a netlist for a semiconductor integrated circuit according to an embodiment of the present invention. Before explaining this procedure, the outline of the semiconductor integrated circuit design process will be briefly explained along the process diagram of FIG. 2. First, in process P1, a system design is performed.

This is a general design of the entire system. In the subsequent process P2, logic design is performed. In other words, integrated circuits are designed at the logic circuit level. As described above, at this time, a netlist with a hierarchical structure is created to show the connection relationship of each logic circuit element.

An example of the hierarchical structure of this netlist is shown in FIG. Here, X1 to X3 indicate individual logic elements. In this way, each logic element is classified into four blocks B1 to B4, and furthermore, in order to unify these four blocks, T
A top block called OP is provided. Thus, in this example, there are first hierarchical blocks at the individual logic element level indicated as X1 to X3, second hierarchical blocks at the intermediate level indicated as blocks 81 to B4, and a second hierarchical block at the highest level indicated as TOP. There are three hierarchical levels: a three-hierarchical block; Complex integrated circuits have even more layers.

Subsequently, logic simulation for this designed logic circuit is executed in process P3. If any problems are found as a result of the simulation, the logic design will need to be modified. If the logic simulation passes,
A specific layout design is performed in process P4. That is, the layout of a mask pattern for processing a semiconductor wafer is determined. At this time, as mentioned above,
Although the netlist created in the logical design of process P2 will be used, it will be necessary to make some modifications. For example, the netlist for the logical design of the process P2 was as shown in FIG. 3, but the netlist for the layout design of the process P4 needs to be as shown in FIG. That is, at the time of logic design, the block structure had a total of three hierarchies, but at the time of layout design, it became necessary to provide a new block SUB in the upper layer of blocks B1 and 82, resulting in a block structure of four hierarchies. The addition of such a new middle-layer block is necessary due to demands such as improving layout efficiency when actually laying out logic elements on a semiconductor wafer surface. For example, during logic design, it would be fine to classify the blocks as shown in Figure 5, but when considering the actual layout, it would cause problems such as extremely long wiring, so it would be better to classify the blocks as shown in Figure 6. A situation arises that is efficient. In particular, in order to obtain a high-quality layout, it is necessary to classify blocks by function, divide or consolidate blocks as appropriate, and make free modifications that are not limited by the hierarchical structure of the netlist.

In the method according to the present invention, a plurality of target blocks B1
The netlist can be automatically corrected simply by specifying SUB and B2 and manually adding a new block SUB in the upper layer.

The automatic correction procedure will be explained below using a specific example. Here, an example will be shown in which the method according to the present invention is applied to a specific logic circuit as shown in FIG. In this logic circuit, four blocks B1 to B4, which are the second layer, are formed below the block TOP, which is the first layer, and further, a block X, which is the third layer, is formed below each block B1 to B4.
1 to X4 are formed. Blocks X1 to X4 are actually logic elements such as NOR circuits and inverter circuits. Codes A, B, C, D in each logic element.

I, 0, 11.12, etc. indicate the terminal names of this logic element. In addition, N1 to N1 written inside blocks B1 to B4
N7 indicates a node between each terminal, and is written on the outline of blocks B1 to B4. Codes such as N1, , and N2 indicate terminal names of blocks.

A netlist for such a logic circuit is as shown in FIG. Here, B1°B2. B3.
B4. The five data groups labeled TOP are blocks Bl, B2 . B3゜B4. This is a list of block data indicating internal connection relationships of the TOP. Each block data is preceded by a node name such as Nl-, N2-, etc. as a heading, followed by the name of a terminal connected to this node. Terminal names are indicated with a symbol "," in front of them. For example, the symbol "N1" indicates a node, while the symbols r and NIJ indicate terminals. Further, the symbol "," is used to separate terminal names, and the symbol ";" is used at the end of data regarding one node. If you understand the above rules, you will understand that the block data in FIG. 8 represents the logic circuit in FIG. 7. For example, r in the rN 1-J column in the first row of the list of block B1, N1. XI, A, I4,
The data I 1 ;
This shows that A and the terminal 11 of block X4 are connected. Also, rN in the 4th line of the same list
4=rN4 in column J=X3. 0. I4, I2. J
The data is stored at node N4 at terminal 0 of block X3.
, and the terminal 12 of block X4 are connected. Generally, the name of the block to which the terminal belongs is added in front of the terminal names listed on the right side of "=". For example, in the rX3 mentioned above, OJ is the terminal name, O
The block name X3 is added in front of the block name X3, and the terminal O in the block X3 is specified. However, in the netlist of this embodiment, the block name is omitted for the block itself for which the netlist indicates a connection relationship. For example, among the data r, N1°XI, A, I4, IIJ in the rN 1-J column mentioned above, the terminal names r and NIJ are originally
However, since this block data is for block B1, the block name "B1" is omitted.

Now, in the logic design, a netlist for the circuit shown in Figure 7 was created, but in the layout design, it became necessary to provide a new middle block SUB above blocks B1 and B2. do. In the end, the logic circuit has a block configuration as shown in FIG. A new block S that includes blocks B1 and B2
UB is provided, and on the outline of this new block SUB, disconnected terminals, N1. , N2 are provided. If such a modification is made, the netlists for blocks B1 to B4 will not change, but for block TOP, the internal connection relationship will change, so the netlist will need to be modified, and new block SU
It is necessary to create a new netlist for B. After all, in order to change the block configuration shown in FIG. 7 to the block configuration shown in FIG. 9, it is necessary to perform two correction operations on the netlist. The first is to change the list for block TOP out of the five lists shown in FIG. 8 as shown in FIG. 10, and the second is to change the list for block TOP as shown in FIG. 11 as a new list. Block S
The purpose is to create a list about UB. According to the procedure described below, based on the netlist for the block TOP shown in FIG.
It is possible to automatically create a diagram netlist.

This procedure will now be explained along the flowchart of FIG.

In addition, in the following explanation, the upper layer, middle layer,
The lower layer refers to the relative hierarchical relationship between blocks, and in the specific examples shown in FIGS. 7 and 9, blocks B1 to B4 are the lower layer blocks, block TOP is the upper layer block, and the newly created block is the lower layer block. Block SUB will be called a middle layer block. First, in step S1, a modification command is input. The netlist shown in FIG. 8 is given to the computer as data, but the operator also sends the names of multiple lower-layer blocks to be modified (blocks B1 and B2 in this example) as a modification command.
), the upper layer block name that includes these lower layer blocks (in this example, block TOP), and the name of the newly created middle layer block (in this example, block 5UB),
Give the computer input that specifies the Note that the upper layer block name can be specified based on the netlist without input by the operator, and the middle layer block name can be uniquely assigned any name by the computer. be. Therefore, the operator only needs to input the minimum amount of information to specify a plurality of lower-layer blocks to be modified. Hereinafter, the plurality of lower blocks specified as correction targets will be referred to as target blocks.

In the following step S2, block data defined for the upper layer block is extracted for each node. In this example, block TOP is the upper layer block, so the 8th
Block data is extracted line by line from the list for the block TOP shown in the figure. That is, first rN
The data in column 1-J is extracted, and then rN 2 =J
The data in the column rN5-J is extracted, and the data in the column rN5-J is extracted line by line in order.

In the following step S3, terminal discrimination is performed on this extracted data. That is, the block to which all terminals included in the extracted data belong is examined, and it is determined which of the three states they are in. For example, if the data in the column "rN1=" in the first line of the block TOP list shown in FIG. 8 is extracted, "=
” data rB1, N1. The two terminals (Bl, N1) and (B2, N5) that make up B2, N5J
), consider the block to which it belongs. As mentioned above, terminals are described by writing the terminal name after the name of the block to which it belongs.
The name of the block to which it belongs can be immediately recognized. For example, terminal (Bl, N1) belongs to block B1 and terminal (
B2, N5) can be recognized as belonging to block B2. Based on the information regarding the block to which it belongs recognized in this way, in step S3, it is determined whether each extracted data is in one of the following three states, and the process branches to the next step.

■First state: If all the terminals belong to the target block (the plurality of lower blocks identified in step S1), the process branches to step S4.

(2) In the second state, if some of the terminals belong to the target block, the process branches to step S5.

■Third state: If none of the terminals belong to the target block, the process branches to step S6.

In this way, different processing is performed at the branch destination (in the case of the third state, no processing is performed), and in either case, the process reaches step S6. Finally, in this step S6, it is determined whether all data has been extracted. In this example, step S2
The steps from then on are repeated.

Now, step S3. B4. The procedure of B5 will be explained in detail based on a specific example. As mentioned above, in step S2,
The block data shown in the block TOP list in FIG. 8 is extracted line by line. That is, rN 1 in the first row
The data in the =J column to the data in the 5th column "N=5J" will be extracted line by line.Hereafter, this 1
Processing for extracted data extracted row by row will be explained in order.

First, rN1=B1, N1. B2, N5; J
The terminal determination in step S3 is performed for the data. There are two terminals (Bl, N1) and (
B2, N5) are described, and the former is block B1
The latter is recognized to belong to block B2.

Since these blocks B1 and B2 are both terminals that belong to the target block (the plurality of lower blocks identified in step S1), they are determined to be in the first state in step S3, and the processing in step S4 is performed. Become.

The process in step S4 is a process of moving the extracted data from the upper layer block list to the middle layer block list. That is, rNl-B1, N1. B2, N5;
The extracted data J is the newly created block S from the block TOP (upper block) list in Figure 8.
Moved to the UB (middle layer block) list. As a result, as shown in FIG. 11, rNi=B1, N1. B2, N5; J
The extracted data will be entered. The process of step S4 is now complete. The process returns to step S2 via step S6, and this time rN2=Bl, N2. B2, N7; For the data J, the terminal determination in step S3 is performed. There are two terminals (Bl, N2) and (B2,
N7) is described, and it is recognized that the former belongs to block B1 and the latter belongs to block B2. Since both blocks B1 and B2 are terminals belonging to the target block, they are determined to be in the first state in step S3, and the process in step S4 is performed.

Therefore, this extracted data is the block TO in FIG.
The block is moved from the list of P to the newly created list of block SUB.

As a result, as shown in FIG. 11, in the second line of the block SUB list, rN2-B], , N2°B2. N7;
Extracted data J is entered. The process of step S4 is now complete.

Subsequently, the process returns to step S2 via step S6,
This time, rN in the third row of the block TOP list in Figure 8.
3=B2, N1. B3, N4; For the data J, the terminal determination in step S3 is performed. here,
Two terminals (B2, N1) and (B3, N4)
It is recognized that the former belongs to block B2 and the latter belongs to block B3. By the way, block B2 is a target block, but block B3 is not a target block. Therefore, the second state is determined in step S3, and the process in step S5 is performed. In the process of step S5, a disconnected terminal is generated, and two block data indicating the connection relationship between some of the plurality of terminals included in the extracted data and the disconnected terminal are created. Processing is then performed to replace the extracted data in the list of upper layer blocks with the data of one of these blocks, and to add the data of the other block to the newly created list. Note that the disconnected terminal generated here is a disconnected terminal for the newly created middle-layer block SUB. As shown in FIG. 9, by newly providing the middle block S'UB, disconnected terminals N1 and N are placed on the outline of block SUB.
2 is occurring. The generated new terminal name may be specified by the operator, but it is preferable to have the computer automatically name it because it saves the operator's time and effort. In this embodiment, mechanically, , N], N2 . They are named in order.

Also, since this disconnected terminal is a terminal belonging to the newly created block SUB, the description on the block data is (SUB, N1), (SUB, N2),
...becomes...

Now, N5 in the third line of the block TOP list in FIG. 8 = B2, N], , B3, N4;
Let us actually perform the process of step S5 on the data (1). There are two terminals (B2, N1
) and (B3, N4) are described, and if block data is created that shows a state in which disconnected terminals (SUB, N1) are connected to each, N3=SUB, N1. B2, N1; (2
)N3=SUB, N1. , B3, N4:
(3) Two block data can be created. In other words, by separating the terms indicating the two terminals on the right side of data (1) and combining them with terms indicating the new terminal (SUB, N1), data (2) and (3) can be mechanically obtained. . Of the two block data obtained in this way, one that includes the terminal for the target block (i.e.
Data (2) including terminals for target block B2)
is added to the list for the newly created middle block SUB.

As a result, rN3-, NlB2.
Block data N1:J is obtained (formally, this data is equivalent to the above-mentioned data (2), although the character string rSUBJ, which is the name of the block itself, is omitted). Then, the list of upper layer blocks is replaced with the other data (3). That is, the data [N5-B2, Nl, B3, N4; J (extracted data) in the third line of FIG. As a result, the rN-=3J column in the list for block TOP is modified as shown in FIGS. 8 to 10. If we rearrange the above process again, we get the following.

A: Extract the third row of data (1) from the “rap” list (Figure 8).

B: Data (2) based on extracted data (1)
, (3) was created.

C: Add data (2) to the SUB list (3rd line in Figure 11).

D: Replace data (1) in the 3rd line of the TOP list with data (3) (1st line in Figure 10).

Next, N4-B2, N2 . B3, N5; (4
), when we actually perform the processing in step S5, we find that by generating new terminals (SUB, N2), N4-8UB, N2. B3, N5; (5)
N4=SUB, N2. B2, N2; (6)
Two block data can be created. therefore,
The processing in step S5 can be summarized as follows.

A: Extract the 4th line of data (4) from the TOP list (Figure 8).

B: Data (5) based on extracted data (4)
, create (B).

C: Add data (5) to the SUB list (line 4 in Figure 11).

D: Replace data (4) in the 3rd line of the Top list with data (6) (2nd line in Figure 10).

Finally, r on the 5th line of the block TOP list in Figure 8.
N5-B3, N1. The terminal determination in step S3 is performed for the data B4, N6;J. here,
Two terminals (B3, N1) and (B4, N6)
It is recognized that the former belongs to block B3 and the latter belongs to block B4. By the way, neither blocks B3 nor B4 are target blocks. Therefore, the third state is determined in step S3,
Step S6 is reached without any processing being performed.

Therefore, the data in the rN 5-J column of the fifth row of list I in the block TOP of FIG. 8 remains as is in the list of FIG. 10.

Thus, in step S6, it is determined that all data regarding the upper layer block (block TOP) has been extracted, and all modification procedures are completed. In the end, of the list of five blocks shown in FIG. 8, the list of block TOP was modified as shown in FIG. 10,
A new list of blocks SUB shown in FIG. 11 will be added.

Note that the above-mentioned embodiment shows one embodiment of the present invention, and the present invention can be implemented in various other embodiments. For example, a new terminal name may be given using a different nomenclature, or a netlist may be written using a different method.

〔Effect of the invention〕

As described above, according to the method for modifying a netlist for a semiconductor integrated circuit of the present invention, a plurality of target lower blocks,
When making a modification such as defining a new middle block between an upper block defined in the hierarchy above this lower block, the list for the upper block will be modified, and a new block will be added to the list for the middle block. Since the list is automatically created based on data sequentially extracted from the original list of upper-layer blocks, the operator only has to perform input work to specify the target block.

[Brief explanation of the drawing]

Figure 1 is a flowchart showing the steps of the method for modifying a netlist for semiconductor integrated circuits according to the present invention, Figure 2 is a diagram showing the design process of a general semiconductor integrated circuit, and Figure 3 is a diagram showing the net list created during logic design. Figure 4 is a diagram showing the list. Figure 4 is a diagram showing the netlist required during layout design. Figures 5 and 6 are layout diagrams explaining the need to make modifications to the netlist during layout design. Figure 7. is the logic circuit diagram before modification, Figure 8 is the netlist diagram before modification, Figure 9 is the logic circuit diagram after modification, Figure 10 is the netlist diagram of the upper layer block after modification, and Figure 11 is after modification. FIG. 7 is a netlist diagram of an added middle layer block. TOP...upper layer block, SUB...middle layer block, B1-B4...lower layer block, X1-X8...lowest block (logic element), N1-N7...node 1
, N1~. N7...terminal. Patent applicant: Dai Nippon Printing Co., Ltd. Applicant's agent: Patent attorney Hiroshi Shimura (Figure 3)

Claims (1)

[Claims] For a netlist constructed by classifying each component of a semiconductor integrated circuit into blocks having a hierarchical structure and defining block data indicating connection relationships within the blocks for each block, In a method for making a modification such as defining a new middle block between a plurality of target lower blocks and an upper block defined in a hierarchy above the lower block, the plurality of lower blocks and the inputting a modification instruction specifying the upper layer block;
Focusing on the step of extracting block data defined for the upper layer block one node at a time and the plurality of terminals whose connection relationships are indicated by the extracted data, all of the plurality of terminals are terminals for the lower layer block. If so, it is determined to be the first state, if some of the terminals are for the lower block, it is determined to be the second state, and if none of the terminals are for the lower block, the third state is determined. and when the first state is determined, moving the extracted data from the list for the upper block to a newly created list for the middle block; 2, generates a new terminal, and creates two block data indicating the connection relationship between this new terminal and some of the plurality of terminals whose connection relationships are indicated by the extracted data; replacing the extracted data in the list for the upper block with one of the block data and adding the other block data to the newly created list; and the third state; A method for modifying a netlist for a semiconductor integrated circuit, comprising the steps of not modifying the list when the determination is made.