JPS6329187U - - Google Patents
Info
- Publication number
- JPS6329187U JPS6329187U JP12164986U JP12164986U JPS6329187U JP S6329187 U JPS6329187 U JP S6329187U JP 12164986 U JP12164986 U JP 12164986U JP 12164986 U JP12164986 U JP 12164986U JP S6329187 U JPS6329187 U JP S6329187U
- Authority
- JP
- Japan
- Prior art keywords
- address
- clock
- input line
- bit input
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Description
第１図はこの考案の機能ブロツク図、第２図は
この考案の一実施例の全体構成図、第３図は表示
ＲＡＭと表示スクリーンとの位置対応を示す図、
第４図は実施例の要部のエデイツトアドレスカウ
ンタの構成図、第５図は変形例の構成図である。
２……エデイツトアドレスカウンタ、ａ……エ
デイツトアドレスインクリメントクロツク、ｃ…
…インクリメントモードラツチパルス、ＬＴ……
ラツチ、ＤＣ……デコーダ、Ｎ……ＮＯＲゲート
、ＯＡ１〜ＯＡＮ―１……オアアンドゲート、Ｆ
１〜ＦＮ……フリツプフロツプ。
FIG. 1 is a functional block diagram of this invention, FIG. 2 is an overall configuration diagram of an embodiment of this invention, and FIG. 3 is a diagram showing the positional correspondence between the display RAM and the display screen.
FIG. 4 is a block diagram of an edit address counter, which is a main part of the embodiment, and FIG. 5 is a block diagram of a modified example. 2...Edit address counter, a...Edit address increment clock, c...
...Increment mode latch pulse, LT...
Latch, DC...decoder, N...NOR gate, OA1~OAN-1...OR-AND gate, F
1~FN...Flip-flop.
Claims (1)
モリに対する一連のアドレスを発生可能なアドレ
ス発生手段を備える表示制御装置において、 上記アドレス発生手段が、 第１のビツト入力線にクロツクが与えられた場
合に表示スクリーン上を行方向に歩進するアドレ
スを発生し、第２のビツト入力線にクロツクが与
えられた場合に表示スクリーン上を列方向に歩進
するアドレスを発生するプリセツト可能なバイナ
リ方式のアドレスカウンタと、 選択制御情報に従つて上記の第１または第２の
ビツト入力線にクロツクを通す選択回路と、 を有することを特徴とする表示制御装置。[Claims for Utility Model Registration] A display control device comprising address generation means capable of generating a series of addresses for the display memory for editing the contents of the display memory, wherein the address generation means is connected to a first bit input line. Generates an address to step in the row direction on the display screen when a clock is applied, and generates an address to step in the column direction on the display screen when a clock is applied to the second bit input line. A display control device comprising: a presettable binary address counter; and a selection circuit that passes a clock to the first or second bit input line in accordance with selection control information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12164986U JPS6329187U (en) | 1986-08-09 | 1986-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12164986U JPS6329187U (en) | 1986-08-09 | 1986-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6329187U true JPS6329187U (en) | 1988-02-25 |
Family
ID=31011120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12164986U Pending JPS6329187U (en) | 1986-08-09 | 1986-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6329187U (en) |
-
1986
- 1986-08-09 JP JP12164986U patent/JPS6329187U/ja active Pending
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