JPS6331458U - - Google Patents
Info
- Publication number
- JPS6331458U JPS6331458U JP12522486U JP12522486U JPS6331458U JP S6331458 U JPS6331458 U JP S6331458U JP 12522486 U JP12522486 U JP 12522486U JP 12522486 U JP12522486 U JP 12522486U JP S6331458 U JPS6331458 U JP S6331458U
- Authority
- JP
- Japan
- Prior art keywords
- key
- key input
- latch
- instruction signal
- input circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electric Clocks (AREA)
- Calculators And Similar Devices (AREA)
- Input From Keyboards Or The Like (AREA)
Description
第１図は本考案の一実施例の構成を示す回路ブ
ロツク図、第２図はキー入力部の具体例を示す回
路図、第３図は上記実施例の動作を示すフローチ
ヤート、第４図は従来例の電子時計の構成を示す
回路ブロツク図、第５図は第４図におけるキー入
力部の回路図、第６図は第４図の電子時計の動作
を示すフローチヤートである。
１……ＲＯＭ、４……ＲＡＭ、６……キー入力
部、１１……ラツチ、１２ａ〜１２ｄ……ＥＯＲ
ゲート、１３……オアゲート、Ｓ１〜Ｓ４……キ
ー。
Fig. 1 is a circuit block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a circuit diagram showing a specific example of the key input section, Fig. 3 is a flowchart showing the operation of the above embodiment, and Fig. 4. 5 is a circuit diagram showing the configuration of a conventional electronic timepiece, FIG. 5 is a circuit diagram of the key input section in FIG. 4, and FIG. 6 is a flowchart showing the operation of the electronic timepiece shown in FIG. 4. 1...ROM, 4...RAM, 6...key input section, 11...latch, 12a-12d...EOR
Gate, 13...OR gate, S1 to S4 ...key.
Claims (1)
つて装置の動作を制御する制御部に、キーの指示
信号を送出するキー入力回路において、 前記キーの入力状態をラツチするラツチ手段と
、 該ラツチ手段のデータと現在のキーの入力状態
とを比較し、両方が一致したときはキーの指示な
し信号を出力する手段とを設けたことを特徴とす
るキー入力回路。[Claims for Utility Model Registration] In a key input circuit that sends a key instruction signal to a control unit that controls the operation of the device by a microprogram stored in a storage means, a latch that latches the input state of the key is provided. A key input circuit comprising: means for comparing the data of the latch means with the current key input state, and outputting a key no instruction signal when both match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12522486U JPS6331458U (en) | 1986-08-15 | 1986-08-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12522486U JPS6331458U (en) | 1986-08-15 | 1986-08-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331458U true JPS6331458U (en) | 1988-03-01 |
Family
ID=31017941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12522486U Pending JPS6331458U (en) | 1986-08-15 | 1986-08-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331458U (en) |
-
1986
- 1986-08-15 JP JP12522486U patent/JPS6331458U/ja active Pending
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