JPS6155221U - - Google Patents
Info
- Publication number
- JPS6155221U JPS6155221U JP13940484U JP13940484U JPS6155221U JP S6155221 U JPS6155221 U JP S6155221U JP 13940484 U JP13940484 U JP 13940484U JP 13940484 U JP13940484 U JP 13940484U JP S6155221 U JPS6155221 U JP S6155221U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- operating state
- oscillation circuit
- bias oscillation
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
Description
第１図は本考案テープレコーダの一実施例の回
路系統図、第２図及び第３図は第１図の動作説明
用フローチヤート、第４図及び第５図は第１図の
動作説明用タイミングチヤートである。
１…バイアス発振回路、２…検波回路、３…イ
ンバータ、４…微分回路、５…シユミツト回路、
６…スイツチ検出回路、７…メカニズム制御回路
、８…出力制御回路、９…状態検出回路、１０１
〜１０４…ＣＰＵ端子、Ｑ１〜Ｑ３…トランジス
タ、ＳＷ…パワースイツチ。
Figure 1 is a circuit diagram of an embodiment of the tape recorder of the present invention, Figures 2 and 3 are flowcharts for explaining the operation of Figure 1, and Figures 4 and 5 are for explaining the operation of Figure 1. This is a timing chart. 1... Bias oscillation circuit, 2... Detection circuit, 3... Inverter, 4... Differential circuit, 5... Schmitt circuit,
6...Switch detection circuit, 7...Mechanism control circuit, 8...Output control circuit, 9...State detection circuit, 10 1
~ 104 ...CPU terminal, Q1 ~ Q3 ...Transistor, SW...Power switch.
Claims (1)
構成のテープレコーダにおいて、パワースイツチ
の操作に応じてバイアス発振回路を動作状態及び
非動作状態にする回路と、該バイアス発振回路が
動作状態にある時上記マイクロコンピユータをウ
エイクアツプ状態にする一方、該バイアス発振回
路が非動作状態にある時上記マイクロコンピユー
タをスリープ状態にする回路とを設けてなるテー
プレコーダ。 In a tape recorder having a configuration in which various operations are controlled by a microcomputer, there is provided a circuit that turns a bias oscillation circuit into an operating state or a non-operating state according to the operation of a power switch, and a circuit that turns a bias oscillation circuit into an operating state and a non-operating state according to the operation of a power switch, and when the bias oscillation circuit is in an operating state, the microcomputer controls the bias oscillation circuit. 1. A tape recorder comprising a circuit that wakes up a computer and puts the microcomputer into a sleep state when the bias oscillation circuit is in an inactive state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13940484U JPH045043Y2 (en) | 1984-09-17 | 1984-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13940484U JPH045043Y2 (en) | 1984-09-17 | 1984-09-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6155221U true JPS6155221U (en) | 1986-04-14 |
| JPH045043Y2 JPH045043Y2 (en) | 1992-02-13 |
Family
ID=30697783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13940484U Expired JPH045043Y2 (en) | 1984-09-17 | 1984-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH045043Y2 (en) |
-
1984
- 1984-09-17 JP JP13940484U patent/JPH045043Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH045043Y2 (en) | 1992-02-13 |