JPS63288516A - Transistor circuit - Google Patents

Transistor circuit

Info

Publication number
JPS63288516A
JPS63288516A JP62124232A JP12423287A JPS63288516A JP S63288516 A JPS63288516 A JP S63288516A JP 62124232 A JP62124232 A JP 62124232A JP 12423287 A JP12423287 A JP 12423287A JP S63288516 A JPS63288516 A JP S63288516A
Authority
JP
Japan
Prior art keywords
channel mos
turned
transistor
mos transistor
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62124232A
Other languages
Japanese (ja)
Inventor
Yoshinori Sakakibara
榊原　美紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62124232A priority Critical patent/JPS63288516A/en
Publication of JPS63288516A publication Critical patent/JPS63288516A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Abstract

PURPOSE:To increase the current supply capability to a load and to attain high) speed switching by connecting a bipolar NPN transistor (TR) and an N-channel MOS TR between a power supply and a ground point, connecting the emitter of the bipolar element and the drain of the MOS element so as to form an output terminal. CONSTITUTION:In applying a low level voltage to an input terminal 3, the P-channel MOS TR 14 and the NPN TR 11 are turned on, the N-channel MOS TR 12 is turned off and the output reaches a high level. In applying a high level voltage to the input terminal 3, the TRs 14, 11 are turned off, the TR 12 is turned on and the output goes to a low level. The N-channel MOS TR 13 is turned on in this case and the base electric charge of the TR 11 is given to the emitter, then the switching speed of changeover of on/off of the TR 11 is quickened and the current supply capability to the load 15 is increased.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、負荷へ供給できる電流能力を大きくし、スイ
ッチングスピードを高めたトランジスタ回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a transistor circuit with increased current capability that can be supplied to a load and increased switching speed.

従来の技術 従来より、Ｃ−ＭＯＳの基本回路は、第２図のように、
電源Ｖｃｃ接地点との間に、ＰチャネルＭｏＳトランジ
スタ１とＮチャネルＭＯＳトランジスタ２とを直列接続
し、各ゲートを共通接続して入力端子３、ドレインを出
力端子４として使用されている。Conventional technology Conventionally, the basic circuit of C-MOS is as shown in Figure 2.
A P-channel MoS transistor 1 and an N-channel MOS transistor 2 are connected in series between a power supply Vcc and a ground point, and their gates are commonly connected to use an input terminal 3 and a drain as an output terminal 4.

このように構成されたＣ−ＭＯＳ基本回路は、入力端子
３にＨレベルの電圧が印加されると、ＰチャネルＭＯＳ
トランジスタ１がオフ、ＮチャネルＭＯＳ　トランジス
タ２がオンとなって、出力レベルは低レベルになり、入
力端子３に低レベルの電圧が印加されると、Ｐチャネル
ＭＯＳトランジスタ１がオン、ＮチャネルＭＯＳトラン
ジスタ２がオフとなって、出力レベルは高レベルとなり
、インバータの働きをする。In the C-MOS basic circuit configured in this way, when an H level voltage is applied to the input terminal 3, the P-channel MOS
Transistor 1 is turned off, N-channel MOS transistor 2 is turned on, and the output level becomes low level. When a low-level voltage is applied to input terminal 3, P-channel MOS transistor 1 is turned on, and N-channel MOS transistor 2 is turned off, the output level becomes high level, and it functions as an inverter.

発明が解決しようとする問題点 しかしながら、上記従来の回路では、ＰチャネルＭＯＳ
トランジスタ２の電流容量が小さいので、容量の大きな
負荷のときには、充電時間が長（なってしまうという問
題がある。本発明は、バイポーラのＮＰＮトランジスタ
を使って、電流容量を太き（するとともに、ターンオフ
時にベース領域の電荷をＮチャネルＭＯ８トランジスタ
を使って逃がすことによって、スイッチングスピードを
速くすることを目的とする。Problems to be Solved by the Invention However, in the above conventional circuit, the P-channel MOS
Since the current capacity of the transistor 2 is small, there is a problem that charging time becomes long when a load with a large capacity is used.The present invention uses a bipolar NPN transistor to increase the current capacity (as well as increase the current capacity). The purpose is to increase the switching speed by dissipating the charge in the base region using an N-channel MO8 transistor at turn-off.

問題点を解決するための手段 この目的を達成するために、本発明の論理回路は、電源
Ｖｃｃと接地点との間に、バイポーラのＮＰＮトランジ
スタとＮチャネルＭＯＳトランジスタを接続し、ＮＰＮ
　トランジスタのエミッタとＮチャネルＭＯ８トランジ
スタのドレインとを接続して出力端子とし、ＮＰＮ　ト
ランジスタのベースとエミッタをＮチャネルＭＯＳトラ
ンジスタを介して接続してなるものである。Means for Solving the Problems In order to achieve this object, the logic circuit of the present invention connects a bipolar NPN transistor and an N-channel MOS transistor between a power supply Vcc and a ground point.
The emitter of the transistor and the drain of an N-channel MO8 transistor are connected to form an output terminal, and the base and emitter of an NPN transistor are connected via an N-channel MOS transistor.

作用 この構造によって、出力端子の電圧が低レベルの電圧か
ら高レベルの電圧に切り替わる時、ＮＰＮトランジスタ
のベースとエミッタの間にあるＮチャネルＭＯＳトラン
ジスタがオンして、ベースの電荷をエミッタに逃がすこ
とができるので、ＮＰＮトランジスタのオンからオフへ
の切り替わりのスイッチングスピードを速くすることが
できる。Effect: With this structure, when the voltage at the output terminal switches from a low level voltage to a high level voltage, the N-channel MOS transistor located between the base and emitter of the NPN transistor is turned on and the base charge is released to the emitter. Therefore, the switching speed of the NPN transistor from on to off can be increased.

実施例 以下本発明の一実施例について、第１図の回路図を参照
しながら説明する。第１図において、１１は出力が高レ
ベルの時に電流を流し出すためのＮＰＮトランジスタ、
１２は出力が低レベルの時に導通して電流を接地点に流
し込むＮチャネルＭＯ８トランジスタ、１３はＮチャネ
ルＭＯＳトランジスタ、１４はＰチャネルＭＯ３トラン
ジスタ、１５は抵抗である。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the circuit diagram shown in FIG. In FIG. 1, 11 is an NPN transistor for flowing current when the output is at a high level;
12 is an N-channel MO8 transistor that is conductive when the output is at a low level and allows current to flow into the ground point; 13 is an N-channel MOS transistor; 14 is a P-channel MO3 transistor; and 15 is a resistor.

以上の構造により、入力端子３に低レベルの電圧が印加
された場合には、ＰチャネルＭＯＳトランジスタ１４が
オンになるので、ＮＰＮトランジスタ１１はオンになり
、ＮチャネルＭＯＳトランジスタ１２はオフになるので
、出力は高レベルになる。また、入力端子３に高レベル
の電圧が印加された場合には、ＰチャネルＭＯＳトラン
ジスタ１４がオフになるので、ＮＰＮトランジスタ１１
はオフとなり、ＮチャネルＭＯＳトランジスタ１２はオ
ンになるので、出力は低レベルになる。With the above structure, when a low level voltage is applied to the input terminal 3, the P channel MOS transistor 14 is turned on, the NPN transistor 11 is turned on, and the N channel MOS transistor 12 is turned off. , the output will be at a high level. Further, when a high level voltage is applied to the input terminal 3, the P channel MOS transistor 14 is turned off, so the NPN transistor 11
is turned off and N-channel MOS transistor 12 is turned on, so the output becomes a low level.

この時、ＮチャネルＭＯＳトランジスタ１３はオンとな
り、これを通してＮＰＮトランジスタ１１のベースの電
荷をエミッタへ逃がすことができるので、同ＮＰＮトラ
ンジスタ１１のオンからオフへの切り替わりのスイッチ
ングスピードを速くすることができる。At this time, the N-channel MOS transistor 13 is turned on, through which the charge at the base of the NPN transistor 11 can be released to the emitter, thereby increasing the switching speed of the NPN transistor 11 from on to off. .

発明の効果 以上のように、本発明の論理回路によると、負荷への電
流供給能力が大きくなるとともに、高速スイッチング動
作を可能にするものである。Effects of the Invention As described above, the logic circuit of the present invention increases the ability to supply current to a load and enables high-speed switching operation.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例論理回路の回路図、第２図は従
来例の回路図である。 ３・・・・・・入力端子、４・・・・・・出力端子、１
１・・・・・・ＮＰＮトランジスタ、１２．１３・・・
・・・ＮチャネルＭＯＳトランジスタ、１４・・・・・
・ＰチャネルＭＯＳトランジスタ、１５・・・・・・抵
抗。FIG. 1 is a circuit diagram of a logic circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 3...Input terminal, 4...Output terminal, 1
1...NPN transistor, 12.13...
...N-channel MOS transistor, 14...
・P-channel MOS transistor, 15... Resistor.

Claims (1)

【特許請求の範囲】[Claims] 電源にコレクタを接続したバイポーラトランジスタのエ
ミッタと、ソース接地した第１のＮチャネルＭＯＳトラ
ンジスタのドレインとを接続し、前記バイポーラトラン
ジスタのベースに、ソースを前記電源に接続した第１の
ＰチャネルＭＯＳトランジスタのドレインと、ソースを
前記バイポーラトランジスタのエミッタに接続した第２
のＮチャネルＭＯＳトランジスタのドレインとの接続点
を結合し、前記第１のＰチャネルＭＯＳトランジスタの
ゲートと前記第１のＮチャネルＭＯＳトランジスタのゲ
ートと前記第２のＮチャネルＭＯＳトランジスタのゲー
トとを共通接続したことを特徴とするトランジスタ回路
。The emitter of a bipolar transistor whose collector is connected to a power supply is connected to the drain of a first N-channel MOS transistor whose source is grounded, and the base of the bipolar transistor is connected to a first P-channel MOS transistor whose source is connected to the power supply. a second transistor whose drain and source are connected to the emitter of the bipolar transistor;
A connection point with the drain of the N-channel MOS transistor is connected, and the gate of the first P-channel MOS transistor, the gate of the first N-channel MOS transistor, and the gate of the second N-channel MOS transistor are connected in common. A transistor circuit characterized by being connected.
JP62124232A 1987-05-21 1987-05-21 Transistor circuit Pending JPS63288516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62124232A JPS63288516A (en) 1987-05-21 1987-05-21 Transistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62124232A JPS63288516A (en) 1987-05-21 1987-05-21 Transistor circuit

Publications (1)

Publication Number Publication Date
JPS63288516A true JPS63288516A (en) 1988-11-25

Family

ID=14880246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62124232A Pending JPS63288516A (en) 1987-05-21 1987-05-21 Transistor circuit

Country Status (1)

Country Link
JP (1) JPS63288516A (en)

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