JPH0685498B2 - Logic circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a logic circuit technique and a technique particularly effective when applied to a logic circuit of high driving force and high speed,
For example, it relates to a technique effectively used for a logic circuit in a gate array.

[Background technology]

Conventional logic circuits are bipolar transistors or MO
It was composed of only one element of the S field effect transistor.

However, recently, for example, as described in the application specification of Japanese Patent Application No. 58-12711, a so-called Bi-MOS type logic circuit using both a bipolar transistor and a MOS field effect transistor has been developed. It has come to be composed. This Bi-MOS type logic circuit has been attracting attention because it has both the current driving capability of a bipolar transistor and the low power consumption of a MOS field effect transistor.

However, the conventional Bi-MOS type logic circuit of this type is configured by providing a driving stage using a MOS field effect transistor in a bipolar type logic circuit such as TTL, so There was a tendency that the number of stages (the number of stages) up to the output increased. For this reason,
It has been made clear by the present inventor that there are problems that the operation speed is reduced, the number of circuit elements is increased, and the electric power consumed outside the output operation is large. And, these problems have a minimum dimension of 2 μm.
It has been found that it becomes remarkable in the following highly integrated circuit devices.

[Object of the Invention]

An object of the present invention is to improve the operation speed by reducing the number of stages from the input to the output of the logic circuit, reduce the number of circuit elements, and reduce the power consumed except for the output operation to improve the power utilization efficiency. It is intended to provide a logic circuit technology capable of doing so.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the C-MOS inverter section drives the output stage section of the bipolar transistor, while the operating power supply of the C-MOS inverter section is supplied from the base of the bipolar transistor of the output stage section to output from the input of the logic circuit. The number of stages is reduced to improve the operation speed, the number of circuit elements is reduced, and the power consumed except for the output operation is reduced to improve the power utilization efficiency.

〔Example〕

Hereinafter, representative embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a logic circuit according to the present invention.

First, the logic circuit shown in the figure is configured as a logic circuit in a gate array, particularly as an inverter, and is configured using bipolar transistors and MOS field effect transistors.

The logic circuit of the embodiment shown in FIG. 1 comprises an input circuit 1 and an output circuit 2, and operates between the power supply V _CC and the ground potential.

The input circuit 1 is an emitter follower composed of a pnp bipolar transistor Q1, a resistor R1 and a diode D1. The input circuit 1 is provided as an input protection circuit or a buffer, and can be omitted in the logic circuit used inside the gate array.

The output circuit 2 is a main part of the logic circuit,
It is composed of a C-MOS inverter unit 21 and an output stage unit 22.

The C-MOS inverter unit 21 includes a p-channel MOS field effect transistor M1 and an n-channel MOS field effect transistor M2.
Composed by.

The output stage section 22 is configured by connecting the pnp bipolar transistor Q2 and the npn bipolar transistor Q3 in series with their collectors in common.

Here, the C-MOS inverter section 21 is designed such that its operating power supply is given from the base of the pnp bipolar transistor Q2 and the base of the npn bipolar transistor Q3. On the other hand, the output of the C-MOS inverter section 21 is connected to the common collector of the pnp bipolar transistor Q2 and the npn bipolar transistor Q3. Then, the logic input in via the input circuit 1 is introduced to the input of the C-MOS inverter unit 21. Further, the logical output out is derived from the common collector. A capacitive load CL is connected to the logic output out, for example, to a MOS gate of another logic circuit.

Furthermore, the pnp bipolar transistor Q2 and the n
Resistors R2 and R3 are inserted in parallel between each base and emitter of the pn bipolar transistor Q3.

Next, the operation will be described.

FIG. 2 shows the operation of the logic circuit with current direction arrows for each state.

First, as shown in FIG. 9A, when the logic input in rises from "L" to "H", the input of the C-MOS inverter section 21 changes from "L" to "H". As a result, the p-channel MOS field effect transistor M1 on the power supply V _CC side turns from ON (conduction) to OFF.
(Non-conductive), the n-channel MOS field effect transistor on the ground potential side is turned off (non-conductive) to on (conductive). Then, from the capacitive load CL connected to the output out to n
The base current Ib3 is supplied to the npn bipolar transistor Q3 on the ground potential side via the channel MOS field effect transistor M2. As a result, the collector current Ic3 comes to flow through the npn bipolar transistor Q3. As a result, the charge of the load CL is rapidly discharged, and the output out is "H".
To "L". On the other hand, the pnp bipolar transistor Q2 on the power supply V _CC side changes from ON (conducting) to OFF (non-conducting) by discharging the residual base charge through the resistor R2, as shown by the dotted arrow in the figure. Change rapidly.

Next, as shown in FIG. 7B, when the logic input in rises from "H" to "L", the input of the C-MOS inverter section 21 changes from "H" to "L". As a result, the p-channel MOS field effect transistor M1 on the power supply V _CC side is turned off (non-conductive).
It is turned on (conducting), and the n-channel MOS field effect transistor on the ground potential side is turned on (conducting) and turned off (non-conducting). Then, the base current Ib2 flows from the power source V _CC through the p-channel MOS field effect transistor M1 to the pnp bipolar transistor Q2 on the power source V _CC side. This allows that pnp
The bipolar transistor Q2 turns ON (conducts). As a result, the collector current Ic2 and the base current Ib2 of the pnp bipolar transistor Q2 simultaneously flow into the load CL connected to the output out. As a result, the load CL is rapidly charged,
Output out is inverted from "L" to "H". On the other hand, the npn bipolar transistor Q3 on the ground potential side rapidly changes from ON (conducting) to OFF (non-conducting) by discharging the residual base charge through the resistor R3, as shown by the dotted arrow in the figure. Change to.

As described above, the logic of the input in is inverted and appears in the output out.

In the logic circuit described above, first, since the number of stages from the input to the output is only two, signal transmission can be made very fast. That is, the operating speed can be improved. At the same time, the circuit is simplified and the number of required circuit elements can be greatly reduced. Further, it is easy to increase the integration density of the semiconductor integrated circuit device or reduce the size of the semiconductor chip.

Next, when the output out is “L”, the current from the current V _CC is not required. Further, when the output out is “H”, both the collector current and the base current of the bipolar transistor Q2 are discharged from the output out. That is, the current from the power supply V _CC is
Almost all of it is used to drive the load CL connected to the output out, and the power consumed except for the output operation is very small. As a result, it is possible to significantly improve power utilization efficiency and reduce power consumption.

〔effect〕

(1) The C-MOS inverter section drives the output stage section of the bipolar transistor, while the operating power of the C-MOS inverter section is supplied from the base of the bipolar transistor of the output stage section. The effect that the operating speed can be improved by reducing the number of stages from the input to the output is obtained.

(2) At the same time, the circuit is simplified, and the number of necessary circuit elements can be significantly reduced.

(3) Further, by simplifying the circuit, it is possible to increase the integration density of the semiconductor integrated circuit device or reduce the size of the semiconductor chip.

(4) Next, almost all of the current from the power supply V _CC is effectively used to drive the load connected to the output, reducing the power consumed other than the output operation and significantly reducing the power consumption. The effect is that it can be reduced to a very low level.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, the resistance R
2, R3 may be equivalent resistances of active elements such as MOS field effect transistors.

[Field of application]

In the above description, the case where the invention made by the present inventor is mainly applied to the logic circuit technology in the gate array which is the field of application which is the background has been described, but the present invention is not limited thereto, and, for example, a semiconductor integrated circuit. It can also be applied to logic circuit technology in a storage device. It can be applied at least to the condition that constitutes a logic circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a logic circuit according to the present invention, and FIGS. 2 (a) and 2 (b) are circuit diagrams showing the operation of the logic circuit according to an embodiment of the present invention. 1 …… input circuit, 2 …… output circuit, 21 …… C-MOS inverter section, 22 …… output stage section, Q1, Q2 …… pnp bipolar transistor, Q3 …… npn bipolar transistor, M1 ……
p-channel MOS field effect transistor, M2 ... n-channel MOS field effect transistor, R1, R2, R3 ... resistor, D
1 …… Diode, V _CC …… Power supply, in …… Logic input, out
…… Logic output, CL …… Load.

Claims (1)

[Claims] 1. A logic circuit formed by a semiconductor integrated circuit, wherein an input signal inputted from an external terminal is supplied to a base, an emitter follower input transistor, and a load resistor provided at the emitter of the emitter follower input transistor. A diode for level-shifting and transmitting the operating voltage to the load resistance, and the emitter output of the emitter follower input transistor is supplied to the gate of p
C-MOS consisting of channel MOSFET and n-channel MOSFET
An inverter circuit, a resistance element that supplies an operating voltage to the sources of the p-channel MOSFET and the n-channel MOSFET, a pnp bipolar transistor whose base is connected to the source of the p-channel MOSFET, and a base of the source of the n-channel MOSFET. And an npn bipolar transistor connected to each other, and both collectors of the pnp bipolar transistor and the npn bipolar transistor are connected to the C
-A logic circuit which is commonly connected with the output terminal of a MOS inverter circuit to obtain an output signal for driving a capacitive load.