JPS63283139A - Method for packaging semiconductor element - Google Patents

Method for packaging semiconductor element

Info

Publication number
JPS63283139A
JPS63283139A JP11929887A JP11929887A JPS63283139A JP S63283139 A JPS63283139 A JP S63283139A JP 11929887 A JP11929887 A JP 11929887A JP 11929887 A JP11929887 A JP 11929887A JP S63283139 A JPS63283139 A JP S63283139A
Authority
JP
Japan
Prior art keywords
tape carrier
metal
semiconductor element
metal conductor
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11929887A
Other languages
Japanese (ja)
Inventor
Tomoyuki Nakai
智之 中井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP11929887A priority Critical patent/JPS63283139A/en
Publication of JPS63283139A publication Critical patent/JPS63283139A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize a high-density package of semiconductor elements on a tape carrier without holes by a method wherein a semiconductor element is connected to a metal protrusion formed at an end of a metal conductor. CONSTITUTION:Metal conductors 12 are built on a tape carrier 11 so that the tape carrier 11 itself will serve as a circuit board. A resist 14 is provided on a substrate 13 for metal protrusion formation and, to the resist 14 at its prescribed position, a metal protrusion 15 is attached. The metal protrusion 15 is connected to an end of the metal conductor 12, pressure is exerted by using a pressing block 16, and an ultrasonic heater 17 is activated in an ultrasonic bonding process. The ultrasonic heater 17 is activated again in a process of attaching a semiconductor element 18 to the protrusion 15 on the tape carrier 11, which is accomplished at a lower temperature under pressure. A metal conductor may be fixed secure to a tape carrier in this method, and an enhanced-density package realizes of semiconductor elements on a tape carrier.

Description

【発明の詳細な説明】 〔発明の分野〕 本発明はテープキャリアを用いた半導体素子の実装方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for mounting semiconductor devices using a tape carrier.

〔従来技術とその問題点〕[Prior art and its problems]

(従来技術) 従来テープキャリアを用いて多数の半導体素子を基板上
に実装する場合には、例えば第4図に示すように両側に
一定間隔毎に設けられたスプロケットホールを有するテ
ープキャリア1の所定位置にデバイスホール2や切断用
ホール3を形成し、その上部に金属導体4を形成する。
(Prior Art) When mounting a large number of semiconductor elements on a substrate using a conventional tape carrier, for example, as shown in FIG. A device hole 2 and a cutting hole 3 are formed at the positions, and a metal conductor 4 is formed above them.

そして金属導体4の端部に金属突起(Auバンプ等)5
を形成すると共に、第5図(a)、 (b)に示すよう
に押さえ部材6を用いて半導体素子7を例えば熱圧着に
より接続し、必要な個所で金属導体4を切断しフォーミ
ングして基FiB上に実装するようにしていた。
Then, a metal protrusion (Au bump, etc.) 5 is attached to the end of the metal conductor 4.
At the same time, as shown in FIGS. 5(a) and 5(b), the semiconductor elements 7 are connected by, for example, thermocompression bonding using the holding member 6, and the metal conductor 4 is cut and formed at necessary locations to form the base. I was trying to implement it on FiB.

(発明が解決しようとする問題点) しかしながらこのような従来のテープキャリア法におい
て、テープキャリア自体を基板として用いる場合がある
。このような場合にはデバイスホールや切断用ホールの
部分に回路パターンを形成することができず、回路パタ
ーンの自由度が制限されるという問題点があった。
(Problems to be Solved by the Invention) However, in such conventional tape carrier methods, the tape carrier itself may be used as a substrate. In such a case, there is a problem that a circuit pattern cannot be formed in the device hole or the cutting hole, and the degree of freedom of the circuit pattern is restricted.

又デバイスホールが存在するため半導体素子7を接続す
る場合には、第5図(alに示すように金属導体4の一
部のみがテープキャリア1に支持されている状態となる
。従って金属突起5の形成や半導体素子7の接続時には
金属導体4の一部が折れ曲がって接続不良になる恐れが
あるという欠点もあった。そのため半導体素子間の間隔
をあまり広げることができず、テープキャリア上に半導
体素子を高密度実装することができなかった。
Further, since the device hole exists, when connecting the semiconductor element 7, only a part of the metal conductor 4 is supported by the tape carrier 1 as shown in FIG. There is also a drawback that there is a risk that a part of the metal conductor 4 may be bent, resulting in a poor connection when forming the semiconductor element 7 or connecting the semiconductor element 7.For this reason, it is not possible to widen the gap between the semiconductor elements, and the semiconductor element 7 is placed on the tape carrier. It was not possible to mount elements at high density.

〔発明の目的〕[Purpose of the invention]

本発明はこのような従来の半導体素子の実装方法の問題
点に鑑みてなされたものであって、テープキャリアを回
路基板として用いて半導体素子を高密度実装できるよう
にすると共に、実装時の信顛性を向上することを技術的
課題とする。
The present invention has been made in view of the problems of the conventional semiconductor device mounting method, and it enables high-density mounting of semiconductor devices using a tape carrier as a circuit board, and also improves reliability during mounting. The technical challenge is to improve the flexibility.

〔発明の構成と効果〕[Structure and effects of the invention]

(問題点を解決するための手段) 本発明はテープキャリアを用いた半導体素子の実装方法
であって、第1図に示すように、テープキャリア上に金
属導体による回路パターンを形成する工程と、テープキ
ャリア上の金属導体の端部に金属突起を形成する工程と
、テープキャリアの金属導体側より半導体素子の電極端
子を金属突起に接続する工程と、を有し、テープキャリ
アを用いて半導体素子を実装することを特徴とするもの
である。
(Means for Solving the Problems) The present invention is a method for mounting a semiconductor element using a tape carrier, which includes the steps of forming a circuit pattern using a metal conductor on the tape carrier, as shown in FIG. The steps include forming a metal protrusion on the end of the metal conductor on the tape carrier, and connecting the electrode terminal of the semiconductor element to the metal protrusion from the metal conductor side of the tape carrier. It is characterized by implementing the following.

(作用) このような特徴を有する本発明によれば、テープキャリ
アに半導体素子を取付ける位置にもデバイスホールやパ
ターン切断用のホールを形成することなく接続用パター
ンとして金属導体を形成している。そして金属導体の端
部に接合用金属突起を形成すると共にテープキャリアの
一方の側より半導体素子を接続している。こうしてテー
プキャリア自体を回路用基板としてそのまま用いるよう
にしている。
(Function) According to the present invention having such characteristics, a metal conductor is formed as a connection pattern without forming a device hole or a pattern cutting hole even at a position where a semiconductor element is attached to a tape carrier. A joining metal protrusion is formed at the end of the metal conductor, and a semiconductor element is connected from one side of the tape carrier. In this way, the tape carrier itself can be used as a circuit board.

(発明の効果) そのため本発明によれば、テープキャリアにホールを設
けないのでテープキャリアに金属導体が確実に固定され
ており、実装時に導体が変形する恐れがなくなる。従っ
てテープキャリア上に多数の半導体素子を高密度実装す
ることができる。又その場合にも高い信顧性を有する半
導体装置とすることができる。
(Effects of the Invention) Therefore, according to the present invention, since no holes are provided in the tape carrier, the metal conductor is securely fixed to the tape carrier, and there is no possibility that the conductor will be deformed during mounting. Therefore, a large number of semiconductor elements can be mounted on the tape carrier with high density. Also in that case, it is possible to provide a semiconductor device with high reliability.

〔実施例の説明〕[Explanation of Examples]

第1図は本発明の一実施例による半導体装置の製造工程
を示す図である。まず第1図(a)に示すように周辺に
スプロケットホールを有するテープキャリア11の上面
に従来と同様に金属導体12を構成する。この金属導体
12はテープキャリア11自体を回路基板として用いる
ことができるように複数の半導体素子相互を接続する回
路パターンを同時に形成しておくものとする。そしてそ
の後金属導体12の端部の半導体素子が取付けられる位
置に金属製の突起を形成する。これは第1図(b)に示
すように金属突起形成用基板13上にレジスト14を設
け、その上部の所定位置にあらかじめ金属突起15を取
付ける。そしてテープキャリア11の金属導体12の端
部に第1図(C)に示すように超音波接合を行う、超音
波接合は金属突起形成用基板13の上部の金属突起15
を金属導体12の端部に接続し、押さえブロック16を
用いて圧力を加えると共に超音波接続用ヒータ17を用
いて加熱し、超音波を加えることによって行うものとす
る。こうして金属パターンの端部に金属突起15を有す
るテープキャリア11を構成し、第1図(d)に示すよ
うに同一の面に更に半導体素子18を取付ける。半導体
素子18の取付時にも同様にして超音波接続用ヒータ1
7を用いてチップを加圧、加熱しながら超音波を付加し
低温で接合を行うものとする。
FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), a metal conductor 12 is formed on the upper surface of a tape carrier 11 having sprocket holes around its periphery in the same manner as in the prior art. A circuit pattern for connecting a plurality of semiconductor elements to each other is simultaneously formed on the metal conductor 12 so that the tape carrier 11 itself can be used as a circuit board. Then, a metal protrusion is formed at the end of the metal conductor 12 at a position where the semiconductor element is to be attached. As shown in FIG. 1(b), a resist 14 is provided on a substrate 13 for forming metal protrusions, and a metal protrusion 15 is attached in advance at a predetermined position on the resist 14. Then, ultrasonic bonding is performed on the ends of the metal conductors 12 of the tape carrier 11 as shown in FIG. 1(C).
is connected to the end of the metal conductor 12, pressure is applied using the holding block 16, heating is performed using the ultrasonic connection heater 17, and ultrasonic waves are applied. In this way, a tape carrier 11 having metal protrusions 15 at the ends of the metal pattern is constructed, and a semiconductor element 18 is further attached to the same surface as shown in FIG. 1(d). When attaching the semiconductor element 18, the ultrasonic connection heater 1 is
Bonding is performed at a low temperature by applying ultrasonic waves while pressurizing and heating the chips using a microprocessor.

こうすればテープキャリア自体にはデバイスホールを設
けないので金属導体12がテープキャリア11に確実に
保持される。従って第2図及び第3図に示すようにテー
プキャリア11上に多数の半導体素子18を高密度で実
装することができる。
In this way, since no device hole is provided in the tape carrier itself, the metal conductor 12 is securely held on the tape carrier 11. Therefore, as shown in FIGS. 2 and 3, a large number of semiconductor elements 18 can be mounted on the tape carrier 11 at high density.

又半導体素子を取付ける部分にも金属導体を貫通させて
形成することが可能となり、・パターン設計の自由度を
増すことができる。
Furthermore, it becomes possible to form a metal conductor through the part where the semiconductor element is to be attached, and the degree of freedom in pattern design can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による半導体素子の実装方法
を示す工程図、第2図はテープキャリア上に構成された
半導体素子の一例を示す図、第3図はその断面図、第4
図は従来のテープキャリアの−例を示す図、第5図はそ
のテープキャリア上に半導体素子を実装する際の状態を
示す図である。 11−・−テープキャリア  12−−−−−−一金属
導体15・・−−一−−金属突起  18−−−−一半
導体素子゛特許出願人   立石電機株式会社 代理人 弁理士 岡本宜喜(他1名) 第1図 11−・・−一−テーア鳩り7 12・−・−企λ4猟 15・−・−会&!!Z 18・−−−−−+4 イA(拳子 第2図 第4図 f口 第5図
FIG. 1 is a process diagram showing a method for mounting a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a semiconductor device configured on a tape carrier, FIG. 3 is a cross-sectional view thereof, and FIG.
This figure shows an example of a conventional tape carrier, and FIG. 5 shows a state in which a semiconductor element is mounted on the tape carrier. 11--Tape carrier 12--Metal conductor 15--Metal protrusion 18---Semiconductor element Patent applicant Tateishi Electric Co., Ltd. agent Patent attorney Yoshiki Okamoto ( 1 other person) Figure 1 11-...-1-Thea Pigeon 7 12...-Plan λ4 Hunting 15...-Kai &! ! Z 18・----+4 A (Fist figure 2 figure 4 figure f mouth figure 5

Claims (1)

【特許請求の範囲】[Claims] (1)テープキャリア上に金属導体による回路パターン
を形成する工程と、 前記テープキャリア上の金属導体の端部に金属突起を形
成する工程と、 前記テープキャリアの金属導体側より半導体素子の電極
端子を前記金属突起に接続する工程と、を有し、テープ
キャリアを用いて半導体素子を実装することを特徴とす
る半導体素子の実装方法。
(1) A step of forming a circuit pattern using a metal conductor on the tape carrier, a step of forming a metal protrusion at the end of the metal conductor on the tape carrier, and an electrode terminal of the semiconductor element from the metal conductor side of the tape carrier. A method for mounting a semiconductor device, comprising: connecting a semiconductor device to the metal protrusion, and mounting the semiconductor device using a tape carrier.
JP11929887A 1987-05-15 1987-05-15 Method for packaging semiconductor element Pending JPS63283139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11929887A JPS63283139A (en) 1987-05-15 1987-05-15 Method for packaging semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11929887A JPS63283139A (en) 1987-05-15 1987-05-15 Method for packaging semiconductor element

Publications (1)

Publication Number Publication Date
JPS63283139A true JPS63283139A (en) 1988-11-21

Family

ID=14757953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11929887A Pending JPS63283139A (en) 1987-05-15 1987-05-15 Method for packaging semiconductor element

Country Status (1)

Country Link
JP (1) JPS63283139A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264598A (en) * 1995-03-22 1996-10-11 Nec Corp Apparatus and method for bonding flexible film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264598A (en) * 1995-03-22 1996-10-11 Nec Corp Apparatus and method for bonding flexible film

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