JPS63280518A - Output circuit - Google Patents

Abstract

PURPOSE:To obtain a multi-value output by providing 1st and 2nd output terminals, outputting a voltage signal of a desired level to each of the output terminals through the use of a control signal and obtaining an output from the potential difference between the 1st and 2nd output terminals. CONSTITUTION:The 1st and 2nd output terminals Y1, Y2 are provided and a voltage signal of a desired level is outputted to each of the output terminals Y1, Y2 by using control signals X+, X0, X- to obtain an output from the potential difference between the 1st and 2nd output terminals Y1, Y2. Since the combination of voltage signals outputted to the 1st and 2nd output terminals Y1, Y2 is changed in three ways by output circuit control signals X+, X0, X-, a ternary output is obtained depending on the potential difference between the output terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit of a semiconductor integrated circuit.

[Conventional technology]

FIG. 4 is a circuit diagram showing a conventional output circuit. In the figure, 1 is a P-channel transistor (hereinafter referred to as P-ch Tr).
2 is an N-channel transistor (hereinafter referred to as N-ch
Tr), 1) is the input to the gate of the transistor, and 01 is the output.

Next, the operation will be explained.

When input ■1 is “high”, P-ch Tr 1 is off,
N-ch Tr 2 is turned on, "low" is output to output 01, and when input 1) is "low",
P-ch Tr 1 is turned on, N-ch Tr 2 is turned off, and "high" is output to output 01.

[Problem that the invention seeks to solve]

Since the conventional output circuit is configured as described above, 3
There was a problem in that it was impossible to obtain an output greater than the value.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an output circuit that can obtain an output of three or more values.

[Means for solving problems]

The output circuit according to the present invention includes the first. A second output terminal is provided, a voltage signal of a desired level is outputted to each of the output terminals by a control signal, and an output is obtained from the potential difference between the first and second output terminals.

[Effect]

In this invention, voltage signals of desired levels are outputted to the first and second output terminals according to the control signal, so that a multivalued output can be obtained from the outputs.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention, in which PI and P2 are P-channel transistors (hereinafter referred to as p-Ch Tr), Nl, N
2 is an N-channel transistor (hereinafter referred to as N-ch Tr), Gl and G3 are NOT logic gates, G2. G4
is an OR logic gate, X,,Xo.

X- is an output circuit control signal specifying output of positive, zero, and negative values, respectively; Yl and Y2 are first . This is the second output terminal.

Next, the operation will be explained.

When X, -1 (at this time, X, , X- are "O"), P-ch T
Only r (P 1 ) and N-ah Tr (N 2 ) are turned on, and P-ch Tr (P 2 ) and N-ch Tr (
N 1 ) is turned off.

Therefore, the first output terminal Yl has a positive potential with respect to the second output terminal Y2, and "positive" is output.

Similarly, when Xo=1 (at this time, X and X- are "0"), N-ah Tr(N 1 ), (N
2) is turned on, and the potential difference between output terminals Y1 and Y2 is “
0", 1 zero" is output, and when X-=1 (at this time, Xya, xo is 0"), P-chTr
(P2) and the N-ch Tr (N 1 ) are turned on, the output terminal Yl has a negative potential with respect to Y2, and "negative" is output.

In this way, in the circuit of this embodiment, the output circuit control signals X, ,
According to XO,l, 1st. Since the combination of voltage signals output to the second output terminals Y, , Yt changes in three ways, a three-value output can be obtained by the potential difference between the output terminals.

FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the present invention, which can obtain a five-value output. In the figure, P3. P4, P5. P6 is P-
chTr, N3. N4 is N-ch Tr, G
5. G8 is a NOT logic gate, G6. G9 is a NOR logic gate, G7. GIO is an OR logic gate, X,,X.

, , X-, X-, and Xo are each positive 1. Positive 2 (positive 1 + positive 2), negative 1. negative 2 (1 negative 1) 1 <1 negative 21), an output circuit control signal specifying the output of zero value, Yl and Y2 are the first . This is the second output terminal. Figure 3 shows the part surrounded by the dotted line in Figure 2, where all the transistors are connected to the resistor RP3.
゜RP4. RP5. RP6. RN3. RNA and switch SP3. SP4. SP5. SP6. SN3° and SN4 are shown in place, and RL is the first. This is a load resistance connected between the second output terminals Yl and Y2.

In the output circuit having such a configuration, the output circuit control signals X, as in the first embodiment described above. ,X. .

X, , X-, X-- through the logic gates to switch SP3. SP4. SP5. SP6. SN3°3N4 is controlled, and the first. Second output terminal Yl.

Since there are five combinations of voltage signals output to Y2, five-value outputs can be obtained from the current flowing through RL.

Note that in the above embodiments, three-valued and five-valued outputs were shown, but the first. If the second output terminals are not output when they are at the same potential, it is possible to obtain outputs of not only four values but also six or more values. As a result, in particular, AMI in the telecommunications field
, 2BIQ, and other ternary or quaternary codes can be easily obtained.

Further, in the above embodiment, P-ch Tr, N-ch
Both Tr were used, but only N-ch Tr,
Alternatively, only P-chTr may be used, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the output circuit of the present invention, the first. A second output terminal is provided, and a voltage signal of a desired level is outputted to each of the output terminals according to a control signal, and a voltage signal of a desired level is output to each of the output terminals. Second
Since the output is obtained from the potential difference between the output terminals of
This has the effect of allowing multivalued output to be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the invention, FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the invention, and FIG. 3 is a circuit diagram showing an output circuit according to a second embodiment of the invention. A circuit diagram for explaining the circuit, FIG. 4 is a circuit diagram showing a conventional output circuit. In the figure, P1 to P6 are P channel transistors, N
1 to N4 are N-channel transistors, G1, G3 . G5
．． G8 is a NOT logic gate, G2°G4. G7.010
is an OR logic gate, G6. G9 is a NOR logic gate, x
,,,x,,x,,x−. X- is the output circuit control signal, Yl and Y2 are the first .
This is the second output terminal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) first and second voltage signal generating means each generating a voltage signal of a desired level among a plurality of levels according to an external control signal and outputting it to the first and second output terminals; and a multi-value output circuit that obtains a desired multi-value output from the output of the second output terminal. (2) Each of the above voltage signal generation means has an N whose drain is connected to the output terminal and whose source is grounded.
A channel transistor, a P-channel transistor whose drain is connected to an output terminal and whose source is connected to a power supply, and a zero value of a 3-bit control signal for specifying multi-value output, and a negative or positive value. an OR circuit that takes the value as an input and applies its output to the gate of the N-channel transistor; and an OR circuit that takes the positive or negative value of the 3-bit control signal as an input and applies its output to the gate of the P-channel transistor. and an inverter applied to the gate, and outputs voltage signals of two levels to each output terminal to obtain a three-value output from the multi-value output circuit. Output circuit as described. (3) Each of the above voltage signal generation means has an N whose drain is connected to the output terminal and whose source is grounded.
A channel transistor, n P-channel transistors (n is an integer of 2 or more) each with its source connected to a power supply and its drain connected to an output terminal, and a (2n+1)-bit control signal for specifying multi-value output. an OR circuit that receives the zero value and all negative values, or the zero value and all positive values, and applies its output to the gate of the N-channel transistor; and the (2n+1) bits. a NOR circuit that inputs all positive values or all negative values of the control signals and applies the output to the gate of the first stage P-channel transistor; and the (2n+1) bit control signal. Input the n-th positive value or the n-th negative value, respectively,
and an inverter that applies the output to the gates of the P-channel transistors in the second and subsequent stages, and outputs voltage signals of (n+1) levels to each output terminal,
2. The output circuit according to claim 1, wherein the multi-value output circuit obtains an output of (2n+1) or 2n values.