JPS63280448A - Semiconductor device and resistance trimming thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device in which a resistance value can be adjusted after a resistor is manufactured by forming in advance connecting electrodes to divide a resistance layer formed on a semiconductor substrate, and short-circuiting the resistance layer between the electrodes to alter the sum of the resistance values to control it. CONSTITUTION:Whole resistance of a resistance layer 2 between contact holes 7a, 7b at both ends of the layer 2 is measured, and when the resistance value is larger than a designed resistance value, a set of contact holes 6a, 6b, 6c of connecting electrodes 4a, 4b, 4c and contact holes 7a, 7b to be short-circuited at both ends of the layer 2 are selected. Then, when total resistance value added with partial resistance layers 2a, 2c coincides with an object resistance value, conductive materials are deposited on partial resistance layers 2b, 2d to form an upper wiring layer 8. The layer 8 on the layer 2b is short-circuited by the deposition, and the layer 8 on the layer 2d short-circuits the layer 2d by invading into the holes 6c, 7b. Accordingly, the total resistance of the layer 2 becomes the resistance value added with those of the layers 2a, 2c to become the same as the object resistance value.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can adjust the resistance value of a resistor patterned on a semiconductor substrate, and trimming of the resistor. Regarding the law.

[Conventional technology]

When forming a resistor in an integrated circuit on a semiconductor substrate, it is necessary to control the resistance value to a desired resistance value. Therefore, when forming this resistor by ion implantation, the conductivity of the resistive layer is controlled by adjusting the amount of ions implanted or the acceleration energy of the ions.

In addition, when forming a resistance using the thermal diffusion method, the diffusion temperature,
The conductivity of the resistive layer is controlled by adjusting the diffusion time.

[Problem that the invention seeks to solve]

However, with such resistance value control, it may not be possible to obtain the desired resistance value due to variations in ion implantation or thermal diffusion conditions. On the other hand, at the design stage of a semiconductor device, the element such as a transistor to which a resistor is connected has already been determined, and if the desired resistance value is not 1q, the function of the element will be impaired, so it will be treated as a defective product. be exposed. Therefore,
If the desired resistance value cannot be obtained, it is preferable that the resistance value can be adjusted. In particular, resistance division type A/
This requirement is strong when using a device with strict resistance conditions, such as a D converter, or a manufacturing method that makes it difficult to strictly control manufacturing process conditions.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device in which the resistance value can be adjusted after manufacturing the resistor, and a method for trimming the resistor.

[Means for solving problems]

In the present invention, connection electrodes are formed in advance to divide a resistance layer formed on a semiconductor substrate, and the resistance layer between the connection electrodes is short-circuited to change the total resistance value and control the resistance value. This is what I decided to do.

Therefore, in the semiconductor device according to the present invention, a plurality of connection electrodes are formed at predetermined intervals in the length direction of the resistance layer formed on the semiconductor substrate so that both ends are connected to the lower wiring layer, Connection electrodes are selected through contact holes opened in the insulating layer on each connection electrode so that the sum of the resistance values of the resistance layers becomes the desired resistance value, and these are interconnected with the upper wiring layer. It is characterized by

Further, in the resistance trimming method according to the present invention, a resistance layer connected to a lower wiring layer is formed on a semiconductor substrate, a plurality of connection electrodes are formed at predetermined intervals on the resistance layer, and an insulating layer on the connection electrodes is formed. After forming a contact hole by etching and forming a photoresist film, a photoresist film is formed between the contact holes of the connection electrodes selected so that the sum of the resistance values of the resistance layer between the connection electrodes becomes the desired resistance value. The present invention is structured as described above, in which patterning is performed by step-feeding a predetermined mask and exposure, and an upper wiring layer is formed thereon to short-circuit between connection electrodes. Therefore, the contact hole makes it possible to short-circuit the resistance layer between the connection electrodes, and the upper wiring layer formed between the contact holes acts so that the total resistance value of the resistance layer becomes a target resistance value.

〔Example〕

Hereinafter, some embodiments of the present invention will be described with reference to the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

FIG. 1 shows the main parts of a semiconductor device according to an embodiment of the present invention, FIG. 1(a) is a plan view before resistance value adjustment, and FIG.
) is a plan view of the adjustment bond, and (C) is a cross-sectional view taken along the line A-A. As shown in the figure, a resistive layer 2 having a constant cross-sectional area and a predetermined length is formed on a semiconductor substrate 1.

The resistive layer 2 is patterned through a mask by means such as ion implantation or thermal diffusion. A lower wiring layer 3 is formed at both ends of the resistive layer 2 to connect the resistive layer 2 to each element (not shown) patterned on the semiconductor substrate 1 .

Further, the upper body of the resistance layer 2 is provided with connection electrodes 4a at predetermined intervals.

4b and 4G are formed. Connection electrode 4a.

4b and 4c can be formed simultaneously with the formation of the lower wiring layer 3, but both need to be in ohmic contact with the resistance layer 2. These connection electrodes 4a, 4b,
The resistance between the electrodes of the resistance layer 2 on which 4G is formed is proportional to its length.

Furthermore, an insulating layer 5 is deposited on the semiconductor substrate 1, insulating the connection electrodes 4a, 4b, 4c from each other.

The insulating layer 5 is made of silicon dioxide (Si 02 ) or the like, and is deposited to cover the entire surface of the semiconductor substrate 1 . Then, after the deposition, the connection electrode 4a is formed.

Insulating layer 5 on 4b, 4'C is removed by etching, and contact holes 6a, 6b, 6G are opened.

In this case, a contact hole 7a is also formed in the insulating layer 5 at the overlapping portion of the resistance layer 2 and the lower wiring layer 3.

7b will be opened at the same time. Which contact hole 6
a, 6b, 6c and 7a, 7b are also formed to short-circuit a part of the resistance layer 2.

Next, the procedure for adjusting the resistance value will be explained.

First, the overall resistance of the resistive layer 2 between the contact holes 7a and 7b at both ends of the resistive layer 2 formed as described above is measured. If the measured resistance value is larger than the designed resistance value (that is, the target resistance value), each connection electrode 4a, 4b.

A set of contact holes 6a, 6b, 6c of 4C and contact holes 7a, 7b at both ends of the resistance layer 2 to be short-circuited is selected.

Here, the partial resistance layer 2a between the contact holes,
The resistance values of 2b, 2c, and 2d can be estimated from their lengths and the overall resistance value.

This is because the cross-sectional area of each part of the resistance layer 2 is almost the same, so the ratio of the overall resistance value of the resistance layer 2 to the partial resistance value of each of the partial resistance layers 2a to 2d matches the ratio of their lengths. It is from.

Therefore, for example, when the total resistance value including the partial resistance layers 2a and 2G matches the target resistance value, gold is applied onto the partial resistance layers 2b and 2d through a photoresist film patterned with a predetermined mask. An upper wiring layer 8 is formed by depositing a conductive material such as aluminum. Due to this deposition, the upper wiring layer 8 on the partial resistance layer 2b is formed into contact holes 6a, 6.
The upper wiring layer 8 on the partial resistance layer 2d also penetrates into the contact holes 6C and 7b to short-circuit the partial resistance layer 2d. Therefore, the total resistance of the resistance layer 2 is the resistance value of the partial resistance layers 2a and 2C, which is the same as the target resistance value.

Next, a resistor trimming process according to an embodiment of the present invention will be explained based on FIG. 2.

FIG. 2(a) shows a plan view of the semiconductor device, and FIG. 2(b) shows a plan view of the semiconductor device.
and (C) shows a sectional view taken along line B-B. This example shows a method of forming an upper wiring layer when the partial resistance layers 2b and 2d have different lengths. Well, the same figure (
a>, a resistance layer 2 is formed on a semiconductor substrate 1 by ion implantation or the like, and a lower wiring layer 3 and connection electrodes 4a to 4C are formed thereon. It should be noted that these lower wiring layers and connection electrodes 4a to 4C are subjected to high concentration ion implantation or the like so as to come into ohmic contact with the resistance layer 2.

Next, as shown in FIG. 2(b), an insulating layer 5 made of silicon dioxide or the like is deposited on the upper surface. This insulating layer 5 can be deposited by, for example, the CVD method. Thereafter, a photoresist film (not shown) or the like is deposited and patterned, and the insulating layer 5 in the opening is removed by etching, thereby forming a contact hole as shown in FIG.

Next, after removing the above photoresist film by etching, a photoresist film 9 is again formed on the entire surface, and as shown in FIG.
In C), areas indicated by symbols E1 to E3 are exposed. here,
Regions E'1 to E3 are each exposed using the same mask, and region E2. For E3, multiple exposure is performed by stepping the mask. After that, when the photoresist film 9 is etched, the exposed portion is removed, so if gold (AU), aluminum (AI), etc. are further deposited on it and the photoresist film 9 is etched, the upper wiring is removed by lift-off. @8 is formed as shown in FIG. 1(C). Thereby, short-circuiting of the elongated partial resistance layer 2b can also be performed using a single mask.

Note that in the above manufacturing process, exposure is performed by stepping a single mask, but it goes without saying that masks of different sizes may be used.

Next, an embodiment of the present invention will be specifically described using numerical values with reference to FIG.

FIG. 5A is a plan view of the main parts of a semiconductor device for this purpose, and FIG. 1B is an equivalent circuit diagram thereof.

Connection electrodes 10a, 10b, 10c, and 10d are formed at intervals of J/10 on the resistance layer 2 having an overall length of 1, and each connection electrode 10a, 10b, 10c.

Contact holes 12a and 12b are provided on 10d.

12c and 12d are formed. Therefore, connection electrode 1
Partial resistance layers 11a, 11b divided by 0a to 10d,
The resistance value of 11c is R/1 with respect to the total resistance R of the resistance layer 2.
It is 0.

In this embodiment, for example, if the design resistance value is 1.0Ω, but the total resistance of the manufactured resistive layer 2 is 1.2Ω, two parts of the partial resistance layer are short-circuited. By doing this, the desired resistance value can be adjusted. That is,
Since the effective length of the resistance layer becomes 475p due to the short circuit between the two parts of the partial resistance layer, the resistance value becomes 1.2ΩX415=0.96Ω, which is almost the same as the target resistance value. In this case, the adjacent partial resistance layer 11a.

Short circuiting is possible by shifting the photomask 1710 steps on the photomask 11b and exposing the photomask.

Note that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways.

For example, the number of adjustment resistors may be any number.

Furthermore, the upper and lower wiring layers may be made of any conductive material. Roughly, Figures 2 and 3
What is shown in the figure can be easily realized by changing the mask in the manufacturing process described above.

〔Effect of the invention〕

As explained in detail above, the present invention forms connection electrodes and contact holes that short-circuit the resistance layer at predetermined intervals,
When the resistance value of the resistance layer deviates from the desired resistance value, the part of the resistance layer with the excess resistance value is short-circuited, making it possible to adjust the resistance value, which has the effect of suppressing the occurrence of defective products. .

[Brief explanation of drawings]

1 is a plan view and a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view and a sectional view of a semiconductor device for explaining the manufacturing process according to an embodiment, and FIG. 2 is a plan view of the device and its equivalent circuit diagram for specifically explaining an example using numerical values. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Resistance layer, 3... Lower wiring layer, 4a, 4b, 4c, 10a, 10b, 10c. 10d... Connection electrode, 5... Insulating layer, 6a, 6b. 6c, 6d, 7a, 12a, 12b, 12c. 12d... Contact hole, 8, 9... Upper wiring layer.

Claims (1)

[Claims] 1. A semiconductor substrate, a resistive layer patterned on the semiconductor substrate, a lower wiring layer formed on the semiconductor substrate in ohmic contact with both ends of the resistive layer, and the resistive layer. a plurality of connection electrodes formed in ohmic contact with the resistance layer at predetermined intervals in the length direction; an insulating layer formed on the semiconductor substrate including the resistance layer, a lower wiring layer, and the connection electrode; At least one pair of the connection electrodes or the contact hole formed in the insulating layer on each of the connection electrodes and the connection electrode selected such that the sum of the resistance values between the lower wiring layer becomes a target resistance value. A semiconductor device comprising a connection electrode and an upper wiring layer that interconnects the lower wiring layer. 2. The semiconductor device according to claim 1, wherein the lower wiring layer is formed on the semiconductor substrate with an insulating film interposed therebetween. 3. The semiconductor device according to claim 1 or 2, wherein the contact hole is also formed in the insulating layer on a contact portion between the resistive layer and the lower wiring layer. 4. A first step of patterning a resistive layer on a semiconductor substrate, forming a lower wiring layer that makes ohmic contact with both ends of the resistive layer, and forming a plurality of connection electrodes at predetermined intervals on the resistive layer. a second step; a third step of forming an insulating layer on the semiconductor substrate including the resistive layer, a lower wiring layer, and a connection electrode; and etching the insulating layer on at least the connection electrode to form a contact hole. a fourth step of forming a photoresist film on the insulating layer and the contact hole; and a fifth step of forming a photoresist film on the insulating layer and the contact hole; a sixth step of selecting contact holes and exposing and patterning the photoresist film between the selected connection electrode contact holes by stepping a predetermined mask; a seventh step of forming an upper wiring layer between the contact holes. 5. The fourth step includes etching the insulating layer on the contact portion between the resistance layer and the lower wiring layer to form a contact hole, and the sixth step includes etching the insulating layer on the contact portion between the connection electrode and the lower wiring layer. 5. The method for trimming resistance of a semiconductor device according to claim 4, further comprising the step of exposing the photoresist film between the contact holes.