JP3191712B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
Particularly those compounds resistance of low resistance on the semiconductor substrate is a semiconductor device which is formed and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, four methods have been known as the configuration of a resistor in a compound semiconductor device. The first configuration example is of an ion implantation as shown in FIG.
This is because, for example, the gallium arsenide (GaAs) substrate 9 has S
This is a method of forming a resistive layer 10 by implanting i ions. The resistive layer is formed by implanting Si ions at an acceleration voltage of about 100 keV and at a dose of about 0.5 to 3.0 × 10 ⁻¹³ (cm ⁻² ), followed by GaAs. It is formed by annealing the substrate 9 at a temperature of about 800.degree. In FIG. 1, reference numeral 11 denotes a resist pattern for forming the resistance layer 10.

A second configuration example uses a thin film resistor as shown in FIG. In the case where the thin film resistor 14 is used as the resistor, as a material forming the thin film resistor 14, for example, nickel chromium (Ni-Cr), tungsten silicon nitride (WSiN), or the like is used. In FIG. 1, reference numerals 12 and 13 denote SiO ₂ films, and reference numeral 15 denotes a metal wiring layer electrically connected to the thin film resistor.

A third configuration example is disclosed in Japanese Patent Application Laid-Open No. 8-125123.
In this publication, a part of a wiring is alloyed by using a laser beam as shown in FIG.
This uses a metal wiring 16 having a layered structure of Ti and Au such as Ti / Au, Ti / Au / Ti as a wiring,
A predetermined region of the metal wiring 16 is locally irradiated with a laser beam and is subjected to a heat treatment at about 450 ° C. to form a TiAu alloy wiring 17.
To form At this time, since the wiring resistivity of the TiAu alloy wiring 17 is higher than that of the metal wiring 16 that has not been heat-treated, this is used as a resistance layer.

A fourth configuration example uses a TiAu alloy wiring as a part of a metal wiring as shown in FIG. This is because the metal wiring 1 does not have a two-layer structure of Ti / Au.
8, a break is formed, and the break of Ti / Au is formed in the break.
A metal wiring having a layer structure is formed, and the entire semiconductor substrate is heat-treated to form a TiAu alloy wiring 19. At this time,
The resistivity of the TiAu alloy wiring 19 is set to be higher than that of the metal wiring 18 not having the two-layer structure of Ti / Au.
This is used as a resistance wiring.

[0006]

In the above-mentioned conventional configuration examples, the following problems occur. That is, the first problem is that, as shown in FIG. 4, when the resistance layer 10 is formed by ion implantation, the resistance layer 10 having several ohms to several tens of ohms has a large variation in resistance value and poor reproducibility. That is. The reason is that when forming the low resistance layer on the GaAs substrate 9, a large amount of impurities must be implanted with ions, so that stable activation of the impurities is not performed during annealing.

The second problem is that when the thin film resistor 14 is used as a resistor as shown in FIG. 5, or when a part of the wiring is alloyed by using a laser beam as shown in FIG. This means that the manufacturing cost increases. The reason is that when the thin film resistor 14 is used as the resistor, the thin film resistor 14
This is because, in general, the melting point is high, so that a dedicated evaporation apparatus or sputtering apparatus for forming the thin film resistor 14 must be newly introduced. Also, when a part of the wiring is alloyed by using a laser beam, a part of the wiring must be heat-treated in a range of several microns square, so that a dedicated laser device must be newly introduced.

A third problem is that the resistance layer 10 is formed by ion implantation as shown in FIG. 4 or the thin film resistor 14 is used as a resistor as shown in FIG. That is, a large area may be required. The reason is that the even resistor formed by either method is for requiring area as resistive portion, also connecting the resistive portion and the wiring portion be provided with contact portions (contacts) This is because a dimensional margin must be expected in the contact portion at the time of design, and an extra area is required in the resistance portion.

A fourth problem is that when the resistance layer 10 is formed by ion implantation as shown in FIG. 4 or when the thin film resistor 14 is used as a resistor as shown in FIG. Is difficult to change. The reason is that since the resistance layer 10 and the thin film resistor 14 are formed in a step before the formation of the wiring, when the resistance value is changed, the layout must be changed in the subsequent steps.

A fifth problem is that the conventional low resistance forming technique is not excellent in mass productivity as shown in FIGS. The reason is, Fig. 4, a low resistance formation technique shown in FIGS. 5 and 7, the portion to form the resistor, i.e. 4 in resistance <br/> layer 10, FIG. 5 in the thin film resistor 14, 7 Alloy Wiring 1
This is because the process reliability and the process yield are reduced because 9 is formed separately from the wiring having no resistance. Also, as shown in FIG. 6, when a part of the wiring is alloyed with laser light, the processing time increases in proportion to the increase in the heat treatment area and the place where the heat treatment is performed.

An object of the present invention is to solve these first to fifth problems at once, and to provide a compound semiconductor device having a resistance of several ohms.
An object of the present invention is to provide a semiconductor device capable of easily changing a resistance value of a resistance of several tens of ohms in a small area with good reproducibility, and a method of manufacturing the same.

[0012]

Means for solving the problems of the present invention are as follows.

According to the present invention, a step of forming a low-resistance conductor layer directly on a semiconductor substrate or through an insulating film, a step of forming a first mask having a required pattern on the low-resistance conductor layer, Forming a metal wiring layer following the shape of the mask on the low-resistance conductor layer by metal plating using a first mask; and forming a second metal wiring layer in a region including a separation portion of the formed metal wiring layer. A method for manufacturing a semiconductor device, comprising: forming a mask; and etching the low-resistance conductor layer using the metal wiring layer and a second mask.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
1A is a plan view, and FIG. 1B is a cross-sectional view. As the substrate 1, a semi-insulating substrate such as GaAs, AIGaAs, or InP is used. An insulating film 2 such as SiN or SiO ₂ is formed on the semi-insulating substrate 1.
Is formed. Note that the insulating film 2 may not be provided. Then, conductor layers 3 and 4 are formed on the insulating film 2.
The conductor layer 3 is formed as a low-resistance layer in an elongated plane shape having a required width dimension in which an intermediate portion in the length direction is formed wide.
i, a single-layer metal such as TiN, Ti-Pt, Ti-
It is formed of a laminated metal such as Au and a metal having a resistivity required as a low resistance layer. The conductor layer 4 is formed as a metal wiring layer having an elongated flat shape having the same width as the conductor layer 3, and a highly conductive metal having a low resistivity such as Au, Ag or Cu is formed by plating. An intermediate portion corresponding to a wide intermediate portion of the conductive layer 3 is removed from the conductive layer 4 to form a separated portion 5, and a low resistance is formed in the separated portion 5 by the conductive layer 3. Have been.

Next, a method of manufacturing the resistor shown in FIG. 1 will be described with reference to FIGS. First, FIG.
As shown in (a), the semi-insulating substrate 1 is formed of a GaAs having a thickness of several hundreds μm by a crystal growth method such as an LEC method or a tilt method.
It is configured as a semi-insulating substrate such as s or InP, or a semi-insulating substrate obtained by growing InGaAs or AIGAAs or the like on the semi-insulating substrate by a crystal growth method such as an MBE method or a MOVPE method. Then, as an insulating film 2 on the semi-insulating substrate 1, an LPCVD method or a PCV
By using an insulating film forming technique such as the D method, SiO ₂ of an arbitrary thickness
An insulating film 2 such as a film or a SiN film is formed.

Next, as shown in FIG.
A single-layer metal such as Ti or Pt, or a multi-layer metal such as Ti / Pt or Ti / Pt / Ti, or AuGe, An alloying metal such as WSi is formed. Next, as shown in FIG. 2C, an organic insulating film 7 such as a photoresist or a polyimide is put on the conductor layer 3 by using a photoresist technique except a wiring forming portion.
Form a mask.

Next, as shown in FIG.
Is placed in an electrolytic bath, and Au plating is performed on the conductor layer 3 by a selective plating method using the organic insulating film 7 as a mask.
A plating film such as Ag plating or Cu plating is grown to several μm. After completion of the plating, the organic insulating film 7
Is removed. Thereby, the conductor layer 4 having portions separated from each other is formed according to the pattern shape of the organic insulating film 7. Next, as shown in FIG. 3B, an organic insulating film 8 such as a photoresist or polyimide is selectively put on the conductor layer 3 including the separated portions of the conductor layer 4 by using a photoresist technique. And FIG.
As shown in (c), the conductor layer 3 and the organic insulating film 8 are used as masks by dry etching such as milling or wet etching using an inorganic or organic solvent.
Is etched. Thereafter, the structure shown in FIG. 1 is completed by removing the organic insulating film 8.

According to this structure, since the low-resistance conductor layer 3 is formed by etching using a mask in order to form a low resistance, the processing accuracy of the metal is smaller than the control of the activation rate of ion implantation. Is easier, and the contact portions connecting the low- resistance region and the wiring are formed of the conductor layers 3 and 4.
Since there is no parasitic resistance in this portion, the resistance region can be formed with good reproducibility. Also, at this time, since it is not necessary to secure a contact connecting the resistance region and the wiring region as a region, it is not necessary to provide a contact and a dimensional margin, and it is possible to reduce the area of the low resistance region and thus the chip area. . Further, since the process for forming the contact can be simplified, the number of steps can be reduced, and the cause of process failure such as contact failure can be reduced, and the yield and mass productivity can be improved. Also, since the step of forming the low resistance can be shifted after the formation of the wiring, it is possible to manufacture before the formation of the low resistance in advance, and since the change of the photoresist mask for changing the resistance value is reduced, It is also possible to easily make a low resistance design change.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings. Referring again to FIG. 1, the semi-insulating substrate 1
Is a 100 μm thick GaAs substrate. The insulating film 2 on the semi-insulating substrate 1 is formed of an SiO ₂ film having a thickness of 2000 °. The conductor layer 3 on the insulating film 2 is made of Ti / Pt 2
Each layer is grown to a thickness of 1000 °. Conductor layer 4
Is formed of Au having a thickness of 3 μm.

As an embodiment of the manufacturing method, first,
Referring again to FIG. 2, the semi-insulating substrate 1 is a 100 μm thick GaAs substrate formed by the LEC method. On this semi-insulating substrate 1, an SiO ₂ film having a thickness of 2000 ° is formed as an insulating film 2 by LPCVD. Next, Ti / Pt is formed as the conductor layer 3 on the SiO ₂ film as the insulating film 2.
Is formed. As for the two-layer film of Ti / Pt, first, a Ti film of 1000 ° is formed by using a sputtering device, and then Pt is formed by 1000 ° by using the same sputtering device. Next, a resist film 7 is covered on the conductor layer 3 except for a wiring forming portion by using a photoresist technique.

Next, referring again to FIG. 3, Au plating is grown to a thickness of 3 μm using an electrolytic bath as the conductor layer 4, and the resist film is removed. Next, a resist film 8 is covered on the low resistance forming portion by using a photoresist technique. Next, using a milling apparatus, Au / plating and a resist film were used as masks to form Ti /
After removing the Pt film, the resist 8 is removed.

[0022]

As described above, according to the semiconductor device of the present invention and the method of manufacturing the same, the following effects can be obtained. The first effect is that the resistance region can be formed with good reproducibility. The reason is that, in the formation of low resistance , metal processing accuracy is easier than control of the activation rate of ion implantation. Also, because there is no contact portion connecting the low resistance region and the wiring, there is no parasitic resistance in this portion. The second effect is that when a low-resistance region is separately provided, the area of the low-resistance region and thus the chip area can be reduced. The reason is that there is no need to provide a contact that connects the contact connecting the low-resistance region and the wiring portion, and thus it is not necessary to provide a contact and a dimensional margin. A third effect is that a low resistance design change is facilitated. The reason is that the process of forming the low-resistance region can be shifted after the formation of the wiring, so that it is possible to manufacture before the formation of the low-resistance region in advance,
Also, the change of the photoresist mask caused by the change of the resistance value is reduced. The fourth effect is that the yield and mass productivity are improved. The reason for this is that the process for forming the low resistance can be simplified, and a contact for connecting the low resistance to the wiring is not required, so that the process can be shortened and the cause of process failure such as contact failure can be reduced. is there.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view of an embodiment of the present invention.

FIG. 2 is a perspective view showing the manufacturing method of FIG.
It is.

FIG. 3 is a perspective view showing the manufacturing method of FIG.
It is.

FIG. 4 is a cross-sectional view of a semiconductor having a first conventional configuration example.

FIG. 5 is a sectional view of a semiconductor having a second conventional configuration example.

FIG. 6 is a sectional view of a semiconductor having a third conventional configuration example.

FIG. 7 is a sectional view of a semiconductor having a third conventional configuration example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-insulating substrate 2 Insulating film 3 Conductive layer (low resistance layer) 4 Conductive layer (metal wiring) 5 Separation part 6 Low resistance 7,8 Organic insulating film

Claims (1)

(57) [Claims] A step of forming a low-resistance conductor layer directly on a semiconductor substrate or via an insulating film; a step of forming a first mask having a required pattern on the low-resistance conductor layer; Forming a metal wiring layer following the shape of the mask on the low-resistance conductor layer by a metal plating method using the mask described in (1), and applying a second mask to a region including a separated portion of the formed metal wiring layer. A method of manufacturing a semiconductor device, comprising: a step of forming; and a step of etching the low-resistance conductor layer using the metal wiring layer and a second mask.