JPS6328036A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6328036A JPS6328036A JP61172077A JP17207786A JPS6328036A JP S6328036 A JPS6328036 A JP S6328036A JP 61172077 A JP61172077 A JP 61172077A JP 17207786 A JP17207786 A JP 17207786A JP S6328036 A JPS6328036 A JP S6328036A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- chip
- semiconductor substrate
- etching
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims description 27
- 230000002950 deficient Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000001259 photo etching Methods 0.000 abstract description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 230000005856 abnormality Effects 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000000275 quality assurance Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.
従来の技術
従来の半導体装置の製造方法においては、ホトエツチン
グ工程を用いて酸化膜・窒化膜等の絶縁膜あるいは配線
金属膜等をパターニング加工し、各種のデバイスを一枚
の半導体基板上に大量に形成していた。Conventional technology In conventional semiconductor device manufacturing methods, insulating films such as oxide films and nitride films, or wiring metal films, etc., are patterned using a photoetching process, and various devices are mass-produced on a single semiconductor substrate. was forming.
発明が解決しようとする問題点
このような従来の製造方法では、ホトエツチング工程を
一枚の半導体基板上の多くのチップに実施しても、エツ
チング終了後得られたエツチングパターンを検査せず次
の工程に進めていたため、各エツチング工程の途中にダ
スト等の影響で発生したパターンくずれ不良があっても
、当該チップに対して次の工程を施して製造工程を進め
ていた。Problems to be Solved by the Invention In such conventional manufacturing methods, even if the photo-etching process is performed on many chips on one semiconductor substrate, the etched pattern obtained after the etching process is not inspected and the next etching process is performed. Because the process was progressing, even if there was a pattern distortion defect caused by dust or the like during each etching process, the next process was performed on the chip and the manufacturing process continued.
このため、不良チップについて余分の工程が加えられ、
さらに、得られた不良チップにも行なわれる検査工程の
損失、更には程度の軽い不良チップによって引き起こさ
れる市場不良を防止するために行なわれるバーイン工程
等の品質保障上の損失は非常に大きいものがある。For this reason, extra steps are added for defective chips.
Furthermore, the losses from the inspection process that is also performed on the resulting defective chips, and the losses from quality assurance such as the burn-in process that is performed to prevent market defects caused by mildly defective chips are extremely large. be.
本発明はかかる点に鑑みてなされたもので、製造工程の
途中でパターン照合工程を加えるこ七により、不良チッ
プを早い段階で除去する半導体装置の製造方法を提供す
ることを目的とするものである。The present invention has been made in view of the above, and an object of the present invention is to provide a method for manufacturing a semiconductor device that removes defective chips at an early stage by adding a pattern matching step in the middle of the manufacturing process. be.
問題点を解決するための手段
本発明は、ホトレジストをホトマスクパターンのステッ
プアンドリピート法でパターン検査グし、同ホトレジス
ト下の物質をエツチング処理する工程と、前記物質のエ
ツチング後のパターンを前記ホトマスクパターンと照合
し、前記物質のパターンのうちの不良パターンを記憶処
理する工程をそなえた半導体装置の製造方法である。Means for Solving the Problems The present invention includes the steps of pattern-inspecting a photoresist using a photomask pattern step-and-repeat method, etching the material under the photoresist, and converting the etched pattern of the material into the photomask pattern. This method of manufacturing a semiconductor device includes a step of checking the material pattern and storing a defective pattern among the material patterns.
作用
本発明によれば、ホトレジスト下の物質のエツチングパ
ターンが所望のホトマスクパターンがら著しく外れた形
状になっているものを、同物質のエツチング工程後に直
ちに認識して記憶し、以降の製造工程では、この不良パ
ターンのチップ部分にはホトレジスト工程を省略し、い
わゆる、飛び越し処理することで、工程の迅速化と不良
チップの早期排除が実現される。According to the present invention, if the etched pattern of the material under the photoresist is significantly different from the desired photomask pattern, it is immediately recognized and memorized after the material is etched, and in subsequent manufacturing steps, By omitting the photoresist process for the chip portion of this defective pattern and performing so-called skip processing, it is possible to speed up the process and eliminate defective chips at an early stage.
実施例
第1図の工程フローチャートに示すように、本発明の半
導体装置の製造方法はホトエツチング後に得られる半導
体基板上の各チップのパターンを元のホトマスクパター
ンと比較照合することにより、以降の工程を次々と決定
して進めるものである。パターン照合の例について第2
図を用いて説明する。第2図(a)は、元のホトマスク
パターンに比べてエツチング後得られたパターンの寸法
か細すぎる場合であり、所定の寸法値より細すぎるパタ
ーンを有するチップが半導体基板上にあるときには、こ
のチップへの以降の処理工程を省略する。Embodiment As shown in the process flowchart of FIG. 1, the method for manufacturing a semiconductor device of the present invention compares and verifies the pattern of each chip on the semiconductor substrate obtained after photoetching with the original photomask pattern, thereby controlling the subsequent steps. It is a matter of making decisions one after another and moving forward. Second example of pattern matching
This will be explained using figures. FIG. 2(a) shows a case where the dimension of the pattern obtained after etching is too small compared to the original photomask pattern, and when there is a chip on the semiconductor substrate with a pattern that is too thin than the predetermined dimension value, this The subsequent processing steps for the chip are omitted.
第2図(b)は、元のホトマスクパターンに比べてエツ
チング後、得られたパタ7ンの一部分が異常な形状の場
合であり、このようなチップでも、以降の処理工程を省
略する。FIG. 2(b) shows a case where a part of the pattern 7 obtained after etching has an abnormal shape compared to the original photomask pattern, and even in such a chip, the subsequent processing steps are omitted.
パターン照合の具体的な方法としては、チップの表面を
電子ビームで走査し、被エツチング材料と下地物質がこ
の反射ビームの相異をとらえてエツチングパターンの像
を検知する。このエツチングパターンの寸法と元のホト
マスクパターンの寸法とを数値的に比較し、チップ内で
一ケ所でも所定の差以内になければ、そのチップは不良
と判定する。そしてこの場合、不良チップのウェハ内座
標値を記憶させる。あるいは、当該不良チップの左上端
に数10ミクロン角のパッド状に不良チップを示すマー
クをビーム露光させるものとし、次工程より当該位置に
おいて差信号を検知したときは、次のチップにスキップ
する様にすれば、平面パターンに関しては、完全良品チ
ップのみウェハ上に作成されることになる。A specific method for pattern matching is to scan the surface of the chip with an electron beam, and detect the image of the etching pattern by detecting the difference between the reflected beams between the material to be etched and the underlying material. The dimensions of this etched pattern are numerically compared with the dimensions of the original photomask pattern, and if the difference is not within a predetermined value even at one location within the chip, the chip is determined to be defective. In this case, the intra-wafer coordinate values of the defective chip are stored. Alternatively, a mark indicating a defective chip in the form of a pad of several tens of microns square is exposed to the beam at the upper left end of the defective chip, and when a difference signal is detected at the position in the next process, the process skips to the next chip. If this is done, only completely non-defective chips will be created on the wafer regarding the planar pattern.
発明の効果
以上述べてきたように本発明によれば、半導体装置の製
造工程において、途中のホトエツチング工程の結果得ら
れたパターンに異常があれば異常のあったチップについ
ては以降の工程を省略することにより、半導体基板−枚
当たりに要する処理工程が短縮できる。第1図で、ホト
エツチング工程数が9工程(n=9)ある半導体装置の
製造方法の場合、従来例では全てのチップに9工程を実
施してきたが、本発明の場合では、不良チップにはこの
段階で同チップを記憶し、工程中止を指示し、次の工程
を実施しない。したがって、工程数がかなり減少する。Effects of the Invention As described above, according to the present invention, in the manufacturing process of a semiconductor device, if there is an abnormality in the pattern obtained as a result of an intermediate photoetching process, the subsequent process is omitted for the chip with the abnormality. As a result, the processing steps required per semiconductor substrate can be shortened. In FIG. 1, in the case of a semiconductor device manufacturing method with nine photoetching steps (n=9), in the conventional example, nine steps were performed on all chips, but in the case of the present invention, defective chips are At this stage, the same chip is memorized, the process is instructed to stop, and the next process is not performed. Therefore, the number of steps is considerably reduced.
更に、不良チップが途中で工程を中止されている場合に
は、すでに、この不良チップは、ステップアンドリピー
トに記憶されているから、検査工程でも同チップに対す
る検査過程を省略することができる。Furthermore, if the process for a defective chip is stopped midway, the defective chip has already been stored in the step-and-repeat system, so that the inspection process for the same chip can be omitted in the inspection process.
第1図は本発明の実施例における製造工程のフローチャ
ート、第2図(a) 、 (b)は本発明のパターン検
査における不良パターン形状例を示す。
代理人の氏名 弁理士 中尾敏男 ほか1名第2図
(久)
(b)FIG. 1 is a flowchart of the manufacturing process in an embodiment of the present invention, and FIGS. 2(a) and 2(b) show examples of defective pattern shapes in pattern inspection of the present invention. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2 (Hi) (b)
Claims (1)
リピート法でパターンニングし、同ホトレジスト下の物
質を湿式あるいは乾式エッチングする処理工程に加えて
、前記物質のエッチング後のパターンを前記ホトマスク
パターンと照合し、前記物質のうちの不良パターンを記
憶処理する工程をそなえた半導体装置の製造方法。In addition to patterning the photoresist using a step-and-repeat photomask pattern and wet or dry etching the material under the photoresist, the etched pattern of the material is compared with the photomask pattern, A method for manufacturing a semiconductor device, which includes a process for storing defective patterns.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61172077A JPS6328036A (en) | 1986-07-22 | 1986-07-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61172077A JPS6328036A (en) | 1986-07-22 | 1986-07-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6328036A true JPS6328036A (en) | 1988-02-05 |
Family
ID=15935110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61172077A Pending JPS6328036A (en) | 1986-07-22 | 1986-07-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6328036A (en) |
-
1986
- 1986-07-22 JP JP61172077A patent/JPS6328036A/en active Pending
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