JPH06181156A - Pattern verification in photolithography - Google Patents

Abstract

PURPOSE:To improve the reliability of a semiconductor product by providing a pattern verification method for detecting the defect of a resist pattern caused by the surface structure of a wafer. CONSTITUTION:In the title pattern verification method for detecting the defect of a resist pattern to be formed in the surface of a wafer 1 by photolithography, a plurality of simulation patterns, in which exposure is performed under different exposure conditions including exposure energy E and focal position F as factors, are formed in the resist of the wafer 1 surface and each of the plurality of simulation patterns is subjected to compare check so that the defect of the resist pattern is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern verification method for detecting pattern defects in a resist formed on a wafer surface in a photolithography process in semiconductor manufacturing.

[0002]

2. Description of the Related Art In photolithography, a reticle mask on which a pattern is formed is irradiated with exposure light to project the pattern on a photosensitive composition, and then development processing is performed to form the pattern on the photosensitive composition. To form. This photolithography is frequently used as a method for forming a pattern on a resist on a wafer surface in a semiconductor manufacturing process.

In the semiconductor manufacturing process, the same resist pattern is obtained by repeating the reticle mask using a stepper during exposure.
For example, when exposure is performed as described above using a reticle mask A, a repeated image of shot A is obtained on the wafer surface as shown in FIG. Since the resist pattern obtained as described above is used as a mask to perform fine processing such as etching on the wafer surface, the shape of the pattern formed on the resist requires high accuracy.

Therefore, verification of the formed pattern is indispensable, and pattern verification using a wafer inspection machine is performed. The wafer inspection machine detects the difference between the patterns by comparing the shapes of the patterns, and the verification of the pattern using the wafer inspection machine is performed as follows. First, the shapes of the patterns formed on the respective shots are compared by the wafer inspection machine, and the shots having the patterns of different shapes are found. Next, it is confirmed whether or not the dimension of the found irregular-shaped pattern, for example, the pattern is within the control limit. If it is within the control limit range, it is determined as a normal pattern, and if it exceeds the control limit range, it is determined as a defect pattern.

By the above method, a pattern defect generated in a specific shot due to, for example, adhesion of foreign matter to the wafer surface can be found.

[0006]

However, the above pattern verification method has the following problems. That is, the surface of the wafer to which the resist is applied is not always uniform, and the difference in material and the step structure occur due to the formation of the wiring pattern and the interlayer film. For this reason, for example, the shift of the focal point position is enlarged in the step portion, and the exposure energy is changed in the portion of different material due to the difference of the reflectance of the exposure light.

In photolithography, dimensional deviation and defects occur in a pattern formed on a resist due to excess or deficiency of exposure energy, deviation of a focus position during exposure, or the like. For example, when a positive resist is used, if the exposure energy is insufficient, the pattern size may be enlarged,
As shown in FIG. 3B, the resist remains between the patterns, causing a short circuit of the patterns. Also, if the exposure energy is excessive, the pattern size may be reduced, or
As shown in (3), a pattern defect occurs.

The pattern defects due to such causes similarly occur at the same location of all shots on the wafer surface. Therefore, pattern defects cannot be recognized by the above pattern verification method by comparing images between shots. Therefore, as described above, a wafer having the same pattern defect in all shots is regarded as a normal product and commercialized, and a failure occurs in a reliability test or in the market.

Therefore, an object of the present invention is to provide a pattern verification method capable of recognizing pattern defects caused by the surface structure of a wafer, and thereby improving the reliability of semiconductor products.

[0010]

In order to solve the above problems, the present invention is a pattern verification method for detecting a pattern defect of a resist formed on a wafer surface by photolithography, wherein the resist on the wafer surface is A feature of detecting a pattern defect of a resist by forming a plurality of simulation patterns exposed under different exposure conditions with exposure energy and a focus position as factors, and comparing and inspecting each of the plurality of simulation patterns. And

[0011]

By changing the exposure conditions with exposure energy and focus position as factors, resist simulation patterns having different pattern dimensions are formed. Then, by comparing the respective simulation patterns, the dimensional deviation of each simulation pattern is confirmed. The presence or absence of a pattern defect is determined by the value of this dimensional deviation.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. First, an example of a verification wafer 1 used for pattern verification of the present invention is shown in FIG. Verification wafer 1
Is one of the product wafers extracted from the verification process, and a simulation pattern is formed on the resist applied to the wafer surface as in the product process. This simulation pattern is formed in a plurality of shots in which a reticle mask is repeated as in the manufacturing process of a product, and each shot is given different exposure conditions with exposure energy and focus position as factors.

The exposure energy, which is one of the factors of the above exposure conditions, is an exposure energy m for forming a pattern of a target size on a resist, and a pattern of upper and lower limits of control with respect to the above target size. The exposure energy g, s is used. For example, when a positive resist is used, assuming that a pattern having a target size can be obtained with an appropriate exposure energy m, the pattern width becomes wider at a smaller exposure energy and narrower at a larger exposure energy.

The above exposure energies are obtained as follows. First, as shown in FIG. 1 (2), the focus position is kept in the focus and a pattern in which the exposure energy of each shot a to y on the wafer surface is changed stepwise is formed. At this time, the wafer 2 is the verification wafer 1 described above.
A wafer 2 similar to the above is used. Then, each shot a to y
Pattern dimension is measured by a scanning electron microscope. Then, the exposure energy g for obtaining the control upper limit of the pattern dimension, the exposure energy m for obtaining the target dimension, and the exposure energy s for obtaining the control lower limit are obtained.

The focus position, which is the other factor of the exposure condition, is the upper limit position where the position 0, which is just the focus, may deviate from the normal focus position +.
The three values of α and lower limit position-α are adopted. As shown in FIG. 2, when the focus position is shifted by a certain value or more from the position where just focus is obtained during exposure, the pattern size formed on the resist changes, but the range of the focus position adopted is the change of the pattern size. Is included in the range where does not appear.

Exposure is performed under each of the above exposure conditions to form a simulation pattern on each shot on the surface of the verification wafer 1. As shown in FIG. 1A, the exposure energies of the rows of shots formed on the wafer surface change from the top to g, s, and m. Also, the columns of shots are
From the left, the focus position changes to -α, 0, + α.

The pattern formed on each shot under the respective exposure conditions is as follows. First, since the shot is exposed at the focus position 0 where the optimum exposure energy m and just focus can be obtained, the pattern of the target dimension is formed. Next, since the shots were exposed with a small exposure energy g and a focus position of -α, a pattern that exceeds the target dimension is formed in the case of a positive type resist. Then, in the shot, since the exposure is performed with a large amount of exposure energy s and the focus position + α, a pattern smaller than the target dimension is formed in the case of the positive type resist.

Next, pattern verification is performed using the verification wafer 1 on which the simulation pattern is formed as described above. For the pattern verification, a wafer inspection machine is used to compare the simulation pattern formed on the shot of the verification wafer 1 with the simulation pattern formed on the shots. The wafer inspection machine detects differences between patterns by comparing the shapes of the patterns. Since each of the above simulation patterns is formed under unique exposure conditions, the dimensions of the patterns also differ.
Therefore, the wafer inspection machine detects a difference between the simulation patterns of shots and shots.

Then, it is confirmed whether the detected difference between the simulation patterns is within the control limit range.
Here, since the exposure conditions of each shot to are within the control limit range, the verification wafer 1 for forming a pattern is used.
If the surface state of the is uniform, the difference in the detected simulation patterns is also within the control limit. Therefore, if the difference between the simulation patterns is within the control limit, it is determined that no defect in the resist pattern due to the surface condition of the wafer will occur in the process of extracting the verification wafer 1.

On the other hand, a verification wafer 1 for forming a pattern
If the surface condition of is not uniform and the difference in material or step structure occurs due to the formation of the wiring pattern or the interlayer film, etc., the deviation of the focus position is enlarged in the step part, and in the part of different material, The exposure energy changes depending on the difference in the reflectance of the exposure light. For this reason, if the surface state of the verification wafer 1 is extremely different in material or has a step structure, the simulation pattern formed on the shots ,,, will exceed the control limit.
Therefore, if the difference between the simulation pattern formed on a shot and the simulation pattern formed on a shot exceeds the range of the control limit, the surface of the wafer is not processed in the process of extracting the verification wafer 1. It is determined that a defect in the resist pattern due to the condition occurs.

In the above embodiment, the exposure energy and the focus position, which are the factors of the exposure condition of the verification wafer 1, are set in three stages, but the present invention is not limited to this.

[0022]

As described above, according to the photolithography pattern verification method of the present invention, as described in the embodiments, the pattern defects caused by the surface structure of the wafer can be recognized. Therefore, defective products can be prevented from entering the market, etc., and the reliability of the products is expected to be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a pattern verification wafer.

FIG. 2 is a graph showing a resist pattern dimension deviation depending on a focus position.

FIG. 3 is a diagram illustrating a pattern defect of a resist depending on exposure conditions.

[Explanation of symbols]

 1 Verification wafer (wafer)

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Claims (1)

[Claims] 1. A pattern verification method for detecting a pattern defect of a resist formed on a wafer surface by photolithography, wherein the resist on the wafer surface is exposed under different exposure conditions having exposure energy and a focus position as factors. A pattern verification method is characterized in that a pattern defect of a resist is detected by forming a plurality of simulation patterns which have been subjected to the above and comparing and inspecting each of the plurality of simulation patterns.