JP2011081388A - Apparatus and process for pattern distortion detection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To verify how finished patterns differ under a plurality of process conditions or by methods of forming verification layout patterns in the manufacture of semiconductors. <P>SOLUTION: An apparatus for pattern distortion detection is provided, including: a finished pattern predicting means 2 predicting a finished pattern based on a design layout pattern or a verification layout pattern; a predicted finished pattern polygonizing means 3 converting the outline of the predicted finished pattern into a polygon; an inspection reference pattern generating means 6 generating an inspection reference pattern based on the design layout pattern or a reference layout pattern; and a pattern distortion detecting means 8 detecting a pattern distortion in a finished pattern by comparing the polygonized predicted finished pattern with the inspection reference pattern. A plurality of predicted finished patterns 5 are obtained by the finished pattern predicting means 2 with respect to a plurality of optical conditions and/or a plurality of pattern forming process conditions; and a size fluctuation range 8 of predicted finished patterns is obtained by the difference in the plurality of predicted finished patterns. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a pattern distortion detection apparatus and a detection method for detecting pattern distortion generated in a pattern formation process such as photolithography and etching used in semiconductor manufacturing. More specifically, a pattern distortion detection apparatus that detects a portion where pattern distortion exceeding an allowable range may occur by predicting a pattern formed in a semiconductor manufacturing process and detecting a difference between the prediction and a design layout pattern. And a detection method.

  At present, the design rule of semiconductor devices has reached the 0.2 μm level, which is currently smaller than the light source wavelength of the stepper for transferring it (0.248 μm when using an excimer laser). is there. In such a situation, since the resolution is extremely deteriorated, the resolution performance is improved by a special transfer technique such as a modified illumination technique.

  When this modified illumination is used, resolution is improved, but pattern fidelity is deteriorated. This will be described with reference to FIG. FIG. 67 is a diagram showing an example of the optical proximity effect in pattern formation. FIG. 67 shows the size of a resist pattern formed by using the modified illumination technique when the distance between adjacent patterns, that is, the pitch, is changed with respect to the design layout pattern fixed at a line width of 0.25 μm. Shows how it changes.

As can be seen from FIG. 67, when the pitch is 0.5 μm to 1.0 μm, the resist dimensions change rapidly. This variation varies depending on process conditions, but according to our experiments, it has been found that a maximum of 0.05 μm occurs. This variation is not an acceptable amount considering that the dimensional accuracy required by the 0.25 μm device is ± 0.03 μm or less.
Also, in the etching process, pattern dimensional variation due to pattern density difference occurs due to pattern miniaturization.

  One of the techniques developed to deal with this problem is a pitch verification technique. This will be described with reference to FIG. FIG. 68 shows an example of the pitch verification method. In such pitch verification, patterns 161, 162, 163, and 164 having a specific line width L are extracted, and then the distances between the sides of those patterns and the sides of other patterns adjacent to the sides are extracted. Edges 165 and 166 having a specific value S2 are extracted. By this method, if the sum of the line width of a pattern and the distance between adjacent sides is considered as a pitch, it can be verified that there is no pattern having a specific line width and pitch. If a pattern having a specific line width and pitch is detected, the layout pattern is corrected as necessary.

Japanese Patent Application Laid-Open No. 08-202020 Japanese Patent Laid-Open No. 08-248614 Japanese Patent Laid-Open No. 10-198820 Japanese Patent Laid-Open No. 06-181156

  The problem of this pitch verification will be described with reference to FIG. When a pattern having a specific line width L1 is extracted by the above method, all of the patterns 171, 172, 174, and 175 and a part of the pattern 173 are extracted. Next, by extracting the sides of the extracted pattern whose distance to the side of another adjacent pattern is a specific value S2, the sides 176, 177, and 179 are extracted. Of the extracted sides, the side 178 and the side 179 that are part of the side 176 are not sides to be extracted originally. The pattern variation shown in FIG. 67 exceeds the allowable range when only patterns having the same line width are adjacent to each other. However, if the adjacent pattern width is large as in the case of the side 178, the variation of the pattern is not less than the allowable range. However, the dimensional variation does not always occur. In the case of the side 179, since the length of the opposing side is small, in this case, the dimensional variation beyond the allowable range does not occur. That is, there is a problem that such a detection error cannot be avoided in the conventional pitch verification.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a pattern distortion detection apparatus and a detection method that can detect a pattern distortion with high accuracy without detection errors.
It is another object of the present invention to provide a pattern distortion detection apparatus and a detection method capable of verifying a portion where a variation in a finished predicted pattern dimension is remarkable with respect to changes in a plurality of optical conditions and a plurality of pattern formation process conditions.
Another object of the present invention is to obtain a pattern distortion detection apparatus and a detection method capable of detecting pattern distortion of a part important in terms of circuit with high accuracy and performing verification in consideration of, for example, contrast of optical intensity.
In addition, the present invention creates a plurality of finish prediction patterns different according to different optical and process conditions, and performs graphic operations between these finish prediction patterns, or design layout patterns with these Alternatively, it is an object to perform verification of a pattern distortion error with higher accuracy by performing a graphic operation with a reference layout pattern.

According to a first aspect of the present invention, there is provided a pattern distortion detecting apparatus, in which a finished pattern predicting means for predicting a finished pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process, and a finish for making the contour of the finished predicted pattern polygonal. A prediction pattern polygonizing means, an inspection reference pattern creating means for creating an inspection reference pattern based on the design layout pattern or the reference layout pattern, the polygonal finished prediction pattern, and the inspection reference pattern; Pattern distortion detecting means for detecting pattern distortion of the finished pattern by comparing
Dimensions for obtaining a plurality of finished predicted patterns by the finished pattern predicting means for a plurality of optical conditions and / or a plurality of pattern forming process conditions, and obtaining a dimensional variation width of the finished predicted pattern from the difference between the plurality of finished predicted patterns The variation width detecting means is provided.

  In the pattern distortion detection apparatus according to claim 2 of the present invention, the dimension variation width detecting means performs a difference operation between the plurality of predicted finished patterns, and performs a specified amount of undersizing on the obtained figure. Thus, a portion having a large dimensional variation in the finished predicted pattern is detected.

According to a third aspect of the present invention, there is provided a pattern distortion detection method comprising: a step of predicting a finished pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process; and a step of polygonizing the contour of the finished prediction pattern. Generating a reference pattern for inspection based on the design layout pattern or the reference layout pattern, and comparing the polygonal finished prediction pattern with the reference pattern for inspection, thereby pattern distortion of the finished prediction pattern Detecting steps,
With respect to a plurality of optical conditions and / or a plurality of pattern formation process conditions, a plurality of finished predicted patterns are obtained by the step of predicting the finished pattern, and the size variation width of the finished predicted pattern is determined from the difference between the plurality of finished predicted patterns. It is characterized by including the step which obtains.

  According to a fourth aspect of the present invention, in the step of obtaining the dimension fluctuation range, the difference calculation is performed between the plurality of predicted finished patterns, and the obtained figure is undersized by a specified amount. Thus, a portion having a large dimensional variation in the finished predicted pattern is detected.

Since the present invention is configured as described above, the following effects can be obtained.
According to the pattern distortion detection apparatus and detection method of the present invention, a highly accurate finished prediction pattern calculated using optical intensity simulation and the like, and inspection reference pattern data formed from design layout pattern data or reference layout pattern data are obtained. In comparison, pattern distortion can be detected with high accuracy.
Furthermore, it is possible to directly compare the finished predicted pattern with design layout pattern data or reference layout pattern data to detect pattern distortion, and it is possible to detect pattern distortion with high accuracy particularly with respect to the pattern line width.

  Further, according to the pattern distortion detection apparatus and detection method of the present invention, it is possible to obtain a plurality of predicted finished patterns for a plurality of optical conditions and / or a plurality of pattern formation process conditions, and obtain contrast information of the predicted finished patterns. it can. Thereby, the design layout pattern data or the reference layout pattern data can be corrected accurately.

  Further, according to the pattern distortion detection apparatus and the detection method of the present invention, it is possible to detect a portion having a small contrast of the predicted finished pattern by performing a difference calculation between a plurality of predicted finished patterns and further performing undersizing. it can. Thereby, the design layout pattern data or the reference layout pattern data can be corrected accurately.

It is a figure which shows the block diagram of the pattern distortion detection apparatus by Embodiment 1 of this invention. It is a flowchart which shows the pattern distortion detection method by Embodiment 1 of this invention. In Embodiment 1 of this invention, it is a figure which shows a design layout pattern. In Embodiment 1 of this invention, it is a figure which shows the calculation result of a finish prediction pattern. In Embodiment 1 of this invention, it is a figure which shows the polygon of a finish prediction pattern outline. In Embodiment 1 of this invention, it is a figure which shows formation of the reference pattern for a minimum inspection. In Embodiment 1 of this invention, it is a figure which shows formation of the reference | standard pattern for an upper limit test | inspection. In Embodiment 1 of this invention, it is a figure which shows the comparison with the reference | standard pattern for a minimum inspection, and a finishing prediction pattern. In Embodiment 1 of this invention, it is a figure which shows the comparison with the reference | standard pattern for an upper limit test | inspection, and a finishing prediction pattern. In Embodiment 1 of this invention, it is a figure for demonstrating the problem in the reference | standard pattern generation | occurrence | production for a test | inspection. In Embodiment 2 of this invention, it is a figure which shows formation of the test | inspection reference pattern in case the distance between pattern corners is small. In Embodiment 1 of this invention, it is a figure for demonstrating the problem in the reference | standard pattern for a test | inspection in case a pattern has a micro level | step difference. In Embodiment 3 of this invention, it is a figure which shows formation of the test | inspection reference pattern in case a pattern has a micro level | step difference. In Embodiment 4 of this invention, it is a figure which shows creation of the test | inspection reference pattern. It is a block diagram which shows the structure of the pattern distortion detection apparatus in Embodiment 5 of this invention. 8 shows a configuration of a pattern distortion detection apparatus having a pattern distortion error selection function in the sixth and seventh embodiments. As a verification layout pattern, a specific correction example of a line and space pattern is shown. 18 shows a specific example of a finished pattern based on the verification layout pattern of FIG. FIG. 19 shows a specific example of error output when the finished pattern of FIG. 18 is compared with a corrected design layout pattern. FIG. As a reference layout pattern, a specific example of a design layout pattern before correction is shown. A specific example of an error output when a finished pattern obtained from a corrected layout pattern is compared with a design layout pattern before correction is shown. 10 shows a pattern distortion detection flow according to the sixth embodiment, that is, an error selection flow by performing a logical operation with another design layer. 10 shows a specific example of an input layout pattern in the sixth embodiment. An error output example according to the sixth embodiment is shown for comparison. 10 shows a specific example of a processing process of pattern distortion detection according to the sixth embodiment. 10 shows a specific example of the result of pattern distortion detection in the sixth embodiment. FIG. 10 shows a pattern distortion detection flow according to the seventh embodiment, that is, a flow for selecting an error particularly when the finished pattern is thin or fat. 10 shows a specific example of the result of pattern distortion detection according to the seventh embodiment. The specific example of the other pattern distortion detection of Embodiment 7 is shown. 20 shows a specific example of an input layout pattern in the eighth embodiment. FIG. 31 shows a specific example of intensity distribution such as optical intensity in FIG. 30. FIG. 20 shows a specific example of another input layout pattern in the eighth embodiment. FIG. 33 shows a specific example of intensity distribution such as optical intensity in FIG. The verification result by Embodiment 1 with respect to the design layout pattern of FIG. 30 is shown for the comparison. The verification result by Embodiment 1 with respect to the design layout pattern of FIG. 32 is shown for the comparison. FIG. 31 shows a specific example of a finished pattern for the design layout pattern of FIG. 30. FIG. FIG. 33 shows a specific example of a finished pattern for the design layout pattern of FIG. 9 shows a configuration of a pattern distortion detection apparatus according to Embodiment 8, that is, a configuration of a pattern distortion detection apparatus having a contrast verification function. 10 shows a pattern distortion detection flow according to the eighth embodiment, that is, a contrast verification flow. The example of the process which processes FIG. 30 by the method of Embodiment 8 is shown. The example of the process which processes FIG. 30 on different conditions with the method of Embodiment 8 is shown. The example of the difference calculation result in the process which processes FIG. 30 by the method of Embodiment 8 is shown. FIG. 30 shows a specific example of the result of undersizing processing of FIG. 30 by the method of the eighth embodiment. The example of the process which processes FIG. 32 by the method of Embodiment 8 is shown. The example of the process which processes FIG. 32 on different conditions with the method of Embodiment 8 is shown. The example of the difference calculation result in the process which processes FIG. 32 by the method of Embodiment 8 is shown. FIG. 32 shows a specific example of the result of undersizing processing of FIG. 32 by the method of the eighth embodiment. 10 shows a configuration of a pattern distortion detection apparatus according to a ninth embodiment. It is a figure which shows the structure of the pattern distortion verification apparatus of Embodiment 10. FIG. 10 shows a pattern distortion verification flow according to the tenth embodiment. A specific example of the input layout pattern of the tenth and eleventh embodiments is shown. A finished pattern prediction example according to the first embodiment is shown for comparison. FIG. 52 shows an example in which the input layout pattern of FIG. 51 is actually formed on a wafer. FIG. 38 is a diagram for describing a specific example of the pattern prediction specification of the tenth embodiment. 10 shows an example of a predicted finished pattern according to the tenth embodiment. It is the figure which showed the structure of the pattern distortion verification apparatus of Embodiment 11-13. The pattern distortion verification flow of Embodiments 11-13 is shown. It is for demonstrating the process of the pattern prediction by Embodiment 11. FIG. FIG. 38 shows a specific example of an input layout pattern according to the twelfth embodiment. FIG. 38 is a pattern diagram for explaining a pattern prediction process according to the twelfth embodiment. FIG. 38 is a pattern diagram for explaining a pattern prediction process according to the twelfth embodiment. FIG. 38 is a pattern diagram for explaining a pattern prediction process according to the twelfth embodiment. FIG. 38 is a pattern synthesis diagram for describing a specific example of the pattern prediction specification according to the twelfth embodiment. FIG. 38 is a diagram for describing a specific example of pattern prediction specifications according to the twelfth embodiment. It is the figure which showed the structure of the pattern distortion verification apparatus by Embodiment 14. FIG. FIG. 23 shows a pattern distortion verification flow according to the fourteenth embodiment. It is a figure which shows an example of the optical proximity effect in pattern formation. It is a figure which shows the conventional pattern pitch verification method. It is a figure which shows the problem of the conventional pattern pitch verification.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a pattern distortion detection apparatus according to Embodiment 1 of the present invention. In FIG. 1, 1 is a design layout pattern data holding unit for holding a design layout pattern, 2 is a finished pattern predicting means for predicting the shape of a finished pattern after a pattern transfer process and an etching process by simulation or the like, and 3 is a finished pattern From the data output from the pattern predicting means 2, a finished prediction pattern contour polygonizing means for converting the contour of the finished pattern into polygon data (a list format of vertex coordinates), 4 is a polygon of the finished predicted pattern contour Vertex number reducing means for reducing the number of vertices of the polygon output from the converting means 3 to the number of vertices that can be handled by general CAD software, 5 is a finished prediction pattern that holds polygon data with the reduced number of vertices A data holding unit.

  Reference numeral 6 denotes an inspection reference pattern generation means for generating a reference pattern used for detecting pattern distortion exceeding an allowable range from the design layout pattern data, 7 an inspection reference pattern data holding unit, and 8 a finished product. A pattern distortion detecting unit 9 compares the predicted pattern with the reference pattern for comparison, and extracts a portion in which the pattern distortion exceeds the allowable range, and 9 is a pattern distortion information holding unit. Reference numeral 10 denotes a pattern forming process condition holding unit.

Next, the operation will be described with reference to FIGS.
FIG. 2 is a flowchart showing the operation of the pattern distortion detection apparatus having the above-described configuration. 3 is a diagram showing a design layout pattern, FIG. 4 is a diagram showing a finished prediction pattern calculated by taking in pattern formation process conditions based on the design layout pattern in FIG. 3, and FIG. 5 is a diagram of the finished prediction pattern in FIG. It is the polygonalization pattern which made the outline polygonal. FIG. 6 is a diagram showing a method for creating lower limit inspection reference pattern data, FIG. 7 is a diagram showing a method for creating upper limit inspection reference pattern data, and FIG. 8 is a diagram showing a lower limit inspection reference pattern and a finished prediction pattern. FIG. 9 is a diagram showing a comparison, and FIG. 9 is a diagram showing a comparison between a reference pattern for upper limit inspection and a predicted finished pattern.

  The operation will be described according to the flow of the flowchart of FIG. 2 with reference to the apparatus configuration of FIG. First, in the finished pattern predicting means 2, optical simulation or the like is performed by inputting the data of the design layout pattern 31 (FIG. 3) from the design layout pattern data holding unit 1 and the pattern forming process condition from the pattern forming process condition holding unit 10. Is used to calculate the shape (FIG. 4) of the predicted finished pattern 40 formed on the wafer (step ST21 in FIG. 2). Usually, the finished pattern shape data often has a pit map data structure.

Next, the polygonalization means 3 of the predicted finished pattern contour converts the predicted contour pattern data from the finished predicted pattern shape data into a polygonal finished predicted pattern 50 as shown in FIG. 5, and outputs vertex coordinates. (ST22).
Next, since the contour of the polygonal finished prediction pattern 50 has an enormous number of vertices, the vertex number reducing means 4 removes redundant vertices as much as possible or divides them into rectangles and trapezoids. Thus, the number of vertices (usually about 200 vertices) that can be handled by general CAD software is reduced (ST23). The predicted finished pattern data in which the number of vertices is reduced in this way is stored in the predicted finished pattern data holding unit 5.

Next, in the inspection reference pattern creation means 6, two types of inspection reference pattern data used for extracting a region where pattern distortion occurs beyond the allowable range in the predicted finished pattern are obtained from the design layout pattern data holding unit 1. This is created using the design layout pattern data (ST24).
One is reference pattern data for lower limit inspection. A method for creating the reference pattern data for the lower limit inspection is shown in FIG. In FIG. 6, reference numeral 61 denotes a design layout pattern, 62 denotes a rectangle, and 63 denotes a lower limit inspection reference pattern.
First, a rectangle 62 having a predetermined size is generated in the corner portion of the design layout pattern data, the design layout pattern data and an AND portion of the rectangle 62 are removed from the design layout pattern data, and an undersize corresponding to the allowable value of the pattern distortion is removed. To do. The data of the solid line pattern 63 shown in FIG. 6 is the lower limit inspection reference pattern data.

The other is reference pattern data for upper limit inspection. A method of creating the upper limit inspection reference pattern data is shown in FIG. In FIG. 7, reference numeral 71 denotes a design layout pattern, 72 denotes a rectangle, and 73 denotes an upper limit inspection reference pattern.
First, a rectangle 72 of a predetermined size is generated at the corner of the design layout pattern data, and the design layout pattern data and the rectangle 72 are ORed, and further oversized by an allowable value of pattern distortion. The data of the solid line pattern 73 shown in FIG. 7 is the upper limit inspection reference pattern data. The inspection reference pattern data thus obtained is stored in the inspection reference pattern data holding unit 7.

Next, the pattern distortion detection means 8 compares the finished predicted pattern stored in the finished predicted pattern data holding unit 5 with the lower limit inspection reference pattern stored in the inspection reference pattern data holding unit 7 (ST25). .
FIG. 8 is a diagram showing a comparison between a lower limit inspection reference pattern and a finished prediction pattern.
In FIG. 8, 80 indicates a finished prediction pattern, and 83 indicates a lower limit inspection reference pattern. The interior region of the lower test reference pattern 83 as shown in FIG. 8, region 84 and 85 are predicted finished pattern 80 is present is where the pattern distortion exceeding the allowable range occurs. Information on the position and size of this area is output (ST26) and stored in the pattern distortion information holding unit 9.

  Next, the finished prediction pattern is compared with the upper limit inspection reference pattern (ST27). FIG. 9 is a diagram showing a comparison between the upper limit inspection reference pattern and the finished prediction pattern. In FIG. 9, 90 indicates a finished prediction pattern, and 93 indicates a lower limit inspection reference pattern. As shown in FIG. 9, if the finished prediction pattern 90 is completely included in the upper limit inspection reference pattern 93, it means that there is no pattern distortion exceeding the allowable range. If the finished prediction pattern 90 exists outside the upper limit inspection reference pattern 93, distortion exceeding the allowable range has occurred, so information on the position and size of this region is output (ST28). It is stored in the pattern distortion information holding unit 9.

As described above, according to this embodiment, a highly accurate finish prediction pattern calculated using optical intensity simulation or the like is directly compared with the design layout pattern data. Can be detected.
That is, it is possible to predict the pattern distortion generated in the semiconductor pattern formation process and detect a portion where the pattern distortion exceeds the allowable range.
Furthermore, since the pattern distortion detection apparatus and detection method according to this embodiment have vertex number reduction means and steps for reducing the number of vertexes, the generation of the inspection reference pattern and the comparison between the inspection reference pattern and the finished prediction pattern A general-purpose design rule check program can be used.

  Further, in the pattern distortion detection apparatus and detection method according to this embodiment, a pattern distortion upper limit inspection reference pattern and a lower limit inspection reference pattern are separately formed, and the upper limit inspection reference pattern and the lower limit inspection reference pattern are formed separately. Pattern distortion is detected by comparison with. Therefore, it is possible to detect the pattern distortion by separately setting the allowable upper limit value and the allowable lower limit value of the pattern distortion.

In the pattern distortion detection apparatus and detection method according to this embodiment, since the inspection reference pattern is deformed so as not to detect pattern distortion at the pattern corner portion, a pattern related to a pattern line width that requires high accuracy. Only distortion can be detected with high accuracy.
In addition, the standard pattern for inspection is generated by generating a rectangle at the corner and performing only the figure operation of the rectangle and the design layout pattern, and the sizing process, so a general-purpose design rule check program can also be used. A system can be constructed easily.

The first embodiment can be summarized as follows.
The pattern detection apparatus according to the first embodiment includes a finished pattern predicting unit that predicts a finished pattern based on a design layout pattern in a semiconductor manufacturing process, and a finished predicted pattern polygonizing unit that polygonizes the contour of the finished predicted pattern. In addition, a polygonal finished prediction pattern and a design layout pattern are input, and pattern distortion detection means for the finished predicted pattern is provided by graphic calculation processing of the input data.

  The pattern detection method according to the first embodiment includes a step of predicting a finished pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process, a step of polygonizing the contour of the finished predicted pattern, and a polygon. And a step of detecting the pattern distortion of the finished predicted pattern by the graphic operation processing of the inputted data.

Next, in the first embodiment, the pattern distortion detecting apparatus shown in FIG. 1 can be configured by a computer. The pattern distortion detecting method shown in FIG. 2, recorded as a computer program in a recording medium capable of reading the process to the computer, can be performed by executing the calculation on the computer.
In this case, in the first embodiment, the following programs are recorded as programs to be executed by the computer to be recorded on the program recording medium. In other words, a process for forming design layout pattern data and pattern formation process conditions applied to the semiconductor manufacturing process in the memory area, a process for predicting a finished pattern based on the design layout pattern, and a contour of the finished predicted pattern. A process of making a square, a process of detecting a pattern distortion of the finished predicted pattern by a graphic operation process of the input data, and inputting a polygonal finished predicted pattern and a design layout pattern are recorded as a program.
Incidentally, the graphic calculation here is intended to include the case where an operation for comparing the predicted finished patterns test reference pattern and polygonal formulated created in design layout pattern group.

  In each of the embodiments described below, the pattern distortion detection apparatus can be configured by a computer. The pattern distortion detection method can be performed by recording the process as a computer program on a computer-readable recording medium and causing the computer to execute the calculation. Then, it is possible to provide a computer-readable recording medium in which each pattern distortion detection method is recorded as a program for causing a computer to execute it.

Embodiment 2. FIG.
10 and 11 are diagrams for explaining the creation of a pattern distortion inspection reference pattern according to the second embodiment of the present invention. FIG. 10 is a diagram for explaining a problem in creating an inspection reference pattern in the first embodiment, and FIG. 11 shows an inspection reference pattern in the second embodiment when the distance between corners of the pattern is small. It is a figure which shows the creation method.

In the first embodiment, in order to be able to ignore the pattern distortion of the corner portion, a rectangle of a predetermined size is generated in the corner portion of the design layout pattern, and the graphic calculation of this rectangle and the design layout pattern is performed. A reference pattern was generated.
Figure 10 is a diagram for explaining a problem that may occur in this case, in FIG. 10, 101 design layout pattern, 102 square, 103 denotes a reference pattern for the lower limit test. As shown in FIG. 10, when the size of the rectangle 102 is relatively larger than the width of the design layout pattern 101 or the length of the short side, the rectangles 102 overlap each other, and the lower limit inspection is performed. The reference pattern 103 for use becomes smaller than necessary. As a result, there arises a problem that pattern distortion on the short side of the finished pattern is not detected.

  In the second embodiment, in order to solve this problem, when the rectangles generated in the corner portion of the design layout pattern touch each other or overlap when creating the inspection reference pattern, both of the predetermined values are set. Adjust the size of the rectangle so that it is separated. This is shown in FIG. In FIG. 11, reference numeral 111 denotes a design layout pattern, 112 denotes a rectangle, and 113 denotes a lower limit inspection reference pattern.

Referring to FIG. 11, the above is formulated as follows.
The shortest distance between corners of the design layout pattern 111 is cd, the length of the side of the generated rectangle 112 is w1, the allowable pattern distortion amount is a, the length of the side of the rectangle after size adjustment is w2, and the reference pattern for the lower limit inspection Assuming that the minimum pattern width to be left as 113 is sd, the length of the side of the rectangle is changed to the width w2 calculated by the following equation (1) when cd ≦ w1.
w2 = cd−2 × a−sd (1)
As described above, by adjusting the size of the rectangle generated at the corner portion of the design layout pattern, the pattern distortion on the short side of the pattern can be detected with high accuracy.

Embodiment 3 FIG.
12 and 13 are diagrams for explaining the creation of a pattern distortion inspection reference pattern in the third embodiment of the present invention. FIG. 12 is a diagram for explaining a problem in creating a reference pattern for inspection when there is a minute step on the pattern side in the first embodiment. FIG. 13 shows a minute pattern on the pattern side according to the third embodiment. It is a figure which shows the preparation method of the test | inspection reference pattern in case there exists a level | step difference.

  In FIG. 12, 121 is a design layout pattern, 122 is a rectangle, 123 is a reference pattern for lower limit inspection, and 124 is a minute step portion. As shown in FIG. 12, in the first embodiment, when the minute step portion 124 exists in the design layout pattern 121, a reference pattern creation rectangle 122 larger than necessary is generated in the minute step portion 124. With the lower limit inspection reference pattern 123 formed in this way, pattern distortion near the minute step portion 124 cannot be detected.

  In this third embodiment, in order to solve this problem, when a rectangular pattern generated in the minute step portion of the design layout pattern becomes larger than necessary when creating the reference pattern for inspection, the side of the generated rectangular side Adjust the length in conjunction with the distance between corners. This is shown in FIG. In FIG. 13, 131 is a design layout pattern, 132 is a rectangle, 133 is a reference pattern for lower limit inspection, and 134 is a minute step portion.

Referring to FIG. 13, the above is formulated as follows.
When the distance cd ′ between corners of the minute step portion 134 of the design layout pattern 131 is a minute step that is equal to or less than a predetermined value, the length of the side of the rectangle 132 to be generated is linked to the distance cd ′ between corners. The rectangle is generated at the midpoint 135 between the corners as shown in FIG.
An example of a method for calculating the adjusted rectangular size w3 is shown below, where k is an appropriately set coefficient and b is an appropriately set constant.
w3 = k × cd ′ + b (2)

In the above example, one reduced size rectangle with a small stepped portion inside is set as the midpoint of the stepped portion, but this is set at the midpoint between some corners of the small stepped portion. Also good.
Further, both corner portions of the small stepped portion, may be set as continuous to each other a rectangular area to be reduced from the rectangular area to be set to the corners of the sides.
As described above, according to this embodiment, the pattern distortion in the vicinity of the minute step portion can be detected with high accuracy.

Embodiment 4 FIG.
FIG. 14 is a diagram for explaining the creation of a pattern distortion inspection reference pattern in the fourth embodiment of the present invention. In FIG. 14, 141 is a design layout pattern, 141c is a corner portion thereof, and 143 is a reference pattern for lower limit inspection.
In the first embodiment, in order to ignore the pattern deformation in the corner portion of the pattern, a rectangle is generated in the corner portion, and the corner portion is removed by graphic logic operation.

On the other hand, in the fourth embodiment, as shown in FIG. 14, the corner portion 141c of the design layout pattern 141 is cut obliquely and deleted, and further, the corner portion is undersized by an allowable value of pattern distortion. Negligible lower limit inspection reference pattern data 143 is created.
As described above, according to this embodiment, graphic logic operation processing becomes unnecessary, and processing speed can be increased.

Embodiment 5 FIG.
FIG. 15 is a block diagram showing a configuration of a pattern distortion detection apparatus according to Embodiment 5 of the present invention. In FIG. 15, reference numeral 11 denotes a pattern distortion amount calculation means, and 12 denotes a pattern distortion amount display means. These are added to and combined with the pattern distortion detection apparatus shown in FIG.
In FIG. 15, the pattern distortion amount calculation means 11 obtains information on the position of an area where pattern distortion exceeding the allowable range is generated from the pattern distortion information holding section 9, and the design layout pattern data holding section 1 for that area. Is compared with the predicted pattern data from the predicted pattern data holding unit 5, the difference is obtained by graphic logic operation, and is output to the pattern distortion amount display means 11.

As described above, in the fifth embodiment, when a side of a pattern in which a pattern distortion exceeding the allowable range can be detected, in order to accurately report the distortion amount of the part, the part corresponding to the side is detected. The difference between the design layout pattern data and the predicted finished pattern is obtained by graphic logic operation and output.
Thereby, the design layout pattern data can be corrected accurately. It is also possible to automatically correct the design layout pattern data.

  In each of the embodiments described above, the comparison between the finished predicted pattern and the reference pattern for inspection is described as an example. However, according to the present invention, the difference between the finished predicted patterns calculated from different design layout patterns, or different. It is also possible to verify whether or not the difference between the predicted finished patterns calculated under the pattern formation process conditions is within a certain allowable value.

In the above description of the first to fifth embodiments, when the “design layout pattern” is used as a basis for creating an inspection reference pattern, it can be referred to as a “reference layout pattern”. In this specification, this expression is used as necessary or appropriate.
In the above description of the first to fifth embodiments, the finished pattern is predicted based on the “design layout pattern”. However, when the pattern formation process is actually performed, the final pattern of the finished pattern is based on the corrected "design layout pattern" so that the same pattern as the "design layout pattern" or "reference layout pattern" is finally obtained. Predictions can be made. In this case, the corrected design layout pattern can be referred to as a “verification layout pattern”. Further, the “design layout pattern” based on the prediction of the finished pattern and the corrected design layout pattern can be referred to as “verification layout pattern”. In this specification, this expression is used as necessary or appropriate.

In the embodiment described above, in order to detect pattern distortion generated in the pattern formation process, a finished pattern after the process is obtained from the design layout pattern, the outline is polygonized, and the design layout pattern is exceeded. Alternatively, by performing a difference calculation between the undersized pattern and the finished pattern, a place where pattern distortion of a certain level or more occurs is verified.
In this method, if the difference between the design layout pattern and the finished pattern after the process is equal to or greater than a specified value (except for the corner portion), all are regarded as errors.

In the embodiments described below, this is further improved so that both errors of non-circuit critical parts and errors of critical parts can be distinguished and detected.
In addition, it is possible to perform verification of a portion where a variation in the finished predicted pattern dimension is remarkable with respect to changes in a plurality of optical conditions and a plurality of pattern formation process conditions.
Also, not only the dimensions of the finished pattern are used as verification conditions, but it is also important for the process, for example, it is possible to detect the location of patterns that are prone to errors in consideration of the contrast of optical intensity. is there.

Embodiment 6 FIG.
FIG. 16 is a block diagram showing a configuration of a pattern distortion detection apparatus according to Embodiment 6 of the present invention. In FIG. 16, 1a is a reference layout pattern data holding unit that holds a reference layout pattern, and 1b is a verification layout pattern data holding unit that holds a verification layout pattern.

  Reference numeral 13 denotes a pattern distortion information selection condition holding unit for holding a selection condition for selecting the pattern distortion information held in the pattern distortion information holding unit 9 under a given condition, and reference numeral 14 denotes a pattern distortion information selection. A pattern distortion information selection unit for selecting pattern distortion information from the pattern distortion information holding unit 9 based on a selection condition from the condition holding unit 13, and 15 an error for holding error information output from the pattern distortion information selection unit 14 It is an information holding unit. As an example, as the pattern distortion information selection condition, data of another design layer used in the semiconductor manufacturing process is used, and the pattern distortion information selection unit 14 performs a logical operation between the detected pattern distortion information and the data of another design layer. Let it be done. Other parts are the same as those in FIG.

This embodiment is characterized in that it includes a pattern distortion information selection unit 14 that receives the pattern distortion information holding unit 9, the reference layout pattern data holding unit 1a, and the pattern distortion information selection condition holding unit 13.
In the configuration shown in FIG. 1 of the first embodiment, the design layout pattern data holding unit 1 is input to both the finished pattern predicting unit 2 and the inspection reference pattern creating unit 6, but in FIG. Different data of the holding unit 1b and the reference layout pattern data holding unit 1a are input. This is an example generally used, and the present invention is not limited to this.

Here, the reference layout pattern is a design layout pattern before correction, and is a pattern to be finally formed.
The verification layout pattern may be the same pattern as the design layout pattern before correction (that is, the same pattern as the reference layout pattern) or the layout pattern after correction. The corrected layout pattern is a pattern obtained by correcting the design layout pattern so that the same pattern as the design layout pattern or the reference layout pattern is finally obtained when the pattern formation process is actually performed.

  This will be described with reference to a specific example. FIG. 17 shows a line and space pattern as the verification layout pattern 171. FIG. 18 shows a finished pattern 181 based on the verification layout pattern 171 shown in FIG. FIG. 19 shows an error output 191 when the finished pattern 181 of FIG. 18 is compared with the verification layout pattern 171 for reference.

FIG. 20 shows a reference layout pattern (design layout pattern before correction) 201. FIG. 21 shows an error output when the finished pattern 181 obtained from the verification layout pattern 171 is compared with the reference layout pattern 201. Thus, the reference layout pattern 201 is corrected to the verification layout pattern 171 so that no error output is generated, and is used in an actual pattern forming apparatus.
Above, as a modification of FIG. 1 of the first embodiment, shows the example in which verification layout pattern is used, this is not essential to the sixth embodiment.

Next, the operation of the feature points of the sixth embodiment will be described.
FIG. 22 is a flowchart showing the operation of the pattern distortion detection apparatus of FIG.
First, in step 221 (ST221) of FIG. 22, the pattern distortion shown in FIG. 16 is performed in the same manner as the flow from step 21 (ST21) to step 28 (ST28) of the pattern distortion detection flow shown in FIG. The pattern distortion information is output to the information holding unit 9.

  Next, in step 222 (ST222), based on the pattern distortion information selection condition from the pattern distortion information selection condition holding unit 13, the pattern distortion information selection unit 14 determines whether the reference layout pattern or the design layout pattern and the pattern distortion information. Then, the graphic calculation is performed, and the result is output to the error information holding unit 15 as error information. For example, an error is selected by performing a logical operation between another design layer and the error.

The above operation will be described with reference to a specific example. FIG. 23 shows a specific example of the design layout pattern. In FIG. 23, reference numeral 231 denotes a gate wiring of a transistor, and 232 denotes an active region.
FIG. 24 shows an error output example as a result of performing pattern distortion verification by the method of the first embodiment using the gate wiring 231 as an input. In FIG. 24, reference numeral 231 denotes a gate wiring of a transistor, 232 denotes an active region, and 241 denotes a pattern distortion error. In FIG. 24, in terms of circuit, the error 241 on the active region 232 is important as a dimension that determines the characteristics of the transistor, but the other portions do not require high accuracy in terms of circuit. Therefore, a function of classifying these errors according to the importance on the circuit is desired and necessary.

  FIG. 25 shows an example of error output as a result of pattern distortion verification according to the sixth embodiment. 25, reference numeral 232 denotes an active region, and reference numeral 251 denotes an error output from the pattern distortion information holding unit 9 in step 221 (ST221) of FIG.

In the sixth embodiment, the error classification according to the importance on the circuit is performed by changing the pattern distortion information selection condition from the pattern distortion information selection condition holding unit 13 in FIG. This is performed by inputting to the pattern distortion information selecting means 14.
This as input, the pattern distortion information selecting means 14, when the operation of "performing an AND operation on error and the active region", it is possible to select only errors on the active region.

FIG. 26 shows errors selected in this way and output to the error information holding unit 15. In FIG. 26, reference numeral 231 denotes a transistor gate wiring, 232 denotes an active region, and 261 is classified according to importance. Indicates an error.
As described above, according to this embodiment, it is possible to select and detect an error of a circuit important part.

As described above, according to this embodiment, it is possible to predict the pattern distortion generated in the semiconductor pattern forming process and detect the portion where the pattern distortion exceeds the allowable range.
In addition, it is possible to obtain a pattern distortion detection method and a pattern distortion detection apparatus that can select errors by performing a logical operation between other design layers and pattern distortion errors.
In addition, it is possible to provide a pattern distortion error selection function for selecting the importance of errors. In other words, by selecting the detected pattern distortion errors, it is possible to detect important errors with high functionality.

Embodiment 7 FIG.
Also in the seventh embodiment, the pattern distortion detecting device of FIG. 16 shown in the sixth embodiment is used.
Next, the operation will be described.
FIG. 27 is an error selection flow in the seventh embodiment. The difference from the flow of FIG. 2 of the first embodiment is step 26a (ST26a) and step 28a (ST28a), and the other is the same. However, step ST21 in FIG. 27 is based on the verification layout pattern, and step ST24 is based on the reference layout pattern.

  In FIG. 2 of the first embodiment, in step 25 (ST25), it is asked whether or not the lower limit inspection reference pattern data is completely included in the finished prediction pattern, and in step 26 (ST26), the position of the portion not included. , Output size information. Further, in step 27 (ST27), it is asked whether or not the finished prediction pattern is completely included in the upper limit inspection reference pattern. In step 28 (ST28), information on the position and size of the part not included is output. To do. Both of these outputs are output to the same display destination.

On the other hand, in the seventh embodiment, in step 25 (ST25), it is asked whether the reference pattern data for lower limit inspection is completely included in the finished prediction pattern, and is not included in step 26a (ST26a). The information on the position and size of the portion is output to a predetermined display destination as an error that narrows the information. Further, in step 27 (ST27), it is asked whether the finished prediction pattern is completely included in the upper limit inspection reference pattern. In step 28a (ST28a), information on the position and size of the portion not included is fattened. Output to another display destination as an error. That is, both outputs are output to different display destinations, and are displayed separately or displayed in different colors.
As described above, this embodiment is greatly different from the first embodiment in that the error output destinations detected in step 26a (ST26a) and step 28a (ST28a) are different.

  This will be described with reference to a specific example. FIG. 28 shows a verification result when the gate wiring 231 of the transistor in FIG. 23 is a verification target. In FIG. 28, 231 is a gate wiring of a transistor, 232 is an active region, 281 is an error that is distorted in a direction in which the pattern is thinned, 282 is an error that is distorted in a direction in which the pattern is thickened, and both are selected and output. . In this example, the difference in color display is indicated by the difference in hatching.

As described above, according to this embodiment, it is possible to select and detect a portion where the pattern distortion is thick and a portion where the pattern distortion is thick.
Further, FIG. 29 shows a result of combining the sixth embodiment and the seventh embodiment to select errors in a circuit-important part, and distinguishing and detecting a thin pattern error 291 and a fat error 292 Is shown.

  As described above, according to this embodiment, it is possible to obtain a pattern distortion detection method and apparatus for selecting an error depending on whether a finished pattern is thin or thick with respect to a design layout pattern or a reference layout pattern.

Embodiment 8 FIG.
In each of the embodiments described above, a portion having a large pattern distortion is detected by comparing between the predicted finish pattern data and the design layout data (or reference layout data). However, as an important factor in the process, there is a problem of contrast in addition to the predicted pattern size.
FIG. 30 shows an example of the design layout pattern 301. FIG. 31 shows the resist solubility calculated from the optical intensity, the optical intensity, etc., or the etching rate distribution for the portion indicated by the broken line AA in FIG. The horizontal axis indicates the position on the broken line AA in FIG. 30, and the vertical axis indicates the intensity. Similarly, FIG. 32 shows another design layout pattern 321, and FIG. 33 shows a similar graph for the broken line BB in FIG. 32.

  In the pattern distortion verification according to the first embodiment, a finished pattern is predicted assuming that a portion having a certain intensity, such as the intensity t in FIGS. 31 and 33, is an edge of the finished pattern, and this pattern and the design layout pattern A portion with large distortion was detected. FIGS. 34 and 35 show the results of verifying the design layout patterns of FIGS. 30 and 32 according to the first embodiment, respectively. In FIG. 34, 301 is a design layout pattern, and 341 is a finished pattern predicted by the aforementioned intensity t. In FIG. 35, reference numeral 321 denotes a design layout pattern, and reference numeral 351 denotes a finished pattern predicted by the above-described intensity t. In FIG. 34 and FIG. 35, the amount of deviation between the finished pattern and the design layout pattern does not change, so there is no difference in the verification result.

  However, the process conditions fluctuate due to some factors, and the pattern edge determined by the strength t in FIG. 31 or FIG. 33 may be determined by the strength tu or the strength tl. FIG. 36 shows a finished pattern when the strength for determining the pattern edge is changed for the design layout pattern of FIG. 36, reference numeral 301 denotes a design layout pattern, reference numeral 361 denotes an intensity t, reference numeral 362 denotes an intensity tu, and reference numeral 363 denotes a finished pattern when the finished pattern edge is determined based on the intensity tl.

Similarly, a finished prediction pattern for the design layout pattern of FIG. 32 is shown in FIG. 37, reference numeral 321 denotes a design layout pattern, 371 denotes a strength t, 372 denotes a strength tu, and 373 denotes a finished pattern when a finished pattern edge is determined with a strength tl. Compared to FIG. 36, it can be seen that in FIG. 37, the dimensional variation of the finished pattern is significant when the strength for determining the finished pattern is changed. This is because, as seen by comparing the graphs of FIGS. 31 and 33, in the case of FIG. 37, as compared with the case of FIG. 36, because the intensity contrast at the pattern edges is small. Since the finish of the pattern is poor in a portion where the contrast is small, it is necessary to verify such a portion.
When the optical condition is changed, the optical intensity distribution itself changes. For example, when the defocus value is changed among the optical conditions, the optical intensity itself changes. Even in such a case, it is necessary to verify a portion where the difference in pattern variation is large.
In the eighth embodiment, pattern distortion detection corresponding to such a problem will be described.

FIG. 38 is a block diagram showing the configuration of the pattern distortion detection apparatus according to the eighth embodiment.
In FIG. 38, 16 is a contrast verification condition holding unit for holding a condition for verifying the contrast of the pattern, 17 is a contrast information detecting means for detecting pattern contrast information based on the contrast verification condition, and 18 is a result of the verification. A contrast information holding unit that holds Further, a plurality of finished predicted pattern data holding units 5 are provided, and two are shown here as an example.

  The configuration of the eighth embodiment is different from the first embodiment in that a plurality of finished predicted pattern data holding units 5 are provided, and a plurality of finishes predicted by a plurality of optical conditions or pattern formation process conditions, for example, a plurality of optical intensities. The prediction pattern data is held respectively, and contrast information detecting means 17 having the contrast verification condition holding unit 16 as an input is provided, and the output thereof is held in the contrast information holding unit 18. . As the contrast verification condition, for example, a pattern undersizing amount described later is set to a predetermined value, and the contrast information holding unit 18 holds this value.

Next, the operation will be described.
FIG. 39 is a flowchart showing the operation of the pattern distortion detection apparatus of FIG. In step 391 (ST391) and step 392 (ST392), a finished predicted pattern is calculated under different optical conditions or pattern formation process conditions depending on the apparatus shown in FIG. 38, and each is output to the finished predicted pattern data holding unit 5. In step 393 (ST393), the contrast information detection means 17 determines which of these outputs is the difference calculation in the next process based on the mask correct / inverse information or the magnitude inclusion relation between the output figures. Which one should be difference-calculated from?

  In step 394 (ST394), a difference calculation is performed between the predicted finished patterns. In step 395 (ST395), the result of the difference calculation is undersized for a specified amount according to the verification condition from the contrast verification condition holding unit 16, and the result is output to the contrast information holding unit 18. By performing undersizing in this way, it is possible to detect only a portion having a small contrast.

  Hereinafter, a description will be given according to a specific example. When the verification layout pattern 301 in FIG. 30 is input, a finished prediction pattern 401 as shown in FIG. 40 is obtained at step 391 (ST391) in FIG. 39, and a finished prediction pattern 411 as shown in FIG. 41 is obtained at step 392 (ST392). Is output. In this case, as a plurality of optical conditions or pattern formation process conditions, the optical intensity of exposure for pattern formation is changed.

Next, in step 393 (ST393), it is determined that the result of FIG. 41 is difference-calculated from the result of FIG. FIG. 42 shows a pattern 421 obtained as a result of performing the difference calculation in step 394 (ST394). Further, when undersizing is performed in order to detect a portion having a low contrast, the result is as shown in FIG. Since there is no low contrast part, no error graphic is output.
Here, undersizing means that the outside of the pattern 421 in FIG. 42 (that is, the outside of the pattern 401 in FIG. 40) is reduced by a predetermined amount, and the inside of the pattern 421 in FIG. 42 (that is, outside the pattern 411 in FIG. 41). Enlarging a predetermined amount.

Similarly, when the verification layout pattern 321 in FIG. 32 is input, a finished pattern 441 as shown in FIG. 44 is obtained in step 391 (ST391) in FIG. 39, and as shown in FIG. 45 in step 392 (ST392). A finished pattern 451 is output. After step 393 (ST393), in step 394 (ST394), the pattern of FIG. 46 is obtained by subtracting the figure of FIG. 44 to FIG. 45, and when further undersizing, an error pattern 471 as shown in FIG. can get.
Thus, according to this embodiment, it is possible to detect a low-contrast portion, which is a portion with a poor process condition, in the predicted finished pattern.

As described above, according to this embodiment, a finished predicted pattern is obtained for a plurality of optical conditions or a plurality of pattern formation process conditions, for example, a plurality of optical intensities, a difference calculation is performed between them, and the remaining figure By performing undersizing for a specified amount, a pattern distortion detection method and apparatus for detecting a low contrast portion and performing contrast verification can be obtained.
This also makes it possible to obtain a pattern distortion detection method and apparatus having a contrast verification function that outputs a pattern distortion error to a portion where the optical intensity contrast is smaller than a certain value.
Thus in this embodiment, it can verify the variation is significant part of the predicted finished pattern dimension to changes in the plurality of optical conditions and multiple patterning process conditions.

The eighth embodiment can be summarized as follows.
The pattern detection apparatus according to the eighth embodiment includes a finish pattern predicting unit that predicts a finish pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process, and a finish prediction pattern multiple that polygons the contour of the finish prediction pattern. The apparatus includes a square forming unit and a pattern distortion detecting unit for a predicted finished pattern by inputting a polygonal finished predicted pattern and performing a graphic operation process on the input data.

  The pattern detection method according to the eighth embodiment includes a step of predicting a finished pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process, a step of polygonizing the contour of the finished prediction pattern, and a polygon. And the step of detecting the pattern distortion of the finished predicted pattern by the graphic calculation processing of the inputted data.

Next, in the eighth embodiment, the pattern distortion detection device can be configured by a computer. The pattern distortion detection method can be performed by recording the process as a computer program on a computer-readable recording medium and causing the computer to execute the calculation.
In this case, in the eighth embodiment, the following are recorded as programs to be executed by the computer that records on the program recording medium. That is, a process of forming design layout pattern or verification layout pattern data and pattern formation process conditions applied to the semiconductor manufacturing process in a memory area, and a process of predicting a finished pattern based on the design layout pattern or verification layout pattern As a program, the process of polygonizing the contour of the finished predicted pattern and the process of detecting the distortion of the predicted pattern of the finished pattern by the input of the polygonal finished predicted pattern and the figure calculation processing of the input data Record.
Note that the graphic calculation here includes a case in which a plurality of polygonal finished prediction patterns are compared with each other.

  In each of the embodiments described below, the pattern distortion detection apparatus can be configured by a computer. The pattern distortion detection method can be performed by recording the process as a computer program on a computer-readable recording medium and causing the computer to execute the calculation. Then, it is possible to provide a computer-readable recording medium in which each pattern distortion detection method is recorded as a program for causing a computer to execute it.

Embodiment 9 FIG.
Figure 48 is a combination of FIGS. 16 and 38, is a block diagram showing an example of a configuration of a pattern distortion detecting apparatus including both the function described in Embodiment 6-8 of the embodiment. As described above, the pattern distortion detection apparatus having all the functions of the sixth to eighth embodiments can be obtained.

  In the sixth to ninth embodiments, only the detection of the pattern distortion portion is described. However, it is obvious that the design layout pattern data can be automatically corrected based on the detection result. In addition, it is obvious that errors can be selected based on the level of contrast, and the design layout pattern data can be automatically corrected using the result.

Embodiment 10 FIG.
In each of the embodiments described above, for example, typically the first embodiment, in the pattern distortion detection apparatus and the pattern distortion detection method described with reference to FIGS. 1 and 2, a single finished prediction pattern is used. Since pattern distortion is verified, there is a limit to performing high-accuracy verification when the optical and process conditions are partially different.
Each embodiment to be described below is made to solve the above-described problems. A plurality of different prediction patterns are created according to different optical and process conditions, and a design layout pattern (reference) is created. An object of the present invention is to perform verification of a pattern distortion error with higher accuracy by performing a graphic operation with a layout pattern.

FIG. 49 is a block diagram showing the configuration of the pattern distortion detection apparatus of the tenth embodiment.
49 is compared with FIG. 1, the design layout pattern data holding unit 1 in FIG. 1 is broken down into a reference layout pattern data holding unit 1a and a verification layout pattern data holding unit 1b in FIG. Since it has already been shown in the configuration of FIG. 16 in the sixth embodiment, it is not a new point of this embodiment.

The configuration of FIG. 49 is different from the configuration of FIG. 1 as follows. First, a first highly accurate finished pattern predicting means 19 is newly connected to the finished predicted pattern data holding unit 5. In addition, a first finished pattern prediction specification holding unit 20 is connected as input to the first highly accurate finished pattern predicting means 19, and a first highly accurate finished predicted pattern data holding unit 21 is connected as an output. . Further, the reference layout pattern data holding unit 1a is connected to the first high precision finished pattern predicting means 19 as an input. Further, the output of the first highly accurate finished predicted pattern data holding unit 21 is connected to the pattern distortion detecting means 8.
As described above, in the tenth embodiment, the first high-accuracy finish using the reference layout pattern data holding unit 1a, the finished predicted pattern data holding unit 5, and the first finished pattern predicted specification holding unit 20 as inputs. The pattern predicting means 19 is included.

Next, the operation will be described.
FIG. 50 is a flowchart showing the operation of the pattern distortion detection apparatus having the above-described configuration.
Steps 501 (ST501) to 503 (ST503) in the flow of FIG. 50 are the same as steps 21 (ST21) to 23 (ST23) in FIG. 2 of the first embodiment. Further, the steps after step 505 (ST505) in FIG. 50 are the same as those after step 25 (ST25) in FIG.

  Step 504 (ST504) in FIG. 50 is a feature of this embodiment, and in this step 504 (ST504), a finished predicted pattern is increased corresponding to a plurality of optical conditions and / or a plurality of pattern formation process conditions. Based on the first finished pattern prediction specification for accuracy, a graphic operation is performed between the reference layout pattern and the predicted pattern.

Here, the finished pattern prediction specification means a logic for performing a graphic operation between a finished predicted pattern predicted by a plurality of different optical conditions or pattern formation process conditions and a reference layout pattern.
In the first finished pattern prediction based on the first finished pattern predicting specification, it performs graphics operations between the reference layout pattern and a single predicted finished patterns.

  In addition, in this specification, the term “graphic operation” means processing such as AND, OR, NOT, XOR, sizing, inclusion relation between figures, contact, corner processing, internal / external spacing, etc., which can be performed by a general layout verification tool. Are performed alone or in combination.

FIG. 51 shows a specific example of an input layout pattern, that is, a design layout pattern.
In FIG. 51, reference numeral 511 denotes an active region of a transistor, and 512 denotes a gate wiring of the transistor. Of these, FIG. 52 shows the result of pattern prediction performed by the method of the first embodiment using the gate wiring 512 as an input. 52, reference numeral 521 denotes the same active region as that in FIG. 51, and reference numeral 522 denotes a pattern prediction when the gate wiring 512 in FIG. 51 is input.

  On the other hand, FIG. 53 shows a pattern shape when an input layout pattern is actually formed on a wafer. 53, reference numeral 531 denotes the same active region as in FIG. 51, and reference numeral 532 denotes a pattern shape in which the gate wiring 512 in FIG. 51 is actually formed on the wafer. Comparing FIG. 52 and FIG. 53, it can be seen that the shapes of the portions not overlapping with the active regions 521 and 531 are greatly different.

  In the actual wafer process, the area of the active area 521 is formed and then the area of the gate wiring 522 is formed. However, in an actual wafer, there is a difference in height in the normal direction on the paper surface inside and outside the area of the active area 521 figure. . Therefore, the pattern of the gate wiring 522 is formed differently inside and outside the active region 531 as shown in FIG. Therefore, it is necessary to have a function of changing the pattern prediction method at a portion where the layout conditions are different, such as inside and outside of the active region 531.

54 is a diagram for explaining a specific example of the pattern prediction specification of the embodiment 10, and shows the relationship between the predicted pattern of the gate wiring and the active region (the active regions 511, 521, 531 in FIGS. 51 to 53). .
In FIG. 54, 541 is an active region, 542 is a prediction pattern of a gate wiring, of which 542a is a prediction pattern outside the region 541, and 542b is a prediction pattern within the region 541. The prediction patterns 542a and 542b can be obtained by NOT processing and AND processing of the prediction pattern 542 and the active region 541, respectively.

  Here, the first high-precision finished pattern predicting means 19 supplies the finished pattern prediction specification supplied from the first finished pattern prediction specification holding unit 20 for graphic calculation as “undersize the region of the predicted pattern 542a. The result and the prediction pattern 542b are merged (OR process) ”, thereby obtaining a prediction pattern 552 shown in FIG. The active region 551 in FIG. 55 is the same as that in FIGS. Thus, FIG. 55 shows an example of a finished pattern prediction according to this embodiment.

As described above, by applying the finished pattern prediction specification to the flow of FIG. 50, it is possible to obtain a prediction pattern close to the state of FIG.
Here, after the region of the prediction pattern 542 is limited, the graphic calculation of the prediction pattern 542 and the active region 541 is performed. However, the graphic calculation can be performed on the entire prediction pattern 542 without limiting the region. is there.

  As described above, in this embodiment, a polygonal finished prediction pattern and a reference layout pattern are highly accurate based on a finished pattern prediction specification corresponding to a plurality of optical conditions or a plurality of pattern formation process conditions. It is possible to increase the accuracy of the polygonal finished prediction pattern by performing graphic calculation in the normalized finished pattern predicting means 19.

  As described above, according to this embodiment, it is possible to predict a finished pattern for a process with partially different conditions and to verify pattern distortion by this. Further, it is apparent that this embodiment is effective not only for the influence due to the step, but also for the deformation of the prediction pattern generally correlated with the layout.

Embodiment 11 FIG.
FIG. 56 is a block diagram showing the configuration of the pattern distortion detection apparatus according to the eleventh embodiment.
The difference from the configuration of the tenth embodiment shown in FIG. 49 is as follows. First, in FIG. 56 of this embodiment, the configuration from the finished pattern predicting means 2 to the finished predicted pattern data holding unit 5 in FIG. 49, that is, the finished pattern predicting means 2, the finished predicted pattern contour polygonizing means. 3, the vertex number reducing means 4 and the finished predicted pattern data holding unit 5 are provided with a plurality of systems. FIG. 56 shows two systems.

  In FIG. 56, the second high-precision finished pattern predicting means 22 is provided, and a plurality of finished predicted pattern data holding units 5 are connected to this as input. In addition, a second finished pattern prediction specification holding unit 23 is connected to the second highly accurate finished pattern predicting means 22 as an input, and a second highly accurate finished predicted pattern data holding unit 24 is connected as an output. ing. Further, the output of the second highly accurate finished predicted pattern data holding unit 24 is connected to the pattern distortion detecting means 8. Note that the reference layout pattern data holding unit 1a is connected to the second high-accuracy finished pattern predicting means 22 as an input.

As described above, according to the eleventh embodiment, the second high accuracy is obtained by using the reference layout pattern data holding unit 1a, the plurality of finished predicted pattern data holding units 5, and the second finished pattern predicted specification holding unit 23 as inputs. The finish pattern predicting means 22 is included.
Here, the finished pattern prediction specification means a logic for performing a graphic operation between a finished predicted pattern predicted by a plurality of different optical conditions or pattern formation process conditions and a reference layout pattern.
Further, in the second finished pattern prediction based on the second finished pattern prediction specification, a graphic operation is performed between a plurality of finished predicted patterns.

Next, the operation will be described.
FIG. 57 is a pattern distortion detection flow in this embodiment. Steps 571 (ST571) to 573 (ST573) in the flow of FIG. 57 are the same as steps 501 (ST501) to 503 (ST503) in FIG. 50 of the tenth embodiment. Also, Step 576 (ST576) and subsequent steps in FIG. 57 are the same as Step 505 (ST505) and subsequent steps in FIG.

  Steps 574 (ST574) and 575 (ST575) in FIG. 57 are the features of this embodiment. In FIG. 50 of the tenth embodiment, the finished prediction pattern is obtained under one condition, but this embodiment is implemented. In step 574 (ST574), the flow from step 571 (ST571) to step 573 (ST573) includes a plurality of flows corresponding to a plurality of conditions, that is, a plurality of optical conditions or a plurality of pattern formation process conditions. Do it once.

  In this way, the second highly accurate finished pattern predicting means 22 for a plurality of finished patterns obtained in step 575 based on the second finished pattern prediction specification supplied from the second finished pattern prediction specification holding unit 23. In (ST575), a figure calculation is performed by calculating a figure.

  This will be specifically described below. FIG. 58 is a diagram for explaining the pattern prediction process according to this embodiment. When the gate wiring 512 of FIG. 51 is a verification target, the optical or process conditions differ between the inside and outside of the active region 511 as described above. In contrast, FIG. 58 shows an example in which a pattern is predicted under different conditions. The active region 581 in FIG. 58 is the same as the active region 511 in FIG. 51, 582 in FIG. 58 is a pattern predicted under conditions outside the active region 581, and 583 is a pattern predicted under conditions in the active region 591. is there.

Next, in the second high-precision finished pattern predicting means 22, the finished predicted pattern is converted into a reference layout pattern and a graphic based on the predicted specification of the second finished pattern from the second finished pattern predicted specification holding unit 23. Operate and merge the results.
Here, assuming that the prediction specification of the second finished pattern is “merge (OR process) the result of AND processing of the prediction patterns 583 and 581 and the result of NOT processing of the prediction patterns 582 and 581”. A result close to an actual pattern as shown in FIG. 53 can be obtained.

  As described above, according to this embodiment, a plurality of finished patterns are predicted corresponding to a plurality of processes in which optical conditions or pattern formation process conditions are partially different, and the reference layout pattern (design layout pattern). And figure calculation are performed, and the results are merged to create a highly accurate finished prediction pattern. Then, it becomes possible to perform pattern distortion verification with higher accuracy than in the tenth embodiment by using the finished prediction pattern with higher accuracy. Further, it is apparent that this embodiment is effective not only for the influence due to the step, but also for the deformation of the prediction pattern generally correlated with the layout.

Embodiment 12 FIG.
The pattern distortion verification apparatus and verification flow in the twelfth embodiment will be described using the same diagram as in the eleventh embodiment. (The configuration and verification flow of the pattern distortion verification apparatus in the twelfth embodiment are the same as those in the eleventh embodiment.)
In the eleventh embodiment, the figure calculation is performed between the plurality of finished prediction patterns and the reference layout pattern (design layout pattern). In the present embodiment, an example of performing the figure calculation between the plurality of finished prediction patterns is shown. .

  FIG. 59 shows an input layout pattern, that is, a layout pattern to be verified. 60 to 62 show finish prediction patterns predicted under different conditions. FIG. 63 is a diagram for explaining a specific example of the pattern prediction specification according to this embodiment, and is displayed by superposing FIGS. 60 to 62.

When verifying pattern distortion under a plurality of conditions, a case where the predicted pattern is most distorted through a plurality of conditions is often obtained.
When the pattern is the smallest, it can be obtained by AND processing of all the finished predicted patterns (predicted pattern 633 in FIG. 63), and when the pattern is the largest, it can be obtained by OR processing of all the finished predicted patterns. (Finish prediction pattern 632 in FIG. 63).

  Furthermore, according to the present invention, as shown in FIG. 64, the predicted finished pattern of the active region 581 (641 in FIG. 64) is used instead of the active region 581 of FIG. 58 shown in the eleventh embodiment. By performing graphic processing between the finished prediction patterns 642 and 643, it is possible to perform prediction with higher accuracy. FIG. 64 is for explaining a specific example of the pattern prediction specification according to this embodiment.

Embodiment 13 FIG.
It is obvious form 10 to 12 of the embodiment it is possible to obtain the same effect by performing in combination respectively, that the case structure is the same as FIG. 56.
In the above embodiments 10 to 13, only the detection of the pattern distortion portion has been described. However, it is obvious that the design layout pattern data can be automatically corrected based on the detection result.

Embodiment 14 FIG.
In each of the embodiments described above, for example, typically in Embodiment 1, a finished pattern is predicted from a design layout pattern, and a figure operation is performed between the predicted pattern and the design layout pattern. A portion distorted more than an allowable amount with respect to the design layout pattern is detected (see FIG. 1).
Further, for example, in the sixth embodiment, a finished pattern is predicted from the verification layout pattern, and graphic calculation is performed between the predicted pattern and the reference layout pattern, so that the finished predicted pattern exceeds the allowable amount with respect to the reference layout pattern. A distorted portion is detected (see FIG. 16).
However, in these embodiments, among the plurality of different process conditions and different verification layout pattern generating method, it is impossible to verify whether the finished pattern is how different.

  The fourteenth embodiment to be described below is made to solve the above-described problems. By performing a graphic operation on a plurality of finished prediction patterns created under different conditions, a plurality of finished prediction patterns can be obtained. The purpose of this is to verify the difference in the results between the conditions by detecting the difference points in.

FIG. 65 is a block diagram showing the configuration of the pattern distortion detection apparatus according to the fourteenth embodiment.
In FIG. 65, a verification layout pattern data holding unit 1b, a pattern formation process condition holding unit 10, a finished pattern predicting unit 2, a finished predicted pattern contour polygonizing unit 3, a vertex number reducing unit 4, and a finished predicted pattern data holding unit. 5 is the same as FIG. 16, but in FIG. 65, these are provided in a plurality of systems.

Further, a finished predicted pattern comparison unit 25 is newly connected to the plurality of finished predicted pattern data holding units 5. Furthermore, predicted finished pattern data comparing specification holding section 26 to the predicted finished pattern comparing means 25 is connected as an input, finished pattern difference information holding section 27 is connected as an output.
Thus, the fourteenth embodiment is characterized in that it includes a finish prediction pattern comparison means 25 that receives a plurality of finish prediction pattern data holding units 5 and a finish prediction pattern data comparison specification holding unit 26 as inputs.

Next, the operation will be described.
FIG. 66 is a flowchart showing the operation of the pattern distortion detection apparatus having the above-described configuration. Steps 661 to 663 (ST661 to ST663) and steps 661 ′ to 663 ′ (ST661 ′ to ST663 ′) in FIG. 66 are the same as steps 21 to 23 (ST21 to 23) in FIG. However, step ST661 and step ST661 ′ in FIG. 66 are based on the verification layout pattern.

  The difference between the steps 661 to 663 (ST661 to ST663) and the steps 661 ′ to 663 ′ (ST661 ′ to ST663 ′) is different in the verification layout pattern data and / or the pattern formation process conditions used in each processing. Only.

  Next, in step 664 (ST664), a graphic operation is performed between a plurality of predicted finished pattern data based on the predicted finished pattern comparison specification from the finished predicted pattern comparison specification holding unit 26, and the result is used as finished predicted pattern difference information. Output and finish pattern difference information retention

As described above, in the present embodiment, a difference is detected by performing a graphic operation between the points 661 to 663 (ST661 to ST663) including a plurality of systems and a plurality of predicted finished patterns obtained therefrom. It is characterized by having a step 664 (ST664) for doing this.
In other words, in this embodiment, an XOR process between two finished pattern data is performed and the result is output.

Next, a modification of this embodiment will be described.
One aspect of the comparison between the plurality of predicted finished patterns, among the plurality of predicted finished patterns, select the specific predicted finished pattern, to create a test reference pattern based on this. Then, the reference pattern for inspection is compared with a plurality of predicted finished patterns, or a graphic operation is performed between a plurality of predicted finished pattern data.

In this case, as an inspection reference pattern, an upper limit inspection reference pattern that defines an allowable upper limit that is larger than a specific finished prediction pattern and a lower limit inspection reference pattern that defines an allowable lower limit that is reduced from a specific finish prediction pattern are created. Then, the upper limit and lower limit inspection reference patterns and a plurality of finished prediction patterns are compared by NOT processing.
Since this process is the same as that described in Embodiment 1 with reference to FIG. 2 (ST24), FIG. 6, FIG. 7, and the like, detailed description thereof is omitted.

As described above, according to this embodiment, it is possible to detect a difference between a plurality of predicted finished patterns. It is also obvious that the different parts detected by this method can be classified as follows.
In other words, selecting whether the finished pattern is thinner or thicker than the reference layout pattern, performing a logical operation between the pattern distortion and another design layer, selecting pattern distortion information, and also performing pattern distortion by this logical operation. You can sort the importance of Since these have already been described in Embodiments 6 and 7, etc., redundant description is omitted.

  As described above, in this embodiment, a plurality of finished patterns are predicted by predicting a plurality of finished patterns corresponding to a plurality of different pattern formation process conditions and / or a plurality of verification layout pattern data. Differences between predicted pattern data can be detected by performing graphic operations on the data.

Now, one aspect of the present invention described above with respect to each embodiment can be summarized as follows.
A pattern detection apparatus according to an aspect of the present invention includes a finish pattern predicting unit that predicts a finish pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process, and a finish prediction pattern that polygonizes the contour of the finish prediction pattern Polygonizing means and only the polygonal finished prediction pattern, or the polygonal finished prediction pattern and the design layout pattern are input, and the pattern distortion detection means of the finished prediction pattern from the figure of the input data Is provided.

  The pattern detection method of one aspect of the present invention includes a step of predicting a finished pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process, a step of polygonizing the outline of the finished predicted pattern, A step of detecting a pattern distortion of the finished predicted pattern only by a squared finished predicted pattern or a polygonal finished predicted pattern and a design layout pattern as input. It is what.

Next, in the invention, the pattern distortion detection device can be configured by a computer. The pattern distortion detection method can be performed by recording the process as a computer program on a computer-readable recording medium and causing the computer to execute the calculation.
In this case, in one aspect of the present invention, the following is recorded as a program to be executed by a computer that is recorded on the program recording medium. That is, in the semiconductor manufacturing process, only the design layout pattern or the verification layout pattern, or the process of forming the design layout pattern or the verification layout pattern and the reference layout pattern data in the memory area, and the design layout pattern or the verification layout pattern The process of predicting the finished pattern, the process of polygonizing the outline of the finished forecast pattern, and the polygonal finished forecast pattern only, or the polygonal finished forecast pattern and the design layout pattern or reference layout pattern An input and a process of detecting pattern distortion of the predicted finished pattern by a graphic operation process of the input data is recorded as a program.
According to such a pattern distortion detection apparatus, detection method, or program recording medium, it is possible to accurately detect the pattern distortion of a predicted finished pattern with high accuracy calculated using optical intensity simulation or the like.

The pattern distortion detection apparatus and detection method of the present invention described in the above embodiments are effectively used for manufacturing a semiconductor device.
In the semiconductor manufacturing process, many patterns are formed by an optical lithography technique or the like. There are also many pattern formation processes such as etching. In many of these pattern formation processes, the above-described pattern strain detection apparatus and detection method can be used to accurately form ultrafine patterns. In addition, a semiconductor device in which a fine pattern with little distortion is formed can be obtained by such a manufacturing process.

1 design layout pattern data holding unit,
1a Reference layout pattern data holding unit,
1b Verification layout pattern data holding unit,
2 Finish pattern prediction means,
3 Polygonizing means for the predicted pattern contour of the finish,
4 Vertex reduction means,
5 Finishing prediction pattern data holding unit,
6 inspection reference pattern creation means,
7 Reference pattern data holding unit for inspection,
8 pattern distortion detection means,
9 pattern distortion information holding unit,
10 pattern formation process condition holding unit,
11 pattern distortion amount calculation means,
12 pattern distortion amount display means,
13 pattern distortion information selection condition holding unit,
14 pattern distortion information selection means,
15 error information holding unit,
16 Contrast verification condition holding unit,
17 contrast information detection means,
18 Contrast information holding unit,
19 First high precision finished pattern prediction means,
20 first finished pattern prediction specification holding unit,
21 1st high precision finishing prediction pattern data holding part,
22 2nd high precision finishing pattern prediction means,
23 second finish pattern prediction specification holding unit,
24 2nd high precision finishing prediction pattern data holding part,
25 Finished pattern comparison means,
26 finish prediction pattern data comparison specification holding unit,
27 Finish pattern difference information holding unit,
31, 61, 71, 101, 111, 121, 141, 201, 301, 321 design layout pattern,
40, 50, 80, 90, 181, 361, 362, 363, 371, 372, 373, 401, 411, 441, 451 Finish prediction pattern,
62, 72, 102, 112, 122, 132 rectangle,
63, 83, 103, 113, 123, 143 Lower limit inspection reference pattern,
73,93 Reference pattern for upper limit inspection,
124 minute step,
125 Midpoint of the step,
141c Corner part,
171 verification layout pattern,
421,461 Difference calculation pattern,
471 Undersizing pattern.

Claims (4)

Finished pattern predicting means for predicting a finished pattern based on a design layout pattern or verification layout pattern in a semiconductor manufacturing process, finished predicted pattern polygonalizing means for polygonizing the contour of the finished predicted pattern, and the designed layout pattern or The inspection reference pattern generation means for generating the inspection reference pattern based on the reference layout pattern, and the pattern distortion of the finished pattern is detected by comparing the polygonal finished prediction pattern and the inspection reference pattern. Pattern distortion detecting means,
Dimensions for obtaining a plurality of finished predicted patterns by the finished pattern predicting means for a plurality of optical conditions and / or a plurality of pattern forming process conditions, and obtaining a dimensional variation width of the finished predicted pattern from the difference between the plurality of finished predicted patterns A pattern distortion detecting apparatus comprising a fluctuation range detecting means.   The dimension variation width detecting means performs a difference calculation between the plurality of predicted finished patterns, and performs a specified amount of undersizing on the obtained figure, thereby detecting a portion having a large dimensional variation in the predicted finished pattern. The pattern distortion detection apparatus according to claim 1. A step of predicting a finished pattern based on a design layout pattern or a verification layout pattern in a semiconductor manufacturing process, a step of polygonizing the outline of the finished predicted pattern, and a reference for inspection based on the design layout pattern or the reference layout pattern and creating a pattern, and detecting a pattern distortion of the predicted finished patterns by comparing the polygonal formulated has been finished predicted pattern and the test reference pattern,
With respect to a plurality of optical conditions and / or a plurality of pattern formation process conditions, a plurality of finished predicted patterns are obtained by the step of predicting the finished pattern, and the size variation width of the finished predicted pattern is determined from the difference between the plurality of finished predicted patterns. A pattern distortion detection method comprising the step of:   In the step of obtaining the dimension fluctuation range, a difference calculation is performed between the plurality of predicted finished patterns, and a predetermined amount of undersizing is performed on the obtained figure, thereby detecting a large dimension fluctuation part of the finished predicted pattern. The pattern distortion detection method according to claim 3, wherein:

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