JP3109631B2 - Photolithography pattern verification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern verification method for detecting a pattern defect of a resist formed on a wafer surface in a photolithography process in semiconductor manufacturing.

[0002]

2. Description of the Related Art In photolithography, a pattern is formed on a photosensitive composition by projecting the pattern on a photosensitive composition by irradiating exposure light to a reticle mask on which the pattern is formed, and then performing a developing process. To form. This photolithography is frequently used in a semiconductor manufacturing process as a method for forming a pattern on a resist on a wafer surface.

In the semiconductor manufacturing process, the same resist pattern is obtained by repeating the reticle mask using a stepper at the time of exposure.
For example, when exposure is performed as described above using a reticle mask A, a repeated image of shot A is obtained on the wafer surface as shown in FIG. Then, since fine processing such as etching is performed on the wafer surface using the resist pattern obtained as described above as a mask, high precision is required for the shape of the pattern formed on the resist.

Therefore, verification of the formed pattern is indispensable, and pattern verification using a wafer inspection machine is performed. The wafer inspection machine detects a difference between the patterns by comparing the shapes of the patterns, and the verification of the pattern using the wafer inspection machine has been performed as follows. First, the shape of the pattern formed in each shot is compared by the above-described wafer inspection machine, and a shot having a pattern having a different shape is found. Next, it is checked whether the size of the found irregular pattern, for example, the pattern is within the control limit. If it is within the management limit, it is determined that the pattern is normal, and if it is outside the management limit, it is determined that the pattern is defective.

[0005] By the above-described method, it is possible to find a defect in a pattern generated in a specific shot due to, for example, adhesion of a foreign substance to a wafer surface.

[0006]

However, the above-described pattern verification method has the following problems. That is, the surface of the wafer to which the resist is applied is not always uniform, and a difference in material and a step structure are caused by the formation of a wiring pattern and an interlayer film. For this reason, for example, in a step portion, the deviation of the focal position is enlarged, and in a portion made of a different material, the exposure energy changes due to a difference in the reflectance of the exposure light.

In photolithography, a pattern formed on a resist has a dimensional deviation or a defect due to an excess or deficiency of exposure energy or a shift of a focal position at the time of exposure. For example, when using a positive resist, if the exposure energy is insufficient, the pattern size will be enlarged,
As shown in FIG. 3B, the resist remains between the patterns and a short circuit occurs in the pattern. If the exposure energy is excessive, the pattern size is reduced,
As shown in (3), pattern loss occurs.

[0008] Pattern defects due to such causes also occur at the same place on all shots on the wafer surface. Therefore, the pattern defect cannot be recognized by the above-described pattern verification method by comparing images between shots. Therefore, a wafer having the same pattern defect in all shots as described above is regarded as a normal product and commercialized, and a failure occurs in a reliability test or a market.

Accordingly, an object of the present invention is to provide a pattern verification method capable of recognizing a pattern defect caused by a surface structure of a wafer, thereby improving the reliability of a semiconductor product.

[0010]

In order to solve the above-mentioned problems, a pattern verification method according to the present invention comprises the steps of forming a plurality of simulation patterns on a resist formed on a wafer surface; Comparing each of the simulation patterns and detecting whether or not the difference between the respective simulation patterns is within the range of the control limit. In particular, in the first invention, a plurality of simulation patterns in which the exposure energy is changed within a range in which a pattern having the upper limit of the management and the lower limit of the management are formed, and the focal position is changed within a range in which the pattern dimension does not change. To form Further, in the second invention, a reference pattern exposed with an appropriate exposure energy and an appropriate focus position and a pattern having an upper limit of control and a lower limit of control are formed on the resist formed on the wafer surface. A plurality of simulation patterns are formed in which the exposure energy is changed within a certain range and the focal position is changed within a range in which a change in pattern dimension does not appear. Then, the simulation pattern is compared with the reference pattern, and it is detected whether or not the difference of the pattern due to the comparison is within the management limit.

[0011]

According to the pattern verification method of the first and second aspects of the present invention, the exposure energy is changed within the range of the control limit, and the focal position is changed within the range where the pattern dimension does not change. Is formed on the wafer. Therefore, if the surface condition of the wafer is uniform, the dimensions of these simulation patterns fall within the control limits. On the other hand, when the surface state of the wafer is not uniform and a difference in material or a step structure occurs, the exposure energy exceeds the range of the control limit due to these influences, and the shift of the focal position is enlarged. Among the plurality of simulation patterns, those exceeding the range of the management limit are formed. Therefore, these simulation patterns (and reference patterns)
Compare the simulation pattern differences,
By detecting whether the difference between each simulation pattern and the reference pattern is within the control limit,
The occurrence of a defect in the resist pattern due to the surface state of the wafer is predicted.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. First, FIG. 1A shows an example of a verification wafer 1 used for pattern verification according to the present invention. Verification wafer 1
Is a product wafer extracted from the verification process, and a simulation pattern is formed on a resist applied to the wafer surface as in the product process. This simulation pattern is formed of a plurality of shots obtained by repeating a reticle mask similar to that of a product manufacturing process, and each shot is given different exposure conditions using exposure energy and a focal position as factors.

The exposure energy, which is one of the factors of the above-mentioned exposure conditions, includes an exposure energy m for forming a pattern having a target size on the resist and a pattern having an upper limit and a lower limit for control with respect to the target size. Exposure energies g and s are adopted. For example, in the case of using a positive resist, assuming that a pattern having a target size can be obtained with an appropriate exposure energy m, the pattern width becomes wider with a smaller exposure energy and becomes smaller with a larger exposure energy.

Each of the above exposure energies is obtained as follows. First, as shown in FIG. 1 (2), a pattern in which the exposure energy of each of the shots a to y on the wafer surface is stepwise changed while the focus position is kept at the sharp focus. At this time, the wafer 2 is replaced with the verification wafer 1 described above.
The same wafer 2 is used. Then, each shot a to y
Is measured with a scanning electron microscope. Then, an exposure energy g for obtaining a control upper limit of the pattern dimension, an exposure energy m for obtaining a target dimension, and an exposure energy s for obtaining a control lower limit are obtained.

The focus position, which is another factor of the exposure conditions, is a position 0 at which the focus becomes a just focus, and an upper limit position + which may cause a deviation in a normal exposure process.
Adopt three values of α and the lower limit position −α. As shown in FIG. 2, when the focal position is shifted by a certain value or more from the position at which just focus can be obtained at the time of exposure, the pattern size formed in the resist changes. Is included in the range that does not appear.

Exposure is performed under the above exposure conditions, and a simulation pattern is formed on each shot on the surface of the verification wafer 1. As shown in FIG. 1A, the exposure energy of a row of shots formed on the wafer surface is changed from the top to g, s, and m. And the columns of shots are
From the left, the focal position changes to -α, 0, + α.

The pattern formed on each shot under the respective exposure conditions is as follows. First, the shot was exposed at the focus position 0 at which the optimum exposure energy m and just focus were obtained, so that the simulation pattern of the target size (so-called reference pattern) was used.
) Is formed. Next, since the shot was exposed with a small exposure energy g and a focal position ± α , a simulation pattern exceeding the target size was formed in the case of a positive resist. Since the shot was exposed with a large amount of exposure energy s and a focal position ± α , the simulation pattern of the control lower limit below the target dimension for a positive resist was used.
Over emissions are formed.

Next, pattern verification is performed using the verification wafer 1 on which the simulation pattern is formed as described above. For the pattern verification, a simulation pattern formed on a shot of the verification wafer 1 and a simulation pattern formed on the shots,. The wafer inspection apparatus detects a difference between the patterns by comparing the shapes of the patterns. Since each of the simulation patterns is formed under a specific exposure condition, the dimensions of the patterns are also different.
Therefore, in the above wafer inspection machine, a difference between the shots and the simulation patterns of the shots,.

Then, it is confirmed whether or not the difference between the detected simulation patterns is within the control limit.
Here, since each exposure condition of each shot to is within the range of the control limit, the verification wafer 1 for forming a pattern is exposed.
If the surface state is uniform, the difference between the detected simulation patterns also falls within the management limit. Therefore, if the difference between the simulation patterns is within the range of the control limit, it is determined that no defect of the resist pattern due to the surface state of the wafer occurs in the step of extracting the verification wafer 1.

On the other hand, a verification wafer 1 for forming a pattern
If the surface condition is not uniform and there is a difference in material or a stepped structure due to the formation of wiring patterns or interlayer films, etc., the deviation of the focal position is increased in the stepped portion, and in the portion with different material, The exposure energy changes depending on the difference in the reflectance of the exposure light. For this reason, if an extreme difference in material or a step structure occurs in the surface state of the verification wafer 1, the simulation pattern formed on the shots,.
Therefore, if the difference between the simulation pattern formed on the shot and the simulation pattern formed on the shots,... Exceeds the range of the control limit, in the step of extracting the verification wafer 1, It is determined that a defect of the resist pattern due to the state occurs.

In the above embodiment, the exposure energy and the focal position, which are factors of the exposure condition of the verification wafer 1, are set in three stages, but the present invention is not limited to this. For example, as in a verification wafer 2 shown in FIG.
Exposure energy and focus, which are factors of exposure conditions
The position can be set to 5 levels, or set to more levels
You may.

[0022]

As described above, according to the pattern verification method of photolithography of the present invention, the presence or absence of a pattern defect caused by the surface structure of a wafer is determined.
Judge and predict. Therefore, it is possible to prevent a defective product from appearing on the market and the like, and it is expected that the reliability of the product is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a wafer for pattern verification.

FIG. 2 is a graph showing a pattern dimension deviation of a resist depending on a focal position.

FIG. 3 is a diagram illustrating a pattern defect of a resist depending on exposure conditions.

[Explanation of symbols]

 1 Verification wafer (wafer)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 7/20 521 H01L 21/66

Claims (2)

(57) [Claims] An exposure energy is changed for a resist formed on a wafer surface within a range in which a pattern having an upper limit of control and a lower limit of control is formed, and a change in pattern dimension does not appear. Forming a plurality of simulation patterns with different focal positions, comparing each of the plurality of simulation patterns,
Detecting whether or not the difference between the simulation patterns is within a management limit. 2. A range in which a resist formed on a wafer surface is formed with a reference pattern exposed with an appropriate exposure energy and an appropriate focus position, and a pattern having upper and lower management limits. Forming a plurality of simulation patterns in which the focal position has been changed within a range in which the change in pattern size does not appear while changing the exposure energy, and comparing the simulation patterns with the reference pattern; Detecting whether the difference is within a control limit or not.