JPS63278474A - Image pickup device - Google Patents

Abstract

PURPOSE:To eliminate excessive sensitivity control by affecting the decided result of an output signal corresponding to a sensitivity control quantity on the next sensitivity control operation, by forming the address designation information of a second scanning circuit by referring to the readout signal of a solid-state image pickup device and a reference signal corresponding to a prescribed diaphragm quantity. CONSTITUTION:The sensitivity control operation in which the address designation information of the second scanning circuit 1TGE is formed by using the solid-state image pickup device MID including a first scanning circuit 1TG which outputs the signals of plural picture element cells arranged two-dimensionally by an interlace system in time series and the second scanning circuit 1TGE which performs a selection operation in a vertical scanning direction by the interlace system by an address independent from a selection address in the vertical scanning direction by the first scanning circuit 1TG, and referring to the readout signal of the solid-state image pickup device and the reference signal corresponding to the prescribed diaphragm quantity is performed at a rate of one time of operation per plural frames. In such a way, it is possible to affect the decided result of the output signal corresponding to the sensitivity control quantity on the next sensitivity control operation, and to prevent the sensitivity control from being performed excessively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an imaging device. For example, a pixel signal formed by a photoelectric conversion element is extracted via a MOSFET (insulated gate field effect transistor),
The present invention relates to a technique that is effective for use in solid-state imaging devices that have a function of making the sensitivity variable.

[Conventional technology]

2. Description of the Related Art Solid-state imaging devices consisting of a combination of a photodiode and a switch MO3FET are conventionally known. Regarding such a solid-state imaging device, for example, Japanese Patent Application Laid-Open No. 56-1
There is a publication No. 52382.

In a television camera for surveillance or home use that uses the above solid-state imaging device, an automatic aperture mechanism is provided in the optical lens.

[1. Problems to be Solved by the Invention] The lens of the automatic diaphragm mechanism requires relatively complicated mechanical parts, which causes the lens section of the television camera to become larger and more expensive. . Further, since the automatic throttle mechanism is composed of relatively complicated mechanical parts, there is a problem in reliability due to wear of the mechanical parts.

An object of the present invention is to provide an imaging device that realizes a stable and highly accurate electronic automatic diaphragm.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a first scanning circuit that outputs signals of a plurality of pixel cells arranged in a two-dimensional manner in time series in an interlaced manner, and an address that is independent of the selected address in the vertical scanning direction by the first scanning circuit. Using a solid-state imaging device including a second scanning circuit that performs a vertical scanning direction selection operation in an incremental method based on an address, a readout signal of the solid-state imaging device and a reference signal corresponding to a predetermined aperture amount are referred to. The sensitivity control operation of forming addressing information for the second scanning circuit is performed at a rate of once every frame or once every plural frames.

[For production]

According to the above-mentioned means, the sensitivity setting operation is performed at a rate of once per frame or once every multiple frames, so the determination result of the output signal according to the sensitivity control amount can be reflected in the next sensitivity control operation. As a result of preventing excessive sensitivity control, stable and highly accurate electronic automatic diaphragm operation can be realized.

〔Example〕

FIG. 3 shows a transversal signal L (TS L) having a sensitivity variable function used in the present invention.
A circuit diagram of a main part of an embodiment of a solid-state imaging device of the ine) type is shown. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques. The main blocks in the figure are drawn according to the geometric arrangement in an actual semiconductor integrated circuit device.

The pixel array PD is exemplarily shown with four rows and two columns. However, in order to prevent the drawing from becoming complicated, circuit symbols are added to only two of the four rows of pixel cells. One pixel cell is
A switch MO3FETQI whose gate is coupled to the photodiode D1 and the vertical scanning line vL1, and a switch MO3FETQI whose gate is coupled to the horizontal scanning line HLI.
It consists of a series circuit of F and Ta2. Above photodiode)'DI and switch MO3FETQI,Q
The output nodes of other similar pixel cells (D2.Q3.Q4) arranged in the same row (horizontal direction) as the pixel cell consisting of D2, D2, Q3, Q4, etc.
1. Pixel cells similar to those described above are similarly combined for other rows.

The exemplified horizontal scanning line HLI extends vertically in the figure, and includes switches MO3FETQ2 . It is commonly coupled to gates such as Q6. Pixel cells arranged in other columns are also coupled to the corresponding horizontal scanning IHL2 etc. in the same manner as described above.

In this embodiment, in order to add a substantial electronic automatic aperture function to the solid-state imaging device, in other words, to make the substantial accumulation time for the photodiode variable, the horizontal A switch MO3FETQ is installed at both ends of the signal lines H3I to H84, etc.
8, Q9 and Q26, Q28 are provided. The switches MO3FETQ8 and Q9 arranged on the right end side connect the horizontal signal lines H31 and H32 to the output line S extending in the vertical direction, respectively. This output line vS is the terminal S
The readout signal is transmitted via this terminal S to the input of an externally provided preamplifier. In addition, the above switches MO3FETQ26 and Q2 arranged on the left end side
8 connects the horizontal signal lines H3I, )(S2) to dummy (reset) output lines DVS extending in the vertical direction.

This output line DVS is coupled to the terminal RV, although not particularly limited thereto. With this, if necessary, the above dummy output line D
The VS signal can be sent from the external terminal RV.

In this embodiment, although not particularly limited, the horizontal signal lines H3I to H34 in each row are provided with switches MO3FETQ27, Q29, etc. that are turned on by a reset signal supplied from the terminal RP during the horizontal retrace period. Due to the ON state of these MO3FETs Q27, Q29, etc., the above dummy output line DV is connected from the external terminal RV.
A constant bias voltage (not shown) is applied to each horizontal signal wAH81 to H34 via S. The reason why the reset MO3FETs Q27, Q29, etc. as described above are provided is as follows. Horizontal signal above! l! ! lH
Semiconductor regions such as the drains of switch MO3FETs coupled to 81 to H34 may also be photosensitive, and false signals (smear, blooming) formed by such parasitic photodiodes may be left floating when not selected. is accumulated on the horizontal signal line. Therefore, in this embodiment, all the horizontal signal lines H3I to H34 are reset to the predetermined bias voltage by using the horizontal retrace period as described above. As a result, since pixel signals are always extracted from the selected horizontal signal line in a state in which the false signals have been reset, false signals contained in the image signals to be outputted can be significantly reduced.

Note that the above-mentioned false signals (smear, pluming) are described in detail in, for example, Japanese Patent Laid-Open No. 17276/1983.

A horizontal scanning signal formed by a horizontal shift register H3R is supplied to the horizontal scanning lines HLI to HL2, etc.

The scanning circuit that performs the vertical selection operation (horizontal scanning operation) in the pixel array PD is composed of the following circuits.

In this embodiment, the horizontal signal line H3 of the pixel array PD
A pair of switches MO3FE are installed at both ends of I to H34, etc.
', TQ8, Q9 etc. and switch MO3FETQ26,
A pair of scanning circuits are provided corresponding to the provision of Q28 and the like.

In this embodiment, in order to be applicable to industrial applications, in addition to the interlace mode, selective two-line simultaneous scanning and non-inclace mode scanning are enabled. The following scanning circuit is provided on the right side of the pixel array PD.

The vertical shift register VSR forms output signals Sv1, SV2, etc. used for reading. These output signals SV1, SV2, etc. are output to the increment gate circuit ITG.
and the vertical scanning %lL1 to VL4 and the switches MO3FETQ8 . It is supplied to gates such as Q9.

Since the increment gate circuit TTG performs a vertical selection operation (horizontal scanning operation) in the interlace mode, in the first (odd number) field, the vertical scanning lines VLI to VL4 are connected to the adjacent vertical scanning lines 491VLiVI, 2. VI and 3 are selected simultaneously. That is, the vertical shift register VS is controlled by the switch MO5FETQI8 which is controlled by the odd field signal FA
The R output signal Svi is output to the vertical scanning line VLI that selects the horizontal signal line H3I. Similarly, by the switches MO3FETQ20 and Q22 controlled by the signal FA, the output signal SV2 of the vertical shift register VSR is
It is output to vertical scanning lines VL2 and VL3 to simultaneously select horizontal signal lines H32 and HS3.

Thereafter, selection signals for a pair of horizontal signal lines consisting of combinations in the same order are formed.

In addition, in the second (even numbered) field, the vertical scanning line VLI
to VL4, adjacent vertical scanning lines VLI and VL2
and VL3 and vL4 are selected simultaneously. That is, M? by the even field signal FB? Il
The MO8FETs Q19 and Q21 allow
The output signal SVI of the vertical shift register SR is a vertical scanning IVLI that selects the horizontal signal &ff) fsl and H82.
is output to VL2. Similarly, the switches Mo S F E'I' Q 23 and Q controlled by the signal FB
25, the output signal S of the vertical shift register VSR
V2 is output to vertical scanning lines VL3 and VL4 to simultaneously select horizontal signal lines H33 and H34. Thereafter, selection signals for a pair of horizontal signal lines consisting of combinations in the same order are formed.

The increment gate circuit ITG as described above and the following drive circuit DV realize a plurality of types of horizontal scanning operations as described below.

The output signal from the interlaced gate circuit ITG corresponding to the one vertical scanning line VLI is transmitted to the switch MO3F.
Supplied to the gates of ETQ14 and Q15. The common drain electrodes of switch MO3FETs Q14 and Q15 are also coupled to terminal V3. Above switch MO
S F ETQ 14 supplies the signal supplied from terminal v3 to the vertical scanning line VLI. Also, switch M
The O3FETQ15 is supplied with the signal supplied from the terminal v3 to the gate of a switch MO3FETQ8 that couples the horizontal signal line H3I to the output line VS.

Also, the high level of the output signal is the switch MO3FETQ
14. In order to prevent the threshold voltage from decreasing by the threshold voltage due to Q15, although not particularly limited, MO3FET
A capacitor C1 is provided between the gate of QI4 and the output side (source side) of MO3FETQ15. As a result, when the output signal from the increase gate circuit ITG is set to a high level, the potential of the terminal v3 is set to a low level and the capacitor C1 is precharged.

After this, when the potential of the terminal v3 is set to high level, the above-mentioned MO
The gate voltage of 5FET QI4 and Q15 can be boosted.

The output signal from the incremental gate circuit ITG corresponding to the vertical scanning line VL2 adjacent to the vertical scanning line VLI is supplied to the gates of the switches MO3FETs QI6 and Q17. The common drain electrodes of these switches MO3FET QI 6 and Q17 are coupled to terminal v4. The above switch MO3FETQ16 has a terminal v4
A signal supplied from the vertical scanning line VL2 is supplied to the vertical scanning line VL2. The switch MO8FETQ17 is supplied to the gate of the switch MO3FETQ9 which couples the signal supplied from the terminal v4 to the horizontal signal line H32 to the output line VS.

The high level of the output signal is the switch MO3FETQ16,
In order to prevent the threshold voltage from decreasing by the threshold voltage due to Q17, MO3FET QI
A capacitor C2 is provided between the gate of MO3FET QI 6 and the output side (source side) of MO3FET QI 7. As a result, by changing the potential of the terminal v4 at the same timing as described above, the gate voltages of the MO3FIF, TQ16, and Q16 can be boosted by the bootstrap action of the capacitor C2.

The above terminal v3 is an odd-numbered vertical scanning line (horizontal signal line)
Terminal 4 is provided in common for the drive switch MO3FET corresponding to the 2nd terminal, and the terminal 4 is provided in common for even-numbered vertical scanning NIAs (horizontal signal lines).

As can be understood from the above, the reading operation in the incremental mode is performed by selectively supplying the timing signal to the terminals 3 and v4 and the simultaneous selection of two rows by the interlace gate circuit ITG. becomes possible. For example, in an odd B field in which the terminal FA is set to a high level, by keeping the terminal v4 at a low level and supplying a timing signal synchronized with the operation of the vertical shift register VSR to the terminal v3,
Vertical scanning key (horizontal signal line) to VLI (H31), V
L 3 (H33) No JIIi can be selected. In addition, in an even field in which the terminal FB is set to high level, the vertical scanning line (
horizontal signal line) to VL2 (H32), VL4 (H3
4) can be selected in this order.

On the other hand, if the terminals v3 and {circle around (2)} are simultaneously set to high level in the same manner as described above, two rows can be simultaneously scanned in accordance with the output signal from the interlace gate circuit ITG.

In this case, as mentioned above, two field signals FA and F
By shifting the combination of two lines outputted every two screens by B up and down by one line, the spatial center of gravity is shifted up and down, in other words, an equivalent increase mode is realized.

Furthermore, for example, by setting only the terminal FB to a high level, the horizontal shift register H3R is set to 2 at one vertical scanning timing.
By making the terminals v3 and v4 go high level in synchronization with the operation, VLI, VL2 . VL3.
It is possible to realize the selection operation in the Ninon interlace mode as in the order of VI and 4.

In this case, in order to achieve higher image quality, it is desirable that the clocks supplied to the horizontal shift register (SR) and the vertical shift register VSR be doubled in frequency, i.e., terminals H1 and H2 and terminals v1 and v2. By doubling the frequency of the clock signal supplied to the horizontal shift register H3R and vertical shift register VSR from the terminal, it is possible to read out 60 images per second in a non-interlaced manner. HIN
and VIN are terminals that supply input signals to be shifted by the shift registers H3R and VSR, respectively, and the shift operation is started from the time the input signals are supplied. Therefore, the increase gate circuit TTG and the input terminal V3. When performing the above-mentioned two-row simultaneous readout, interlace scanning, non-inclace scanning, etc. by combining the human input signals supplied to V4, the shift register VSR is adjusted so that the vertical relationship of the output signals is not reversed. Timing considerations need to be taken into consideration when supplying input signals.

Furthermore, reset MOS FETs QIO and Qll are provided between the gates of the vertical scanning lines VLI and the corresponding switches MO3FETQ8 and the ground potential point of the circuit. These reset MO3FETs QIO and Qll receive a clock signal supplied from the terminal v2 in common with the reset MO3FETs provided corresponding to other vertical scanning lines and switch MO3FETs, and reset the vertical scanning line in the selected state. And the gate potential of the switch MO3FET is pulled out to a low level at high speed.

In this embodiment, in order to add a sensitivity variable function as described above, a vertical shift register V S RE for sensitivity control is used.
, interlace gate circuit ITGE and drive circuit DVE
is provided. Each of these sensitivity control circuits is arranged on the left side with respect to the pixel array PD, although it is not particularly limited. These vertical shift register VSRE, interlaced gate circuit ITG, and drive circuit DVE are constituted by circuits similar to the above-described vertical shift register VSR for reading, incremented gate circuit ITG, and drive circuit DV. Terminal V IF, or V4R and VTN
Timing signals similar to those described above are supplied from E, FAF, and ABE, respectively. In this case, in order to perform a shift operation at a synchronized timing between the vertical shift register for readout [no register VSR] and the vertical shift register VSRE for variable sensitivity, the terminal VI
The same clock signal is supplied to E and vl and V2E and v2. Therefore, the above terminals VIE, Vl and V2
E and (2) may be shared by an internal circuit. The reason why the unique terminals vIE and V2E are provided as described above is to enable this solid-state imaging device to be applied to a television camera having a manual aperture function or a conventional mechanical aperture function. When variable sensitivity operation is not performed in this way, wasteful power consumption of the vertical shift register VSRE can be avoided by setting the terminals VIF and V2E to a low level similar to the ground potential of the circuit. This is taken into consideration.

Next, the sensitivity control operation in the solid-state imaging device of this embodiment will be explained.

To simplify the explanation, the vertical scanning operation in the non-interlaced mode will be taken as an example. , the fourth row (vertical scanning line Perform the selection operation of VL4 and horizontal signal line 1 (34).As a result,
Horizontal scanning line HL1. formed by horizontal shift register H3R. In synchronization with the selection operation of H1, 2, etc., the output signal 's V S is the photodiode D in the first row.
1, the optical signals accumulated in D2, etc. are read out in time series. This read operation is performed by supplying a current corresponding to the optical signal from the terminal S through the load resistor, and a precharge (reset) operation is performed simultaneously with the read operation. A similar operation is performed for the photodiodes in the fourth row. In this case, the readout operation at the beginning of the fourth row is performed by the scanning circuit for variable sensitivity (VSRE, ITGE, r)VB) as described above, using the dummy output line DVS.
It is done for. When only the sensitivity control operation is performed, the same bias voltage as the terminal S is applied to the terminal RV.

As a result, the optical signals already accumulated in each pixel cell in the fourth row are swept out, or in other words, a reset operation is performed.

Therefore, by the above vertical scanning operation, the vertical shift register VSR for reading and the increase gate circuit I
The fourth row (vertical scanning line VL) by TG and drive circuit DV
4. The readout operation of the horizontal signal line H34) is performed after the readout operations of the first to third rows, so the fourth
The storage time of the photodiode of the pixel cell arranged in the row is the readout time of the pixel cells of three rows.

In place of the above, vertical shift register VSR for sensitivity control
E. Interlace gate circuit rTGE and drive circuit D
Vertical shift register VS for reading by VE
R, Increment gate circuit ■First line by TG and drive circuit DV (vertical scan %1VL1, horizontal signal vA) (
31), the second row (vertical scanning line V
L2, horizontal signal line H32) is selected. As a result, in synchronization with the selection operation of the horizontal scanning lines HLI, HL2, etc. formed by the horizontal shift register H3R, the output signal FJAvS includes the optical signals accumulated in the photodiodes D1, D2, etc. in the first row. Read out serially. This read operation is performed from terminal S to 'v1. This is done by supplying a current corresponding to the above optical signal that has the total resistance of the load resistance, and precharges (resets) at the same time as the read operation.
An action is taken. A similar operation is performed in the photodiodes D3, D4, etc. in the second row. As a result, in parallel with the readout operation of the first row, the operation of sweeping out the M optical signals already accumulated in each pixel cell of the second row is performed. Therefore, by the above vertical scanning operation,
The readout operation of the second row (vertical scanning line VL2, horizontal signal line H82) by the readout vertical shift register VSR, increase gate circuit ITG, and drive circuit DV is performed after the readout operation of the first row. , second
The storage time of the photodiode of the pixel cell arranged in the row is the readout time of the pixel cell for one row. As a result, compared to the above case, the actual storage time of the photodiode can be reduced to 1/3, or in other words, the sensitivity can be lowered to 1/3.

As mentioned above, the pixel cells in that row are reset by the preceding vertical scanning operation performed by the scanning circuit for sensitivity control, so the actual reading by the scanning circuit for reading is performed from the recent operation. The time up to this point is taken as the storage time for the photodiode. Therefore, in a pixel array consisting of 525 rows, the readout time for one row is up to 525 rows per unit (minimum) due to the different addressing by both vertical scanning circuits and the pixel cell selection operation by the common horizontal scanning circuit. In other words, the sensitivity can be set over 525 stages. However, it is assumed that the change in the light-receiving surface illuminance can be ignored with respect to the scanning time constituting one screen, and that substantially constant light is incident on the photodiode. The maximum sensitivity (525) is
The scanning circuit for sensitivity control is obtained in a non-operating state.

In the sensitivity control operation as described above, reading out pixel signals and resetting operation by the preceding vertical scanning operation are performed in parallel. Therefore, a pixel signal for a reset operation may be mixed with a readout signal due to capacitive coupling via the substrate or the like. When such capacitive coupling occurs, there is a possibility that ghost-like noise in a television receiver may occur in the read pixel signal, degrading the image quality.

Therefore, in this embodiment, external terminals s are connected to the horizontal scanning lines HLI, IL2, etc. via diode-connected MO3FETQ30.
Adds a function to forcibly select all horizontal scanning lines from p. That is, when the terminal SP is set to a high level, the diode-type MO3FETs Q30, Q31, etc. are all turned on, and all horizontal scanning lines 1 (Ll, HL2, etc.) are set to a high level, regardless of the operation of the horizontal shift register (ISR). It can be supplied and put into the selected state.

Also, MO3FETQ30゜Q3 in the above diode form
Since the selection level is supplied through a unidirectional element such as MO3FETQ30.degree. As a result, even if the forcible simultaneous selection circuit as described above is provided, the horizontal scanning lines HLI, HL2, etc., according to the shift operation of the horizontal shift register H3R, are prevented from being brought to the selection level in time series. However, since the horizontal shift register H3R is configured with a dynamic circuit, the shift operation may be adversely affected by the selection level of the FA-like horizontal scanning line f (Ll, HL2, etc.) as described above. If this occurs, a switch circuit or the like is added to prevent the selection level from being transmitted to the inside of the horizontal shift register H3R.

The horizontal scanning line HL1. Simultaneous selection operations such as HL2 are performed during the horizontal retrace period as will be described later, and the preceding vertical scanning is started.

Thereby, the signals of all pixels in the row to be reset can be forcibly reset in advance. Therefore, when reading pixel signals in accordance with the horizontal scanning line selection operation by the horizontal shift register HSR, substantially no pixel signals are output from the preceding row. As a result, even if there is capacitive coupling via the substrate or the like, the above-mentioned noise does not appear in the read signal.

FIG. 1 shows a block diagram of an embodiment of an imaging device using the solid-state imaging device described above and having an automatic aperture function.

The solid-state imaging device MID has a variable sensitivity function as shown in FIG. 1 above. The readout signal output from this solid-state imaging device MTD is amplified by a preamplifier. This amplified signal Vout is supplied to a signal processing circuit (not shown) on the one hand, and is used as, for example, an image signal for television. The amplified signal Vout is used on the other hand for automatic aperture control. That is, the amplified signal Vout is passed through the low pass filter LPF and the detection circuit D.
It is converted to an average DC level by a smoothing circuit consisting of an ET. This DC level VD is determined by the voltage comparator circuit COMP.
is supplied to one input (+) of the

A reference voltage Vref for setting sensitivity is supplied to the other input (-) of the voltage comparison circuit COMP.

The output signal formed by the voltage comparison circuit COMP is supplied to an up/down control terminal U/D of an up/down counter circuit C0UNT that constitutes a sensitivity control operation. The stitch number output signal of the counter 9COUNT is supplied to the control circuit C0NT. The control circuit C0NT decodes the count output signal and also outputs the solid-state imaging device MI.
In response to the signals VIN and vl etc. from the drive circuit which supplies clock signals for controlling the scanning timing as described above to D, the readout timing of the solid-state imaging bag ffM I is referred to and substantially precedes it. Forms the signal VINE. That is, since the preceding timing signal VINE corresponding to the required aperture amount (sensitivity) is formed based on the timing signal VIN, the signal VINE is actually formed after the timing signal VIN. .

However, since repeated scanning is performed, from the point of view of the above signal VINE, the signal V I
It is assumed that N' is delayed. In other words, if the timing signal VINE is generated with a delay of one line relative to the timing signal VIN, the timing signal VIN will be generated on the next scan screen.
E is regarded as a timing signal that precedes the timing signal VIN by 524 lines. The above timing signal V
By rN and VINE, each vertical shift register VS
Since the R and VSRE shift operations are started, the sensitivity variable operation as described above is performed. In this embodiment, the sensitivity setting operation described above is performed once every l frame. For this reason, the timing signal CK supplied from the drive circuit is used. That is, this timing signal is, for example, a vertical synchronization timing signal between an odd field and an even field for a read operation.

Thereby, the counter circuit C0UNT performs a two-step counting operation of up or down according to the output of the voltage comparison output COMP using the timing signal as an input pulse. Therefore, the actual sensitivity setting operation by the control circuit C0NT is performed once every frame.

The reason why the sensitivity setting operation is performed once per frame is as follows.

For example, it is also possible to perform the sensitivity setting operation for each odd/even field. However, in this case, as shown in FIG. 4, flicker is likely to occur due to excessive sensitivity setting near the appropriate control amount.

For example, depending on the low level of the output signal of the voltage comparison circuit COMP, the sensitivity control t6 is set high at the start of the field FAI. This sensitivity side result is the next field FB
Obtained by I. Therefore, in field FAI, an output smoothing level VD is obtained according to the previously set sensitivity WaS. At the start of the next field FBI, the smoothed output level V in the field FAI according to the sensitivity control amount 5 is
Since the output of the voltage comparison circuit COMP becomes high level from D, a control amount 5 is set, which is the sensitivity control amount lowered by a unit control amount.

However, the smoothed output level VD of this field FBI is controlled by sensitivity! i! 6 to a higher level.

In the field FA2 in the next frame, the smoothed output level VD in the field FBI corresponding to the sensitivity control f#5 is made higher than the reference voltage V ref in the same way as described above, so the sensitivity control amount 4 is further lowered by the unit control amount. Set. Furthermore, in the next field FB2, the smoothed output level VD of the field FA2 corresponding to the sensitivity control ¥4 is made higher than the reference voltage Vref, as described above.
More credit system? A sensitivity control amount 3 is set, which is lowered by an amount of 11. In this way, although the smoothed output level VD in field FB2 is already lower than the reference voltage Vref due to the sensitivity setting in field FA2, the smoothed output level VD in field FBI and the reference voltage Vre
Based on the comparison output with f, the sensitivity is excessively reduced as described above.

In the field FA3 in the next frame, the smoothed output level VD in the field FB2 corresponding to the sensitivity control amount 4 is lower than the reference voltage Vref as described above, so the sensitivity control amount 4 is increased by the unit control amount. In the next field FB3, the smoothed output level V of field FA3 corresponding to the sensitivity control 13 is set in the same way as above.
Since D is further lowered than the base fP voltage Vref, sensitivity control I5 is set to increase the control amount by about 1 yen. Then, as above, the next field (frame) F
In A4, the sensitivity control I amount is set even higher, such as 6.

As a result, when the appropriate control amount is between 4 and 5, the excessive control amount 6 or 3 is set. Therefore, the output signal Vout
(Smoothed output level VD) is sensitivity control amount 3 to 6.
There is a possibility that a level change may occur in response to the change, causing flicker.

On the other hand, in the method of setting the sensitivity only once per frame as in this embodiment, as shown in FIG. When the smoothed output level VD is made higher than the reference voltage Vref by setting the II amount 5, in response to this, the sensitivity is lowered by the unit mI view and the sensitivity control amount 4 is set.

This setting of the sensitivity control amount 4 is maintained for each frame (odd and even frames). Therefore, in the sensitivity setting operation in the next frame, is it a sensitivity control? Judgment result of smoothed output level VD corresponding to Dt4 and reference voltage Vref (C0
A sensitivity control amount 5 is set that is higher than the low level of the MP output by the unit weight loss mf#. As a result, for example, in the vicinity of the appropriate control amount where the reference voltage Vref exists between the sensitivity control amounts 4 and 5 as described above, the sensitivity control amount to be set can be a repetition of 4 and 5. . Therefore, the output signal Vout (smoothed output level VD)
However, flicker does not occur because only a minute level change corresponding to the unit sensitivity control amount changes.

Furthermore, in the imaging device of this embodiment, the sensitivity variable function is built into the solid-state imaging device MTD, and the sensitivity is electrically controlled by determining the level of the read output signal. Therefore, since the sensitivity control circuit can also be constructed from a semi-conductor integrated circuit or the like, the device can be made smaller, lighter and more durable.

The effects obtained from the above examples are as follows.

(A first scanning circuit that outputs the signals of a plurality of pixel cells arranged in one dimension in a time-series manner in an interlaced manner, and a Using a solid-state imaging device including a second scanning circuit that performs a vertical scanning direction selection operation in an incremental method based on an address, the readout signal of the solid-state imaging device and a reference signal corresponding to a predetermined aperture are referred to. 2nd above
By performing the sensitivity control operation of forming the address designation M% of the scanning circuit at a rate of once per frame or once per multiple frames, the determination result of the output signal according to the sensitivity control amount is reflected in the next sensitivity control operation. As a result, sensitivity control can be prevented from being performed excessively, resulting in the effect that stable and highly accurate electronic automatic diaphragm operation can be realized.

According to (2) and (11), when the sensitivity control circuit is constructed using a semiconductor integrated circuit device, the effect of simplifying the circuit can be obtained.

(3) According to (2) above, it is possible to provide an automatic aperture mechanism using an electronic circuit integrated in a semiconductor circuit without using a mechanical aperture mechanism in the lens. by this,
The effect is that a television camera compatible with the NTSC system and having an automatic aperture function can be made smaller and lighter.

(4) Since the sensitivity operation can be changed rapidly for each screen (one frame), it is possible to achieve the effect of enabling highly responsive automatic aperture control.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the sensitivity setting operation may be performed not only once per frame, but also once per two or more frames. The sensitivity setting circuit is read out in order to set the automatic diaphragm.
In addition to simply calculating the average value as described above, the configuration of the analog circuit that processes the Various embodiments can be adopted, such as one that calculates the difference between the two. The solid-state imaging device used in the imaging Wiff according to the present invention includes the above-mentioned M
In addition to O3 type solid-state imaging devices, the present invention can also be applied to devices using, for example, a CCD (charge! multi-conveying device). That is, a reset circuit is added that sweeps out the charge of the photodiode in the row preceding the row to be read, and this reset circuit is put into operation by a scanning circuit for sensitivity setting, and a sensitivity variable function is added. It may be something.

The present invention can be widely used in an imaging device using a fixed imaging device whose sensitivity is made variable by sweeping out the signals of the row preceding the row to be read as described above.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in Mokuban is as follows. That is, a first scanning circuit that outputs signals of a plurality of pixel cells arranged in a two-dimensional manner in time series in an interlaced manner, and an address that is independent of the selected address in the vertical scanning direction by the first scanning circuit. Using a solid-state imaging device including a second scanning circuit that performs a vertical scanning direction selection operation in an incremental method based on an address, a readout signal of the solid-state imaging device and a reference signal corresponding to a predetermined aperture amount are referred to. By performing the sensitivity control operation of forming addressing information for the second scanning circuit at a rate of once per frame or multiple frames J, the determination result of the output signal according to the sensitivity control operation is used for the next sensitivity control. Since the sensitivity can be reflected in the operation, excessive sensitivity control can be prevented, and as a result, stable and highly accurate electronic automatic aperture operation can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an imaging device having an automatic aperture function according to the present invention, FIG. 2 is a timing diagram for explaining its sensitivity setting operation, and FIG. FIG. 4 is a factorial circuit diagram showing one embodiment of the solid-state imaging device used, and is a timing diagram for explaining a sensitivity setting operation that was considered prior to the present invention. MID...Solid-state imaging device, LPF...Low pass filter, DET...Detection circuit, COMP...Voltage comparison circuit, C0UNT...Counter circuit, C0NT...Control circuit, PD...Pixel array, VSR... Vertical shift register for readout, ITG...increment gate circuit for readout, DV...drive circuit for readout, VSRE...vertical shift register for sensitivity setting, ITGE...increment gate circuit for sensitivity setting, DVE...sensitivity setting Drive circuit for T(SR...Horizontal shift register, Fig. 1 Fig. 2 - 1 frame 11

Claims (1)

[Claims] 1. A first scanning circuit that outputs signals of a plurality of pixel cells arranged two-dimensionally in a time-series manner in an interlaced manner, and a vertical scanning direction by the first scanning circuit; a solid-state imaging device including a second scanning circuit that performs a selection operation in the vertical scanning direction in an interlaced manner based on the selection address of the above-mentioned selection address and an independent address; An imaging apparatus characterized by comprising: a sensitivity setting circuit that forms addressing information for the second scanning circuit once every one or a plurality of frames with reference to a corresponding reference signal. 2. The sensitivity setting circuit includes a smoothing circuit that receives a read signal from the solid-state imaging device and converts it into a DC signal, and a voltage comparison circuit that receives an output signal of the smoothing circuit and a reference signal corresponding to a predetermined sensitivity amount; A counter circuit whose up/down control is performed by the voltage comparator circuit and performs one-step counting operation in response to a timing signal generated once every frame or multiple frames, and an output signal of this counter circuit. 2. The imaging apparatus according to claim 1, further comprising a control circuit that receives the address information and forms addressing information that specifies the scanning timing of the second scanning circuit. 3. The two-dimensionally arranged pixel cells constituting the solid-state imaging device include a switch element whose control terminal is coupled to a photoelectric conversion element and a vertical scanning line, and whose control terminal is coupled to a horizontal scanning line. The output nodes of pixel cells arranged in the same row are connected to a common horizontal signal line, and the horizontal signal line is connected through a pair of switch elements whose control terminals are connected to the vertical scanning line. A vertical shift register that is coupled to a pair of output signal lines and constitutes the first scanning circuit and a vertical shift register that constitutes the second scanning circuit correspond to the pair of switch elements at both ends of the vertical scanning line. The imaging device according to claim 1 or 2, wherein the imaging device is arranged as follows.