JPH04290080A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To stabilize a video signal by suppressing flicker by improving responsiveness by varying signal accumulation time equivalent to plural horizontal periods per step, and fitting the level of a readout signal at a dead zone in a target level with high accuracy by performing automatic gain control. CONSTITUTION:The readout signal of a sensitivity variable solid-state image pickup element MID is amplified by a pre-amplifier (b), and it is converted to a DC level VD at a smoothing circuit consisting of a PF and a DET. Reference signals of high level VH and low level VL in accordance with set signal levels are compared with the level VD at a voltage comparator COMP, and a result is supplied to the SR of a sensitivity control circuit. In the case, the signal is set as an up/down operating signal of one bit per frame according to a timing signal from a driving circuit (a), and a sensitivity setting signal is formed at a control circuit CONT, which controls the element MID. Also, the readout signal at the dead zone of constant level provided for the readout signal is set at the target level by performing the automatic gain control.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a solid-state imaging device, in which, for example, a pixel signal formed by a photoelectric conversion element is extracted via a MOSFET (insulated gate field effect transistor), and a sensitivity variable function is added. The present invention relates to a technique that is effective for use in devices using solid-state image sensors.

0002

2. Description of the Related Art A MOS type solid-state image pickup device with a variable sensitivity function is well known. This solid-state image sensor has a vertical scanning circuit for varying sensitivity, and by performing a vertical scanning operation in advance of the vertical scanning circuit, the time difference with respect to the vertical scanning for actual readout is controlled, and the photodiode Controls the actual accumulation time. Regarding a MOS type solid-state image sensor having such a variable sensitivity function, there is, for example, Japanese Patent Application Laid-Open No. 63-37781.

0003

In the imaging apparatus using the solid-state imaging device described above, sensitivity is controlled using 1H (horizontal scanning time) as the minimum step. Also,
Immediately after the power is turned on, the sensitivity control circuit of the solid-state image sensor controls its sensitivity from the minimum sensitivity to the optimum sensitivity. This is because such sensitivity control changes the screen like a fade-in, making it easier to see. However, when starting photography under relatively low illuminance, the sensitivity must be changed from the minimum sensitivity to the maximum sensitivity in steps of 1H, resulting in a relatively long time of 8 to 9 seconds. Therefore, when photographing under such conditions, the first photographed screen remains dark due to insufficient light for several seconds. Also,
The sensitivity will always go up and down by 1H around the target level, causing flickering on the screen. An object of the present invention is to provide a solid-state imaging device that improves responsiveness and provides stable output signals. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0004

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. In other words, in a sensitivity setting circuit that compares the readout signal of a solid-state image sensor with variable sensitivity function with a reference signal corresponding to the signal level to be set and forms a control signal so that the two almost match, Increasing or decreasing the signal accumulation amount by multiple horizontal periods,
A dead zone of a certain level is provided for the read signal, and the read signal in this dead zone is set to a target level using an automatic gain control circuit.

[0005]

[Operation] According to the above-mentioned means, responsiveness can be improved by changing the signal accumulation time corresponding to multiple horizontal periods per step, and the automatic gain control circuit adjusts the readout signal level to the target level with high precision. It can be combined with

[0006]

[Example] Fig. 3 shows a TSL (Transversal Signal) having a variable sensitivity function used in the present invention.
1 shows a circuit diagram of a main part of an embodiment of a solid-state image sensor of the Line type solid-state image sensor. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques. The main blocks in the figure are drawn according to the geometric arrangement in an actual semiconductor integrated circuit device.

[0007] The pixel array PD is exemplarily shown with four rows and two columns. However, in order to prevent the drawing from becoming complicated, circuit symbols are added to only two of the four rows of pixel cells. One pixel cell includes a photodiode D1 and a vertical scanning line VL1.
The switch MOSFET Q1 has its gate coupled to the horizontal scanning line HL1, and the switch MOSFET Q2 has its gate coupled to the horizontal scanning line HL1. The above photodiode D1 and switch MOSFET Q1, Q2
The output nodes of other similar pixel cells (D2, Q3, Q4) arranged in the same row (horizontal direction) as the pixel cell consisting of
is combined with Pixel cells similar to those described above are similarly combined for other rows. An exemplary horizontal scanning line H
L1 extends vertically in the same figure and is commonly coupled to the gates of switch MOSFETs Q2, Q6, etc. of pixel cells arranged in the same column. Pixel cells arranged in other columns are also coupled to corresponding horizontal scanning lines HL2 and the like in the same manner as described above.

In this embodiment, in order to add a substantial electronic automatic aperture function to the solid-state image sensor, in other words, to make the substantial accumulation time for the photodiode variable, the pixel array is Switches M are installed at both ends of the horizontal signal lines HS1 to HS4, etc.
OSFETs Q8, Q9 and Q26, Q28 are provided. The above switch MOSFETQ8 located on the right end side,
Q9 couples each of the horizontal signal lines HS1 and HS2 to an output line VS extending in the vertical direction. This output line V
S is coupled to a terminal S, through which a read signal is transmitted to the input of a preamplifier provided externally. In addition, the above switch MOSFET placed on the left end side
Q26 and Q28 are dummy (reset) output lines D extending vertically from the horizontal signal lines HS1 and HS2, respectively.
Connect to VS. This output line DVS is coupled to the terminal RV, although not particularly limited thereto. This allows the signal of the dummy output line DVS to be sent out from the external terminal RV if necessary.

In this embodiment, although not particularly limited, the horizontal signal lines HS1 to HS4 in each row are connected to terminals RP.
The switch MOSFETQ27, Q is turned on by the reset signal supplied during the horizontal retrace period from
29 etc. are provided. These MOSFETQ27,Q
29, etc., a constant bias voltage (not shown) is applied from the external terminal RV to each of the horizontal signal lines HS1 to HS4 via the dummy output line DVS. The reason why the reset MOSFETs Q27, Q29, etc. as described above are provided is as follows. Switch MOSFET coupled to the horizontal signal lines HS1 to HS4
Semiconductor regions such as the drain of
False signals (smear, blooming) formed by such parasitic photodiodes are accumulated on horizontal signal lines that are left floating when not selected. Therefore, in this embodiment, all the horizontal signal lines HS1 to HS4 are reset to the predetermined bias voltage by using the horizontal retrace period as described above. As a result, for the selected horizontal signal line, the pixel signals are always extracted from the state in which the false signals have been reset, so that the false signals included in the output image signal can be significantly reduced. A horizontal scanning signal formed by a horizontal shift register HSR is supplied to the horizontal scanning lines HL1, HL2, etc. The scanning circuit that performs the vertical selection operation (horizontal scanning operation) in the pixel array PD is composed of the following circuits.

In this embodiment, a pair of switch MOSFETs Q8, Q9, etc. and a switch MOSFET are installed at both ends of the horizontal signal lines HS1 to HS4, etc. of the pixel array PD.
A pair of scanning circuits are provided corresponding to the provision of Q26, Q28, etc. In this embodiment, in order to be applicable to industrial applications, in addition to the interlaced mode, selective two-line simultaneous scanning and non-interlaced mode scanning are enabled. The following scanning circuit is provided on the right side of the pixel array PD. The vertical shift register VSR forms output signals SV1, SV2, etc. used for reading. These output signals SV1, SV2, etc. are sent to the vertical scanning lines VL1 to VL4 and the switch MOSFETs via the interlace gate circuit ITG and the drive circuit VD.
It is supplied to gates such as Q8 and Q9.

Since the interlace gate circuit ITG performs a vertical selection operation (horizontal scanning operation) in the interlace mode, in the first (odd number) field, the vertical scanning line V
L1 to VL4 have adjacent vertical scanning lines VL1 and VL4.
Simultaneously selected by combination of L2 and VL3. That is, the vertical shift register VSR is controlled by the switch MOSFETQ18 controlled by the odd field signal FA.
The output signal SV1 is output to the vertical scanning line VL1 that selects the horizontal signal line HS1. Similarly, the output signal SV2 of the vertical shift register VSR is outputted to the vertical scanning lines VL2 and VL3 to simultaneously select the horizontal signal lines HS2 and HS3 by switch MOSFETs Q20 and Q22 controlled by the signal FA. Thereafter, selection signals for a pair of horizontal signal lines consisting of combinations in the same order are formed.

In the second (even) field, adjacent vertical scanning lines VL1 and VL2 and VL3 and VL4 are simultaneously selected as vertical scanning lines VL1 to VL4. That is, by the switch MOSFETs Q19 and Q21 controlled by the even field signal FB, the output signal SV1 of the vertical shift register VSR is outputted to the vertical scanning lines VL1 and VL2 that select the horizontal signal lines HS1 and HS2. Similarly, the output signal SV2 of the vertical shift register VSR is transferred to the horizontal signal line HS3 by switch MOSFETs Q23 and Q25 controlled by the signal FB.
Vertical scanning lines VL3 and VL4 to simultaneously select
is output to. Thereafter, selection signals for a pair of horizontal signal lines consisting of combinations in the same order are formed.

Interlaced gate circuit IT as described above
G and the next drive circuit DV realize a plurality of types of horizontal scanning operations as described below. The output signal from the interlaced gate circuit ITG corresponding to the one vertical scanning line VL1 is transmitted to the switch MOSFET Q14.
and is supplied to the gate of Q15. These switches MO
The common drain electrodes of SFETs Q14 and Q15 are coupled to terminal V3. Above switch MOSFETQ
14 supplies the signal supplied from the terminal V3 to the vertical scanning line VL1. In addition, switch MOSFETQ15
connects the signal supplied from the terminal V3 to the horizontal signal line HS
Switch MOSFETQ8 that couples 1 to the output line VS
is supplied to the gate. In addition, in order to prevent the high level of the output signal from decreasing by the threshold voltage due to the switches MOSFETQ14 and Q15, the gate of MOSFETQ14 and the MOSFET
A capacitor C1 is connected between the output side (source side) of TQ15.
is provided. As a result, when the output signal from the interlace gate circuit ITG is set to a high level, the potential of the terminal V3 is set to a low level and the capacitor C1 is precharged. Thereafter, when the potential of the terminal V3 is set to a high level, the gate voltages of the MOSFETs Q14 and Q15 can be boosted by the bootstrap action of the capacitor C1.

The output signal from the interlace gate circuit ITG corresponding to the vertical scanning line VL2 adjacent to the vertical scanning line VL1 is transmitted to switch MOSFETs Q16 and Q17.
is supplied to the gate. These switch MOSFETs
The common drain electrode of Q16 and Q17 is connected to the terminal V
Combined with 4. The above switch MOSFETQ16 is
A signal supplied from the terminal V4 is supplied to the vertical scanning line VL2. The switch MOSFETQ17 is connected to the terminal V
4, the horizontal signal line HS2 is connected to the output line VS
is supplied to the gate of switch MOSFET Q9 which is coupled to the gate of the switch MOSFET Q9. The high level of the output signal is the switch MOSFET
Although not particularly limited, in order to prevent the threshold voltage from decreasing by the threshold voltage due to Q16 and Q17,
A capacitor C2 is provided between the gate of TQ16 and the output side (source side) of MOSFETQ17. Thereby, by changing the potential of the terminal V4 at the same timing as described above, the gate voltages of the MOSFETs Q16 and Q16 can be boosted by the bootstrap action of the capacitor C2.

The terminal V3 is connected to the odd-numbered vertical scanning line (
Drive switch MOSFET compatible with horizontal signal lines)
The terminal V4 is provided in common for even-numbered vertical scanning lines (horizontal signal lines). As can be understood from the above, the read operation in the interlace mode is achieved by the combination of selectively supplying timing signals to the terminals V3 and V4 and the simultaneous selection of two rows by the interlace gate circuit ITG. It becomes possible. For example, in an odd field in which the terminal FA is set to a high level, terminal V4 is set to a low level and a timing signal synchronized with the operation of the vertical shift register VSR is supplied to the terminal V3. signal line) to VL1 (HS1), VL3 (HS
3) can be selected in this order. Further, in an even field in which the terminal FB is set to high level, terminal V3 is set to low level and a timing signal synchronized with the operation of the vertical shift register VSR is supplied to terminal V4. signal line) to VL2 (H
S2) and VL4 (HS4) can be selected in this order.

If the terminals V3 and V4 are set to high level simultaneously in the same manner as above, the interlaced gate circuit ITG
Simultaneous scanning of two lines can be performed according to the output signal from the . In this case, as mentioned above, two field signals F
By shifting the combination of two lines A and FB output for every two screens up and down by one line, the spatial center of gravity is shifted up and down, in other words, an equivalent interlace mode is realized. .

For example, by setting only the terminal FB to a high level,
Horizontal shift register HSR with one vertical scan timing
By operating VL1, VL2, and VL twice and synchronizing with this and bringing terminals V3 and V4 to high level, VL1, VL2, and VL
3. Selection operation in non-interlace mode can be realized in the order of VL4. In this case, in order to achieve higher image quality, it is desirable that the clocks supplied to the horizontal shift register HSR and vertical shift register VSR be doubled in frequency. That is, terminals H1 and H2 and terminal V1
By doubling the frequency of the clock signal supplied from HSR and V2 to the horizontal shift register HSR and vertical shift register VSR, it is possible to read out 60 images per second in a non-interlaced manner. Note that the terminals HIN and VIN are terminals that supply input signals to be shifted by the shift registers HSR and VSR, respectively, and a shift operation is started from the time when the input signals are supplied. Therefore, when performing the above-mentioned two-row simultaneous readout, interlace scanning, non-interlace scanning, etc. by combining the input signals supplied to the interlace gate circuit ITG and input terminals V3 and V4, the vertical In order to prevent the vertical relationship from being reversed, when supplying the input signal to the shift register VSR,
Timing considerations are required.

Reset MOSFETs Q10 and Q11 are connected between the gates of each vertical scanning line VL1 and the corresponding switch MOSFET Q8 and the ground potential point of the circuit.
is provided. These reset MOSFETQ10
and Q11 are other vertical scan line and switch MOSFETs
In response to a signal supplied from the terminal V2 in common with the reset MOSFET provided corresponding to the reset MOSFET, the gate potential of the vertical scanning line and the switch MOSFET in the selected state is quickly pulled to a low level.

In this embodiment, in order to add the sensitivity variable function as described above, a vertical shift register VSRE for sensitivity control, an interlace gate circuit ITGE, and a drive circuit DVE are provided. Each of these circuits has the same configuration as each circuit that performs vertical scanning for reading, and each circuit is represented by one black box in the figure. Each of these sensitivity control circuits is arranged on the left side with respect to the pixel array PD, although it is not particularly limited. Timing signals similar to those of the reading vertical scanning circuit are supplied from terminals V1E to V4E, VINE, FAE, and ABE, respectively. in this case,
Since the vertical shift register VSR for readout and the vertical shift register VSRE for variable sensitivity are shifted at synchronized timing, terminals V1E and V1 and V2E and V2 are connected to the same clock, although there is no particular restriction. A signal is provided. Therefore, the above terminal V1E
, V1, and V2E and V2 may be shared by an internal circuit. Unique terminal V1E as above
and V2E are provided so that this solid-state imaging device can be applied to a television camera having a manual aperture or a conventional mechanical aperture function. When variable sensitivity operation is not performed in this way, by setting the terminals V1E and V2E to a low level such as the ground potential of the circuit,
Consideration has been taken to prevent wasteful power consumption of the vertical shift register VSRE.

Next, the sensitivity control operation in the solid-state image sensing device of the above embodiment will be explained. To simplify the explanation,
The vertical scanning operation in the non-interlaced mode will be described below as an example. For example, vertical shift register VSRE for sensitivity control, interlace gate circuit ITGE
and the driver circuit DVE, the fourth row is read out in parallel with the reading of the first row (vertical scanning line VL1, horizontal signal line HS1) by the reading vertical shift register VSR, interlace gate circuit ITG, and drive circuit DV. (vertical scanning line VL4, horizontal signal line HS4) selection operation is performed. As a result, the optical signals accumulated in the photodiodes D1, D2, etc. in the first row are transferred to the output signal line VS in synchronization with the selection operation of the horizontal scanning lines HL1, HL2, etc. formed by the horizontal shift register HSR. Read out in chronological order. This read operation is performed by supplying a current corresponding to the optical signal from the terminal S through the load resistor, and a precharge (reset) operation is performed simultaneously with the read operation.

A similar operation is performed for the photodiodes in the fourth row. In this case, the sensitivity variable vertical scanning circuit (VSRE, ITGE, DV
According to E), the read operation on the fourth row is performed on the dummy output line DVS. When only the sensitivity control operation is performed, the same bias voltage as the terminal S is applied to the terminal RV. As a result, the optical signals already accumulated in each pixel cell in the fourth row are swept out, or in other words, a reset operation is performed. Therefore, by the vertical scanning operation, the reading operation of the fourth row (vertical scanning line VL4, horizontal signal line HS4) by the reading vertical shift register VSR, interlace gate circuit ITG, and drive circuit DV is performed on the first row. Since this is performed after the readout operation of the third row, the storage time of the photodiode of the pixel cell arranged in the fourth row is the readout time of the pixel cells of three rows.

Instead of the above, the vertical shift register VSRE for sensitivity control, the interlace gate circuit ITGE and the drive circuit DVE are used to control the first row by the vertical shift register VSR for reading, the interlace gate circuit ITG and the drive circuit DV. In parallel with the reading of (vertical scanning line VL1, horizontal signal line HS1), the selection operation of the second row (vertical scanning line VL2, horizontal signal line HS2) is performed. As a result, in synchronization with the selection operation of the horizontal scanning lines HL1, HL2, etc. formed by the horizontal shift register HSR,
The optical signals accumulated in the photodiodes D1, D2, etc. in the first row are read out in time series to the output signal line VS. This read operation is performed by supplying a current corresponding to the optical signal from the terminal S through the load resistor, and a precharge (reset) operation is performed simultaneously with the read operation. A similar operation is performed in the photodiodes D3, D4, etc. in the second row. by this,
In parallel with the readout operation of the first row, an operation of sweeping out the optical signals already accumulated in each pixel cell of the second row is performed.

[0023] Therefore, by the above vertical scanning operation,
The readout operation of the second row (vertical scanning line VL2, horizontal signal line HS2) by the readout vertical shift register VSR, interlace gate circuit ITG, and drive circuit DV is performed after the readout operation of the first row. , second
The storage time of the photodiode of the pixel cell arranged in the row is the readout time of the pixel cell for one row. As a result, compared to the above case, the actual storage time of the photodiode can be reduced to 1/3, or in other words, the sensitivity can be lowered to 1/3.

To explain this generally, when the scanning circuit for sensitivity control selects the m-th vertical scanning line VLm, the scanning circuit for reading selects the n-th vertical scanning line VLn. Sometimes there is a time difference of X(m-n)H. Here, H is the horizontal scanning time. therefore,
When the vertical scanning line VLm is scanned by the preceding vertical scanning operation, the pixel cells of the vertical scanning line VLm are reset, so from the reset operation until the vertical scanning line VLm is selected again by the reading scanning circuit. The time (XH) is taken as the storage time for the photodiode. Therefore, for a pixel array consisting of 525 rows, it is necessary to set the readout time in multiple stages up to a maximum of 525H minutes, with the readout time of 1H being the unit (minimum), or in other words, setting the sensitivity over 525 stages. Can be done. However, it is assumed that the vertical scanning operation is non-interlaced, that changes in the light-receiving surface illuminance can be ignored with respect to the scanning time constituting one screen, and that substantially constant light is incident on the photodiode. In interlaced mode, the l field is 262.5 with 525/2.
Since the signal becomes H, the sensitivity (storage time) is set from 1H to 262H. In addition, the above maximum sensitivity (525H or 262H)
H) is obtained when the sensitivity control scanning circuit VSRE and the like are in a non-operating state.

FIG. 1 shows a block diagram of an embodiment of a solid-state imaging device having an electronic automatic aperture function according to the present invention. The solid-state image sensor MID has a variable sensitivity function as shown in FIG. 3 above. The read signal output from the solid-state image sensor MID is amplified by a preamplifier. This amplified signal Vout is supplied to a signal processing circuit (not shown) on the one hand, and is used as, for example, an image signal for television. The amplified signal Vout
is used for sensitivity control on the other hand. That is, the amplified signal Vout is passed through the low pass filter LPF.
It is converted to a DC level by a smoothing circuit consisting of a detection circuit DET and a detection circuit DET. This DC level VD is supplied to the voltage comparison circuit COMP. The voltage comparison circuit COMP is a circuit that performs a window-type voltage comparison operation, and has two reference voltages, a high level VH and a low level VL, and performs a comparison operation between them and the above-mentioned series level VD.

[0026] The voltage comparator circuit COMP compares the voltage V
If the level comparison result between H and VD is VD>VH, logic 1
It forms an output signal of 1, and forms an output signal of logic 0 if VD<VL. If VH>VD>VL, a logic 01 or 10 is formed, which means that the dead zone is in effect. Although not particularly limited, the voltage comparison circuit COMP is composed of two comparators having the reference voltages VH and VL as described above, and a 2-bit voltage comparison signal as described above is generated by combining the outputs of the respective comparators. It is formed.

The output signal of the voltage comparison circuit COMP is as follows:
Although not particularly limited, it is supplied to the up/down control terminal U/D of the shift register SR constituting the sensitivity control circuit. If the above comparison output signal is logic 11, shift register S
R indicates a down operation, and a logic 0 indicates an up operation. If the logic is 10 or 10, the shift operation is prohibited. This shift register SR performs a 1-bit up/down shift operation per frame when the timing signal from the drive circuit is a clock pulse and the logic is 11 or 00.

The data held in the shift register SR is supplied to the control circuit CONT. Control circuit CONT
decodes the data in the shift register SR to form a sensitivity setting signal. That is, the solid-state imaging device MID performs the above-described readout operation in response to signals VIN, V1, etc. formed by the drive circuit. The control circuit CONT receives the readout VIN, V1, etc., refers to the readout timing of the solid-state image pickup device MID, and performs control on the readout horizontal line in response to the decoding signal of the cyst signal of the shift register SR. to form a substantially preceding timing signal VINE. That is, since the preceding timing signal VINE corresponding to the required aperture amount (sensitivity) is formed based on the timing signal VIN, the signal VINE is actually formed after the timing signal VIN. .

However, since repeated scanning is performed, from the point of view of the signal VINE, the signal VIN is delayed in scanning the next screen. In other words, the timing signal VI is delayed by 1H with respect to the timing signal VIN.
When NE is generated, the timing signal V is generated in the next scanning screen.
INE is regarded as a timing signal that precedes the timing signal VIN by 261H (in interlace mode). Since the shift operation of each vertical shift register VSR and VSRE is started by the timing signals VIN and VINE, a sensitivity variable operation is performed.

In this embodiment, the sensitivity is set to the lowest sensitivity when photographing starts after the power is turned on. That is, the least significant bit of the shift register SR is set to 1. As a result, the control circuit CONT generates the timing signal VINE that is delayed by 261H with respect to the timing signal VIN, and in the next field, the timing signal is substantially 1H as described above.
Performs vertical scanning with a line lead. When shooting in low light conditions, the output signal is small at this lowest sensitivity, so
The output signal of the voltage comparison circuit COMP becomes logic 00, and the shift register SR is shifted up bit by bit in the sensitivity setting operation for each frame. This results in 2, 4, 8
, 16, . . . , etc., and the maximum sensitivity is reached by performing nine sensitivity setting operations.

When the sensitivity is increased such that voltage VD>voltage VL, the output signal of the voltage comparator COMP changes from logic 00 to 01, and the sensitivity control operation is then stopped. That is, as shown in FIG. 2, the period between VH and VL is set as a dead zone, and the operation of the sensitivity control circuit is stopped. Then, the voltage VD corresponding to the read signal in this dead zone
An automatic gain control circuit AGC included in the signal processing circuit is provided in order to ensure that Vref is at the target level Vref. This automatic gain control circuit AGC controls the target level Vre.
The gain is linearly changed so that a video output signal VDO corresponding to f is formed. By performing a gain control operation on such a linear readout signal, the video output signal VDO can be accurately set to a constant target level without flickering on the screen.

[0032] When the readout signal from the solid-state image sensor MID deviates from the dead zone in response to variations in the brightness of the object, the signal accumulation time of the solid-state image sensor MID is changed by the shift up/down operation of the shift register SR. Sensitivity switching is performed by changing the sensitivity. Then, the automatic gain control circuit A sets the final target level.
This is achieved through GC gain control.

The effects obtained from the above embodiments are as follows. (1) In a sensitivity setting circuit that compares a readout signal from a solid-state image sensor having a variable sensitivity function with a reference signal corresponding to a signal level to be set and forms a control signal so that the two substantially match, By increasing or decreasing the signal accumulation amount for each step time by multiple horizontal periods, such as doubling or halving, sensitivity setting responsiveness can be increased, and the target level can be automatically set within the dead zone. Since this is performed linearly by the gain control circuit, it is possible to prevent flickering on the screen. (2) By doubling or halving the signal accumulation time per step as described above, the sensitivity setting signal can be formed using a shift register, making it possible to simplify the circuit. This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say. For example, in addition to simply calculating the average value as described above, the configuration of an analog circuit that processes the readout signal may be one that calculates the peak value and mixes it to set the aperture amount, or one that digitizes the smoothed output level and uses it as a digital standard. Various embodiments can be adopted, such as one that calculates the difference between the signal and the signal. In the case of digitization in this way, a digital comparator may be used to compare whether or not the absolute value of the difference exceeds a certain amount with respect to the target value, thereby setting a dead zone similar to that of the embodiment described above. The accumulation time per step in sensitivity control may be set to a fixed time, such as 10 horizontal periods, or 5 horizontal periods per step in a low sensitivity region, and 10 horizontal periods per step in an intermediate sensitivity region. In the horizontal period, the unit storage time may be changed such as 20 horizontal periods per step in a region with high sensitivity.

The solid-state imaging device used in the solid-state imaging device according to the present invention can be applied to, for example, a device using a CCD (charge transfer device), in addition to the MOS type solid-state imaging device as in the above embodiment. That is, a reset circuit is added that sweeps out the charge of the photodiode in the row preceding the row to be read, and this reset circuit is put into operation by a scanning circuit for sensitivity setting, and a sensitivity variable function is added. It may be something. The present invention can be widely used in solid-state imaging devices using fixed imaging elements that have a variable sensitivity function by sweeping out signals from the row preceding the row to be read as described above.

[0036]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a sensitivity setting circuit that compares a readout signal from a solid-state image sensor with a sensitivity variable function with a reference signal corresponding to the signal level to be set and forms a control signal so that the two almost match, one step is performed. By increasing/decreasing the amount of signal accumulation per time by multiple horizontal periods, such as doubling or halving, the responsiveness of sensitivity setting can be increased, and the automatic gain allows setting to the target level within the dead zone. Since this is performed linearly by the control circuit, flickering on the screen can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a level characteristic diagram for explaining the sensitivity setting operation of the solid-state imaging device of FIG. 1;

FIG. 3 is a schematic circuit diagram showing one embodiment of a solid-state image sensor used in the present invention.

[Explanation of symbols]

MID...solid-state image sensor, LPF...low-pass filter, D
ET...detection circuit, COMP...voltage comparison circuit, SR...shift register, CONT...control circuit, PD...pixel array,
VSR...Vertical shift register for readout, ITG...Interlace gate circuit for readout, DV...Drive circuit for readout, VSRE...Vertical shift register for sensitivity setting, IT
GE...Interlace gate circuit for sensitivity setting, DVE...Drive circuit for sensitivity setting, HSR...Horizontal shift register.

Claims (3)

[Claims] 1. A first scanning circuit that outputs signals of a plurality of pixel cells arranged two-dimensionally in time series, and a vertical scanning operation independent of the vertical scanning operation in the first scanning circuit. A solid-state imaging device including a second scanning circuit that performs the above-mentioned processing, and a sensitivity control signal that increases or decreases the signal accumulation amount by a plurality of horizontal periods according to a comparison result between a readout signal of the solid-state imaging device and a signal level to be set. a sensitivity control circuit that controls the operation start timing of the second scanning circuit and does not accept signal changes within a certain level as a dead zone; and an automatic gain control circuit that amplifies the readout signal of the solid-state image sensor. A solid-state imaging device comprising: 2. The sensitivity control circuit doubles or halves the previous accumulation time in response to a comparison result between the readout signal of the solid-state image sensor and a reference signal corresponding to a signal level to be set. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured to increase or decrease the amount. 3. The solid-state imaging device according to claim 1, wherein the sensitivity is set to the lowest sensitivity immediately after the solid-state imaging device starts imaging.