JPH0575929A - Solid state image pickup element - Google Patents

Abstract

PURPOSE:To make it possible to vary sensitivity by sweeping the signal charge of picture element cells in a practically valid display screen smaller than an image pickup element valid picture element range time-independently of the scanning operation of a signal output function. CONSTITUTION:Vertical CCD(VCCD) for reading signals are arranged on the right sides of photodiodes and signal sweeping routes are arranged on the left sides of the photodiodes. In a CCD type solid state image pickup element, the signal charge of respective photodiodes is simultaneously read out to their corresponding VCCDs. Signals corresponding to each horizontal picture element are transmitted from the VCCDs to a horizontal CCD(HCCD) in parallel. The signal charge for one horizontal(1H) picture elements through the HCCD is converted into a voltage signal through an amplifier AMP and the voltage signal is serially outputted. Thus the sensitivity can be varied under the control of stored time by sweeping the signal charge in the picture element cells to the signal sweeping routes at the optional timing of signal reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a technique effective for use in a device having a function of sweeping out a signal charge of a pixel cell at an arbitrary timing.

[0002]

2. Description of the Related Art A solid-state image sensor having a variable sensitivity function is known. In the solid-state image pickup device having the sensitivity variable function, the signal charge of the pixel cell is swept out at an arbitrary timing to control the signal storage time of the pixel cell to perform the sensitivity control. As an example of a solid-state image sensor having such a sensitivity variable function, for example, Japanese Patent Laid-Open No.
There is a MOS type solid-state image sensor described in Japanese Patent Laid-Open No. 3-37781.

[0003]

When a video camera is constructed by using a solid-state image pickup device, flicker occurs when shooting with a light source whose brightness changes periodically such as a fluorescent lamp. In order to prevent this flicker, in a video camera that uses a solid-state image sensor with a variable sensitivity function, an optical sensor detects changes in the light source, and the detection signal is used to set the electronic shutter speed by the variable sensitivity function. It is possible to prevent the occurrence of flicker. However, in this case, it is necessary to provide an optical sensor outside the camera body, which is a problem in terms of mounting space and circuit components in a video camera that is being made smaller and lighter. The inventor of the present application paid attention to the fact that the solid-state imaging device itself is a kind of optical sensor, and considered adding a function of detecting the amount of incident light while having a sensitivity variable function. An object of the present invention is to provide a solid-state image sensor capable of detecting the amount of incident light while having a sensitivity varying function with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the signals of a plurality of pixel cells that are two-dimensionally arrayed in the image sensor effective pixel range are output in time series, and the signal is output from the image sensor effective pixel range independently of the scanning operation in the signal output function. The signal charge of the pixel cell of the effective display screen which is made into a small area is swept out, and the pixel cell in which the signal sweeping is not performed is provided outside this effective display screen and it is used as an optical sensor.

[0005]

According to the above-mentioned means, the optical sensor can be formed inside the solid-state image pickup device while having the sensitivity varying function.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an image pickup screen of an embodiment of a solid-state image pickup device according to the present invention. In the image sensor effective pixel range, a pixel cell and a path for reading out the signal and a signal sweeping path for varying the sensitivity are formed. For example, a CCD (charge transfer device) type solid-state image pickup device, which will be described later, includes a photodiode that constitutes a pixel cell and a vertical CCD that transfers a signal charge.
The S-type solid-state image pickup device is composed of a switch MOSFET for reading out the signal from the pixel cell and a scanning line and a signal line for controlling the switch MOSFET.

Within the effective pixel range of the image pickup device, a television screen range displayed on a screen of a television receiver or the like, in other words, a substantially effective display screen is constituted. An electronic shutter non-operating range is provided outside the effective display screen in a shaded area below the effective pixel range of the image sensor. That is, signals are read out from the pixel cells in the electronic shutter non-operating range, but signals are not swept out. Although not directly related to the present invention, a pixel cell is formed outside the effective pixel range of the image sensor, and a light shielding film is provided in this pixel, and the pixel cell indicates a reference indicating optical black. The electric potential is output.

FIG. 2 is a schematic block diagram of an embodiment of a CCD type solid-state image pickup device to which the present invention is applied. A vertical CCD (abbreviated as VCCD in the figure) for reading out a signal is provided on the right side of the photodiode. In order to add a variable sensitivity function, although not particularly limited, a signal sweeping path is provided on the left side of the photodiode. In the CCD type solid-state image pickup device, the signal charges of the photodiodes are simultaneously read out to the corresponding vertical CCDs. This signal charge is transmitted to the horizontal CCD (abbreviated as HCCD in the drawing) in parallel by the vertical CCD for the signal of one horizontal pixel. And through this horizontal CCD, 1
The signal charge for H is converted into a voltage signal through the amplifier AMP and serially output. The sensitivity is varied by controlling the accumulation time by sweeping out the signal charge of the pixel cell to the signal sweeping path at an arbitrary timing when such signal reading is performed.

In this embodiment, among the photodiodes which are two-dimensionally arranged as described above, the photodiodes arranged in the lowermost stage in the figure are read out by transmitting the signal charges to the vertical CCDs. There is no sweep path. That is, the signal charges of these photodiodes always output the signal charges with a constant signal accumulation time regardless of the sensitivity variable control. It should be noted that in the CCD of this embodiment, the signal that is read out first is an optical sensor output that is outside the television screen range, which is the effective display screen. Therefore, in the correspondence with FIG. 1, the vertical relationship is reversed.

FIG. 3 shows a TSL to which the present invention is applied.
A circuit diagram of a main part of an embodiment of a MOS type solid-state image pickup device of a (Transversal Signal Line) type is shown. Each circuit element in the figure is not particularly limited by a well-known semiconductor integrated circuit manufacturing technique, but is not limited to a single crystal silicon
It is formed on each semiconductor substrate. The main blocks in the figure are drawn according to the geometrical arrangement in the actual semiconductor integrated circuit device.

The pixel array PD is exemplarily shown as having four rows and two columns. However, in order to prevent the drawing from being complicated, circuit symbols are added only to the pixel cells of two rows of the above four rows. One pixel cell includes a photodiode D1 and a switch MOSFET Q1 whose gate is coupled to a vertical scanning line VL1.
A switch M whose gate is coupled to the horizontal scanning line HL1
It is composed of a series circuit of the OSFET Q2. The output nodes of other similar pixel cells (D2, Q3, Q4) arranged in the same row (horizontal direction) as the pixel cell composed of the photodiode D1 and the switch MOSFETs Q1, Q2,
In the figure, it is coupled to a horizontal signal line HS1 extending in the horizontal direction. Pixel cells similar to the above are similarly combined for the other rows. Horizontal scan line HL1 shown as an example
Are extended in the vertical direction in the figure and are commonly coupled to the gates of the switch MOSFETs Q2, Q6, etc. of the pixel cells arranged in the same column. Pixel cells arranged in other columns are also coupled to the corresponding horizontal scanning line HL2 and the like as described above.

In this embodiment, in order to add a sensitivity varying function to the solid-state image pickup element, in other words, to vary the substantial accumulation time for the photodiode,
Horizontal signal lines HS1 to HS forming the pixel array
Switch MOSFETs Q8 and Q are connected to both ends of
9 and Q26 and Q28 are provided. The switch MOSFETs Q8 and Q9 arranged on the right end side couple the horizontal signal lines HS1 and HS2 to the output line VS extending in the vertical direction, respectively. The output line VS is coupled to the terminal S, and the read signal is transmitted to the input of the external preamplifier through the terminal S. The switch MOSFETs Q26 and Q28 arranged on the left end side are
The horizontal signal lines HS1 and HS2 are respectively coupled to the dummy (reset) output line DVS extending in the vertical direction.
The output line DVS is coupled to the terminal RV, though not particularly limited. As a result, if necessary, the dummy output line D
The VS signal can be transmitted from the external terminal RV.

In this embodiment, although not particularly limited, the terminals RP are connected to the horizontal signal lines HS1 to HS4 in each row.
Switch MOSFETs Q27, Q which are turned on by a reset signal supplied in the horizontal retrace period from
29 and the like are provided. These MOSFETs Q27, Q
A constant bias voltage (not shown) is applied to each of the horizontal signal lines HS1 to HS4 from the external terminal RV through the dummy output line DVS by the ON state of 29 or the like.
The reason why the reset MOSFETs Q27, Q29 and the like as described above are provided is as follows. Switch MOSFETs coupled to the horizontal signal lines HS1 to HS4
The semiconductor region such as the drain of may also be photosensitive,
False signals (smear, blooming) formed by such parasitic photodiodes are accumulated in the horizontal signal line which is brought into a floating state when not selected. Therefore, in this embodiment, all the horizontal signal lines HS1 to HS4 are reset to the predetermined bias voltage by utilizing the horizontal blanking period as described above. As a result, with respect to the selected horizontal signal line, since the pixel signal is always taken out from the state in which the false signal is reset, the false signal included in the output image signal can be significantly reduced. A horizontal scanning signal formed by a horizontal shift register HSR is supplied to the horizontal scanning lines HL1 and HL2.

A scanning circuit for performing a vertical selection operation (horizontal scanning operation) in the pixel array PD is composed of the following circuits. A pair of switch MOSFETs Q is provided at both ends of the horizontal signal lines HS1 to HS4 of the pixel array PD.
A pair of scanning circuits are provided corresponding to the provision of the switch MOSFETs Q26 and Q28 and the switch MOSFETs Q26 and Q28.

In this embodiment, in addition to the interlaced mode, selective two-row simultaneous scanning and non-interlaced mode scanning are possible in order to be applicable to industrial applications. The following scanning circuit is provided on the right side of the pixel array PD. The vertical shift register VSR forms output signals SV1, SV2, etc. used for reading. These output signals SV1, SV2, etc. are transmitted through the interlaced gate circuit ITG and the drive circuit VD to the vertical scanning lines VL1 to VL4 and the switch MOSFETs Q8, Q.
It is supplied to the 9th gate.

Since the interlaced gate circuit ITG performs the vertical selection operation (horizontal scanning operation) in the interlaced mode, the vertical scanning line V in the first (odd) field.
The adjacent vertical scanning lines VL1 and V are connected to L1 to VL4.
The combination of L2 and VL3 is simultaneously selected. That is, the vertical shift register VS is controlled by the switch MOSFET Q18 controlled by the odd field signal FA.
The R output signal SV1 is output to the vertical scanning line VL1 that selects the horizontal signal line HS1. Similarly, the output signal SV2 of the vertical shift register VSR is changed by the switch MOSFETs Q20 and Q22 controlled by the signal FA.
The signals are output to the vertical scanning lines VL2 and VL3 so that the horizontal signal lines HS2 and HS3 are simultaneously selected. Thereafter, a pair of horizontal signal line selection signals are formed in a similar combination.

In the second (even) field, vertical scanning lines VL1 to VL4 are simultaneously selected by a combination of adjacent vertical scanning lines VL1 and VL2 and VL3 and VL4. That is, the output signals SV1 of the vertical shift register VSR are output to the vertical scanning lines VL1 and VL2 that select the horizontal signal lines HS1 and HS2 by the switch MOSFETs Q19 and Q21 controlled by the even field signal FB. Similarly, the output signal SV2 of the vertical shift register VSR is supplied to the horizontal signal line HS3 by the switch MOSFETs Q23 and Q25 controlled by the signal FB.
And the vertical scanning lines VL3 and VL4 so as to simultaneously select the data lines and HS4.
Is output to. Thereafter, a pair of horizontal signal line selection signals are formed in a similar combination.

Interlaced gate circuit IT as described above
G and the next drive circuit DV realize a plurality of types of horizontal scanning operations as described below. The output signal from the interlaced gate circuit ITG corresponding to the one vertical scanning line VL1 is a switch MOSFET Q14.
And to the gate of Q15. These switches MO
The common drain electrodes of SFETs Q14 and Q15 are coupled to the terminal V3. Switch MOSFET above
Q14 supplies the signal supplied from the terminal V3 to the vertical scanning line VL1. Also, the switch MOSFET Q1
Reference numeral 5 denotes a signal supplied from the terminal V3 on the horizontal signal line H.
Switch MOSFET Q for coupling S1 to output line VS
8 gates. Further, in order to prevent the high level of the output signal from being lowered by the threshold voltage of the switch MOSFETs Q14 and Q15, the gate of the MOSFET Q14 and the MOSF are not particularly limited.
Capacitor C between the output side (source side) of ETQ15
1 is provided. As a result, when the output signal from the interlaced gate circuit ITG is set to the high level, the potential of the terminal V3 is set to the low level and the capacitor C1 is set.
Pre-charge. After that, when the potential of the terminal V3 is set to a high level, the gate voltage of the MOSFETs Q14 and Q15 can be boosted by the bootstrap action of the capacitor C1.

Output signals from the interlaced gate circuit ITG corresponding to the vertical scanning line VL2 adjacent to the vertical scanning line VL1 are output from the switch MOSFETs Q16 and Q17.
Is supplied to the gate. These switch mosfets
The common drain electrode of Q16 and Q17 is the terminal V
Is combined with 4. The switch MOSFET Q16 is
The signal supplied from the terminal V4 is supplied to the vertical scanning line VL2. The switch MOSFET Q17 has the terminal V
The signal supplied from the horizontal signal line HS2 to the output line VS
Is supplied to the gate of a switch MOSFET Q9 that is coupled to. High level of output signal is switch MOSFET
Although it is not particularly limited in order to prevent the voltage drop by the threshold voltage of Q16 and Q17,
A capacitor C2 is provided between the gate of TQ16 and the output side (source side) of MOSFET Q17. Thus, the gate voltage of the MOSFETs Q16 and Q16 can be boosted by the bootstrap action of the capacitor C2 by changing the potential of the terminal V4 at the same timing as above.

The terminal V3 is a drive switch MOSFET corresponding to an odd-numbered vertical scanning line (horizontal signal line).
The terminal V4 is commonly provided for T, and the terminal V4 is commonly provided for even-numbered vertical scanning lines (horizontal signal lines). As will be understood from the above, the read operation in the interlaced mode can be performed by the combination of the alternative supply of the timing signal to the terminals V3 and V4 and the simultaneous two-row selection operation by the interlaced gate circuit ITG. It will be possible. For example, in the odd field where the terminal FA is set to the high level, the terminal V4 is set to the low level and a timing signal synchronized with the operation of the vertical shift register VSR is supplied to the terminal V3 so that the vertical scanning line (horizontal Signal line) VL1 (HS1), VL3 (H
It is possible to select in the order of S3). Further, in the even field in which the terminal FB is set to the high level, the terminal V3 is set to the low level and the timing signal synchronized with the operation of the vertical shift register VSR is supplied to the terminal V4, so that the vertical scanning line (horizontal Signal line) to VL2
(HS2) and VL4 (HS4) can be selected in this order.

If the terminals V3 and V4 are simultaneously set to the same high level as described above, the interlaced gate circuit ITG is obtained.
2 rows can be simultaneously scanned in accordance with the output signal from. In this case, as described above, the two field signals F
By vertically shifting the combination of two lines output by two screens by A and FB by one line, the spatial center of gravity is vertically shifted, in other words, an equivalent interlaced mode is realized. ..

For example, setting only the terminal FB to a high level,
Horizontal shift register HSR at one vertical scanning timing
Is operated twice and the terminals V3 and V4 are set to the high level in synchronization therewith, so that VL1, VL2 and VL
It is possible to realize the selection operation in the non-interlaced mode like 3 and VL4. In this case, it is desirable that the clock supplied to the horizontal shift register HSR and the vertical shift register VSR has a frequency doubled in order to obtain higher image quality. That is, terminals H1 and H2 and terminal V1
By setting the frequency of the clock signal supplied from V2 and V2 to the horizontal shift register HSR and the vertical shift register VSR to twice as high, it is possible to read 60 images per second by the non-interlaced method. The terminals HIN and VIN are terminals that supply input signals that are respectively shifted by the shift registers HSR and VSR, and the shift operation starts from the time when the input signals are supplied. Therefore, when the above-mentioned two-row simultaneous reading, interlaced scanning, non-interlaced scanning, etc. are performed by the combination of the input signals supplied to the interlaced gate circuit ITG and the input terminals V3, V4, the vertical output signal is output. When supplying the input signal of the shift register VSR, it is necessary to consider the timing so that the vertical relationship of the directions is not reversed.

Reset MOSFETs Q10 and Q11 are provided between the gates of the vertical scanning lines VL1 and the switch MOSFET Q8 corresponding thereto and the ground potential point of the circuit.
Is provided. These reset MOSFET Q10
And Q11 are other vertical scan lines and switch MOSFETs.
In response to the signal supplied from the terminal V2 in common with the reset MOSFET provided corresponding to, the gate potentials of the vertical scanning line and the switch MOSFET in the selected state are quickly pulled to the low level.

In this embodiment, a vertical shift register VSRE for sensitivity control, an interlaced gate circuit ITGE and a drive circuit DVE are provided in order to add the sensitivity variable function as described above. Each of these circuits has the same configuration as each circuit for performing the vertical scanning for reading, and each circuit is represented by one black box in FIG. Although not particularly limited, these sensitivity control circuits are arranged on the left side of the pixel array PD. Timing signals similar to those of the vertical scanning circuit for reading are supplied from terminals V1E to V4E, VINE, FAE, and ABE, respectively. in this case,
The read vertical shift register VSR and the sensitivity varying vertical shift register VSRE perform the shift operation at the timings synchronized with each other. Therefore, the terminals V1E and V1 and V2E and V2 have the same clock. Signal is supplied. Therefore, the terminal V1E
And V1 and V2E and V2 may be shared by an internal circuit. Unique terminal V1E as described above
And V2E are provided so that this solid-state imaging device can be applied to a television camera having a manual diaphragm or a conventional mechanical diaphragm function. When the sensitivity variable operation is not performed in this way, by setting the terminals V1E and V2E to a low level such as the ground potential of the circuit,
The vertical shift register VSRE is designed to generate unnecessary power consumption.

Next, the sensitivity control operation in the solid-state image pickup device of the above embodiment will be described. To simplify the explanation,
The vertical scanning operation in the non-interlaced mode will be described below as an example. For example, a vertical shift register VSRE for sensitivity control, an interlaced gate circuit ITGE
And the driving circuit DVE, in parallel with the reading of the first row (vertical scanning line VL1, horizontal signal line HS1) by the reading vertical shift register VSR, the interlaced gate circuit ITG, and the driving circuit DV, and the fourth row. A selection operation of (vertical scanning line VL4, horizontal signal line HS4) is performed. As a result, in synchronization with the selection operation of the horizontal scanning lines HL1, HL2, etc. formed by the horizontal shift register HSR, the optical signal accumulated in the photodiodes D1, D2 etc. in the first row is output to the output signal line VS. It is read out serially. The read operation is performed by supplying a current corresponding to the optical signal from the terminal S via the load resistor, and the precharge (reset) operation is performed at the same time as the read operation.

The same operation is performed in the photodiode on the fourth row. In this case, the vertical scanning circuit (VSRE, ITGE, DV) for varying the sensitivity as described above is used.
According to E), the read operation of the fourth row is performed on the dummy output line DVS. When only the sensitivity control operation is performed, the same bias voltage as that of the terminal S is applied to the terminal RV. As a result, the optical signal already accumulated in each pixel cell on the fourth row is swept out, in other words, the reset operation is performed. Therefore, by the vertical scanning operation, the read operation of the fourth row (vertical scanning line VL4, horizontal signal line HS4) by the read vertical shift register VSR, the interlaced gate circuit ITG, and the drive circuit DV is the above first row. Since it is performed after the read operation of the third row, the accumulation time of the photodiodes of the pixel cells arranged in the fourth row is the read time of the pixel cells of three rows.

Instead of the above, the vertical shift register VSRE for sensitivity control, the interlaced gate circuit ITGE, and the drive circuit DVE are used to read the vertical shift register VSR for read, the interlaced gate circuit ITG, and the drive circuit DV for the first row. In parallel with the reading of (vertical scanning line VL1 and horizontal signal line HS1), the selection operation of the second row (vertical scanning line VL2, horizontal signal line HS2) is performed. Thereby, in synchronization with the selection operation of the horizontal scanning lines HL1, HL2, etc. formed by the horizontal shift register HSR,
The output signal line VS has a photodiode D in the first row.
The optical signals accumulated in 1, D2, etc. are read out in time series. The read operation is performed by supplying a current corresponding to the optical signal from the terminal S via the load resistor, and the precharge (reset) operation is performed at the same time as the read operation. Similar operation is performed in the photodiodes D3, D4, etc. in the second row. As a result, in parallel with the read operation of the first row, the sweep operation of the optical signal already accumulated in each pixel cell of the second row is performed.

Therefore, by the above vertical scanning operation,
The reading operation of the second row (vertical scanning line VL2, horizontal signal line HS2) by the reading vertical shift register VSR, the interlaced gate circuit ITG, and the drive circuit DV is performed after the reading operation of the first row. The accumulation time of the photodiodes of the pixel cells arranged in the second row is the readout time of the pixel cells for one row. As a result, the substantial storage time of the photodiode can be reduced to ⅓, in other words, the sensitivity can be reduced to ⅓, as compared with the above case.

Generally speaking, when the scanning circuit for sensitivity control performs the selecting operation of the m-th vertical scanning line VLm, the scanning circuit for reading performs the n-th vertical scanning line VLn. Sometimes there is a time difference of X (m-n) H. Here, H is the horizontal scanning time. Therefore,
Since the pixel cells of the vertical scanning line VLm are reset when the vertical scanning line VLm is scanned by the preceding vertical scanning operation, until the vertical scanning line VLm is selected again by the reading scanning circuit from the reset operation. (XH) is the storage time for the photodiode.

Although not shown in the figure, the photodiodes which are substantially out of the effective display screen as described above are not scanned by the scanning circuit for sensitivity control and are connected to the dummy output line DVS. The switch MOSFET and the like, which are switch-controlled by the signal PR, are omitted.

FIG. 4 shows a schematic block diagram of an embodiment of a video camera using the solid-state image pickup device according to the present invention. The solid-state image pickup device performs a scanning operation and a sensitivity varying operation according to a timing signal formed by a drive circuit. The output signal VO from the solid-state image sensor is transmitted to the signal processing circuit, where it is converted into the video signal VD. Although not particularly limited, the signal VO 'corresponding to the output signal VO amplified by the signal processing circuit is input to the flicker detection circuit. The flicker detection circuit extracts the output signal of the photodiode corresponding to the non-operating range of the electronic shutter from the output signal VO ′ from the solid-state image pickup device according to the gate pulse GP output from the drive circuit, and changes its signal level. To detect. The drive circuit is controlled according to the cycle of the change in the signal level to control the sensitivity of the solid-state image sensor, in other words, the electronic shutter speed is controlled to prevent the occurrence of flicker. For example, 50Hz
When shooting with a fluorescent lamp, set the shutter speed to 1
/ 100 seconds may be set.

The effects obtained from the above embodiment are as follows. (1) The signals of a plurality of two-dimensionally arrayed pixel cells in the image sensor effective pixel range are output in time series, and the image sensor effective pixel range is temporally independent of the scanning operation in the signal output function. A sensitivity variable function is provided by providing a pixel cell that does not perform signal sweeping outside the effective display screen by sweeping out the signal charge of the pixel cell of the effective display screen that is made into a smaller area. At the same time, the effect that the optical sensor can be formed inside the solid-state imaging device is obtained. (2) According to the above (1), since it is not necessary to provide an optical sensor outside, while reducing the size and weight of the video camera,
The effect is that the degree of freedom in design can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the flicker detection and the circuit for setting the electronic shutter speed of the solid-state image sensor according to the flicker detection can adopt various embodiments. Output signal VO of the solid-state imaging device
The signal corresponding to the amount of incident light included in the above can be widely used as a signal for detecting the amount of incident light as well as the signal for detecting flicker as described above.

[0034]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the signals of a plurality of pixel cells that are two-dimensionally arrayed in the image sensor effective pixel range are output in time series, and the signal is output from the image sensor effective pixel range independently of the scanning operation in the signal output function. By providing a pixel cell that does not perform signal sweeping outside the effective display screen by sweeping out the signal charge of the pixel cell of the effective display screen that is made into a small area, it is possible to provide a variable sensitivity function. Meanwhile, an optical sensor can be configured inside the solid-state image sensor.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image pickup screen showing an embodiment of a solid-state image pickup device according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a CCD type solid-state image pickup device according to the present invention.

FIG. 3 is a schematic circuit diagram showing an embodiment of a MOS type solid-state image pickup device to which the present invention is applied.

FIG. 4 is a schematic block diagram showing an embodiment of a video camera using the solid-state image sensor according to the present invention.

[Explanation of symbols]

VCCD ... Vertical CCD, HCCD ... Horizontal CCD, AMP
... amplifier, PD ... pixel array, VSR ... read vertical shift register, ITG ... read interlaced gate circuit, DV ... read drive circuit, VSRE ... sensitivity setting vertical shift register, ITGE ... sensitivity set interlaced gate circuit , DVE ... Sensitivity setting drive circuit, HS
R ... Horizontal shift register.

Claims (2)

[Claims] 1. A signal output function for outputting signals of a plurality of pixel cells arranged two-dimensionally in an effective pixel range of an image sensor and a scanning operation in the signal output function independently of each other in terms of time. A solid-state image pickup device having a function of sweeping out signal charges of pixel cells of a substantially effective display screen which is set to a range smaller than an effective pixel range. 2. The function of sweeping out the signal charge is used for varying the sensitivity, and among the signals output by the signal output function, a signal from a pixel cell which is not swept out is a flicker of a light source. The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device is used for detection.