JPS63278263A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63278263A JPS63278263A JP62005976A JP597687A JPS63278263A JP S63278263 A JPS63278263 A JP S63278263A JP 62005976 A JP62005976 A JP 62005976A JP 597687 A JP597687 A JP 597687A JP S63278263 A JPS63278263 A JP S63278263A
- Authority
- JP
- Japan
- Prior art keywords
- package
- solder
- semiconductor device
- leads
- curved end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229910000679 solder Inorganic materials 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000005476 soldering Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 4
- 239000006071 cream Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 210000005056 cell body Anatomy 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、外部リードがパッケージの裏面方向に3字状
に湾曲形成された半導体装置に適用して有効な技術に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a semiconductor device in which external leads are curved in a three-shape shape toward the back surface of a package.
外部リード(以下、単にリードという)がパッケージの
裏面方向に3字状に湾曲形成された半導体装置、いわゆ
るP L CC(Plastic Leaded Ch
ip Carrier)型の半導体装置については、例
えば日経マグロウヒル社、1984年6月11日発行、
「日経エレクトロニクス別冊・マイクロデバイセズJ、
(P148〜P153)に記載がある。A semiconductor device in which external leads (hereinafter simply referred to as leads) are curved in a three-shape toward the back surface of the package, so-called P L CC (Plastic Leaded Ch)
Regarding semiconductor devices of the ip carrier type, for example, Nikkei McGraw-Hill, published June 11, 1984,
“Nikkei Electronics Special Issue/Micro Devices J,
There is a description in (P148 to P153).
ところで、半導体装置の高集積化に伴い、基板上にパッ
ケージを高密度に実装する方式として、上記PLCCあ
るいはこれに類似した構造を有するS OJ (Sma
ll 0utline J−Lead Package
)型の半導体装置などを用いる面実装方式が多用される
ようになった。By the way, with the increasing integration of semiconductor devices, the above-mentioned PLCC or SOJ (Soma
ll 0utline J-Lead Package
)-type semiconductor devices have come into widespread use.
このPLCC型あるいはSOJ型の半導体装置を基板に
搭載するには、基板の表面にパターン形成された配線上
の所定個所に半田クリームあるいは半田ペーストを被着
してその上にパッケージを載置した後、半田リフローに
より半田付けする方法が一般的である。To mount this PLCC type or SOJ type semiconductor device on a board, solder cream or solder paste is applied to predetermined locations on the wiring patterned on the surface of the board, and a package is placed on top of it. , a common method is soldering by solder reflow.
従って、半田リフローの際、パッケージ裏面方向に3字
状に湾曲形成された複数のリードが均一に半田ペースト
と接していることが、半田付けの信頼性、いわゆる半田
付は性(ソルダビリティ)を向上させる点で重要になる
。Therefore, during solder reflow, the reliability of soldering, so-called solderability, is determined by ensuring that the multiple leads curved in a 3-shape toward the back of the package are in uniform contact with the solder paste. This is important for improving.
ところが、本発明者は上記PLCC型あるいはSOJ型
のパッケージ構造には下記のような問題があることを見
出した。However, the inventors of the present invention have found that the above-mentioned PLCC type or SOJ type package structure has the following problems.
すなわち、これらのパッケージ構造においては、パッケ
ージ側面から突出する複数のリードを均一な精度で3字
状に弯曲形成するのが困難であるために、各リードの湾
曲端部の高さにバラツキが生じ易く、そのため半田ペー
ストの上にパッケージを載置した時にリードの一部がハ
ンダペーストと接触しないことがあり、これがり=ドと
配線との間の導通不良や接合強度不足などの不都合を引
き起こす原因になっている。In other words, in these package structures, it is difficult to curve the multiple leads protruding from the side of the package into a three-shape shape with uniform precision, resulting in variations in the height of the curved end of each lead. Therefore, when the package is placed on top of the solder paste, some of the leads may not come into contact with the solder paste, which causes problems such as poor continuity between the lead and the wiring, and insufficient bonding strength. It has become.
また、上記リードの表面には例えばスズ(Sn)などの
メッキが施されているが、このリードを3字状に湾曲形
成する際、特にその湾曲端部などには過大な歪が生じ易
く、そのために湾曲端部の耐食性が低下してリードの腐
食を引き起こす原因になっている。Furthermore, the surface of the lead is plated with tin (Sn), for example, but when the lead is curved into a three-shape shape, excessive distortion tends to occur particularly at the curved end. Therefore, the corrosion resistance of the curved end portion decreases, causing corrosion of the lead.
本発明の目的は、半導体装置を基板に搭載する際の半田
付は性を向上させる技術を提供することにある。An object of the present invention is to provide a technique for improving soldering properties when mounting a semiconductor device on a substrate.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、パッケージの側面から突出する複数のリード
の各湾曲端部近傍に半田被膜を被着形成するとともに、
各湾曲端部の半田被膜を平坦化して各リードが均一に基
板表面に当接するようにした半導体装置とするものであ
る。That is, a solder film is formed near each curved end of a plurality of leads protruding from the side surface of the package, and
A semiconductor device is provided in which the solder coating on each curved end is flattened so that each lead uniformly contacts the substrate surface.
上記した手段によれば、基板の上にパッケージを載置し
た時に複数のリードが均一に基板表面に当接され、しか
も各湾曲端部近傍の半田被膜によってその半田ぬれ性が
向上する。従って、これにより、半田付は後におけるリ
ードと配線との間の導通不良や、パッケージと基板との
間の接合強度不足などの不都合が解消される。According to the above-mentioned means, when the package is placed on the substrate, the plurality of leads are brought into uniform contact with the substrate surface, and the solder wettability of the leads is improved by the solder coating near each curved end. Therefore, this eliminates problems such as poor conduction between the leads and wiring and insufficient bonding strength between the package and the board after soldering.
第1図は本発明の一実施例である半導体装置を示す断面
図、第2図は基板に載置されたこの半導体装置の要部側
面図である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a side view of essential parts of this semiconductor device placed on a substrate.
本実施例の半導体装置は、PLCC型のパッケージ構造
を有する半導体装置であって、第1図に示すように、エ
ポキシ樹脂などでモールド成形されたパッケージ2と、
銅(Cu)などの表面をスズ(STI)などでメッキ処
理した複数のリード1とにより構成されている。The semiconductor device of this embodiment is a semiconductor device having a PLCC type package structure, and as shown in FIG. 1, a package 2 molded with epoxy resin or the like,
It is composed of a plurality of leads 1 made of copper (Cu) or the like whose surface is plated with tin (STI) or the like.
上記パッケージ2の内部のほぼ中央には、所定の集積回
路が形成された半導体ペレット3が銀(Ag>ペースト
などからなる接合材(図示せず)を介してタブ4の上に
取付けられている。また、このタブ4の周囲には、上記
リード1と一体形成された複数の内部リード5が、上記
タブ4とは非接触の状態で放射状に形成され、金(Au
)などからなる導電性のワイヤ7を介して上記半導体ペ
レット3と電気的に接続されている。At approximately the center of the inside of the package 2, a semiconductor pellet 3 on which a predetermined integrated circuit is formed is attached onto a tab 4 via a bonding material (not shown) made of silver (Ag> paste or the like). Further, around this tab 4, a plurality of internal leads 5 integrally formed with the lead 1 are formed radially in a non-contact state with the tab 4, and are made of gold (Au).
), etc., and is electrically connected to the semiconductor pellet 3 via a conductive wire 7 .
一方、このパッケージ2の西側面から突出形成された複
数のリード5の各々は、パッケージ2の裏面(図の下側
)方向に3字状に湾曲形成されており、それらの湾曲端
部近傍には半田被膜1が被着形成され、かつ、このパッ
ケージ2を基板に載置したときに各リード5がそれらの
湾曲端部において均一に基板の表面に当接されるよう、
半田被膜1に平坦面1aが形成されている。On the other hand, each of the plurality of leads 5 protruding from the west side of the package 2 is curved in a 3-shape toward the back surface (lower side of the figure) of the package 2, and is located near the curved end. The solder film 1 is deposited and the leads 5 are arranged so that when the package 2 is placed on the board, the curved ends of the leads 5 are uniformly brought into contact with the surface of the board.
A flat surface 1a is formed on the solder coating 1.
この半田被膜1を形成するには、例えばパッケージ2を
半田溜にディップすればよく、これにより、複数のリー
ド5の各湾曲端部近傍に同時に半田が被着される。また
、この半田被膜1に平坦面1aを形成するには、例えば
表面が平滑な砥石の上にパッケージ2を載置して研削を
行えばよく、これにより、複数のリード5の湾曲端部の
半田被膜1が均一に平坦化される。To form this solder film 1, for example, the package 2 may be dipped in a solder pool, whereby solder is applied to the vicinity of each curved end of the plurality of leads 5 at the same time. Further, in order to form the flat surface 1a on the solder coating 1, the package 2 may be placed on a grindstone with a smooth surface and ground. The solder film 1 is uniformly planarized.
上記構成からなる半導体装置を例えばプリント配線板な
どの基板に半田付けするには、第2図に示すように基板
8の表面にパターン形成された配線9の所定個所に半田
クリーム10を被着してその上にパッケージ2を載置す
る。このとき、すべてのリード1の平坦面1aが半田ク
リーム10と均一に当接される。次いで、この基板8を
図示しないリフロー炉に搬入して半田リフローを行えば
、この半導体装置の基板8への半田付けが完了する。In order to solder the semiconductor device having the above structure to a substrate such as a printed wiring board, solder cream 10 is applied to predetermined locations of wiring 9 patterned on the surface of the substrate 8, as shown in FIG. and place package 2 on top of it. At this time, the flat surfaces 1a of all the leads 1 are brought into uniform contact with the solder cream 10. Next, this substrate 8 is carried into a reflow oven (not shown) and solder reflow is performed, thereby completing the soldering of this semiconductor device to the substrate 8.
このように、本実施例によれば以下の効果を得ることが
できる。As described above, according to this embodiment, the following effects can be obtained.
(1)、パッケージ2の側面から突出する複数のリード
5の各湾曲端部近傍に半田被膜1を被着形成するととも
に、この半田被膜1を湾曲端部において平坦化すること
により、これらのリード5を3字状に湾曲形成した際に
各リード5の湾曲端部の高さにバラツキが生じていても
、すべてのリード5が均一に基板8の表面に当接される
。従って、半田付は後におけるリード5と配線9との間
の導通不良や接合強度不足などの不都合が解消される。(1) By forming a solder film 1 near each curved end of a plurality of leads 5 protruding from the side surface of the package 2, and flattening the solder film 1 at the curved end, these leads Even if the heights of the curved ends of the leads 5 vary when the leads 5 are curved into a tri-shape, all the leads 5 are uniformly brought into contact with the surface of the substrate 8. Therefore, problems such as poor conductivity and insufficient bonding strength between the leads 5 and the wiring 9, which will occur later in soldering, are eliminated.
(2)、 !J−ド5の湾曲端部近傍に半田被膜1を
被着形成したことから、リフロ一時におけるリード50
半田ぬれ性が向上する。(2), ! Since the solder film 1 was formed near the curved end of the J-board 5, the lead 50 was easily removed during reflow.
Improves solder wettability.
(3)、 ’)−ド5の湾曲端部近傍に半田被膜1を被
着形成したことから、湾曲端部におけるリード5の腐食
を防止することができる。(3), ') - Since the solder coating 1 is formed near the curved end of the lead 5, corrosion of the lead 5 at the curved end can be prevented.
(4)、上記(1)〜(3)により、基板搭載時におけ
る半導体装置の半田付は性が向上する。(4) Due to the above (1) to (3), the soldering properties of the semiconductor device when mounted on a board are improved.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。例えば、パッケージやリ
ードの材質などは任意に変更してもよい。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the materials of the package and leads may be changed as desired.
また、以上の説明では主として本発明者によってなされ
た発明をその利用分野である、いわゆるPLCC型のパ
ッケージ構造を有する半導体装置に適用した場合につい
て説明したが、本発明はこれに限定されるものではなく
、例えばSOJ型の半導体装置にも適用することができ
る。Further, in the above explanation, the invention made by the present inventor is mainly applied to a semiconductor device having a so-called PLCC type package structure, which is the field of application thereof, but the present invention is not limited to this. For example, the present invention can also be applied to an SOJ type semiconductor device.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、パッケージの側面から突出する複数のリード
の各湾曲端部近傍に半田被膜を被着形成するとともに、
この半田被膜を湾曲端部において平坦化することにより
、基板の上にパッケージを載置した時に複数のリードが
均一に基板表面に当接される。従って、半田付は後にお
けるリードと配線との間の導通不良や、パッケージと基
板との間の接合強度不足などの不都合が解消され、半導
体装置の半田付は性が向上する。That is, a solder film is formed near each curved end of a plurality of leads protruding from the side surface of the package, and
By flattening this solder coating at the curved end, the plurality of leads can uniformly contact the substrate surface when the package is placed on the substrate. Therefore, in soldering, problems such as poor conduction between leads and wiring and insufficient bonding strength between the package and the substrate are eliminated, and the soldering properties of semiconductor devices are improved.
第1図は、本発明の一実施例である半導体装置を示す断
面図、
第2図は、基板に載置されたこの半導体装置の一8=
要部側面図である。
1・・・半田被膜、1a・・・平坦面、2・・・パッケ
ージ、3・・・半導体ペレット、4・・・タブ、5・・
・外部リード、6・・・内部リード、7・・・ワイヤ、
8・・・基板、9・・・配線、10・・・半田クリーム
。
/−学田布四
、/a−3炬面
θ−暑不ρFIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a side view of a main part of this semiconductor device mounted on a substrate. DESCRIPTION OF SYMBOLS 1...Solder film, 1a...Flat surface, 2...Package, 3...Semiconductor pellet, 4...Tab, 5...
・External lead, 6...Internal lead, 7...Wire,
8... Board, 9... Wiring, 10... Solder cream. /-Gakutafu 4, /a-3 Komian θ-Shotfu ρ
Claims (1)
前記パッケージの裏面方向に湾曲形成し、その湾曲端部
を基板表面に当接してこれを基板に半田付けする半導体
装置であって、前記複数の外部リードの各湾曲端部近傍
に半田被膜を被着形成するとともに、各湾曲端部におい
てこの半田被膜を平坦化することにより、各外部リード
が均一に基板表面に当接するようにしたことを特徴とす
る半導体装置。 2、前記半田被膜の平坦化は各外部リードの半田被着面
を平滑な研削手段で研削することにより行われることを
特徴とする特許請求の範囲第1項記載の半導体装置。[Claims] 1. A semiconductor device in which a plurality of external leads protruding from the side surface of a package are curved toward the back surface of the package, and the curved ends are brought into contact with the surface of a substrate and soldered to the substrate. By forming a solder film near each curved end of the plurality of external leads and flattening the solder film at each curved end, each external lead uniformly contacts the substrate surface. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the solder coating is flattened by grinding the solder-adhering surface of each external lead with a smooth grinding means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62005976A JPS63278263A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62005976A JPS63278263A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63278263A true JPS63278263A (en) | 1988-11-15 |
Family
ID=11625871
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62005976A Pending JPS63278263A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63278263A (en) |
-
1987
- 1987-01-16 JP JP62005976A patent/JPS63278263A/en active Pending
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