JPS63278251A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate equipping a gate array with the delay time of an analog value by a method wherein an input buffer and an output buffer are connected to a pad and an external capacitor is connected to the pad. CONSTITUTION:At an input/output part, both an input buffer 1 and an output buffer 2 are connected to a pad 3, and the input buffer 1 and the output buffer 2 are actuated simultaneously. Furthermore, an external capacitor 4 is connected to the pad 3 so that the delay time becomes available. If, in a gate array which is constituted by two or more transistors, only a part of the transistors is connected to the pad, it is possible to enhance an output impedance which drives the capacitance for delay use and to form a delay circuit whose delay time is longer.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a semiconductor integrated circuit (hereinafter referred to as a gate array) in which elements are arranged in several rows in units of logic gates and the required functions are realized by interconnecting these gates. ), it concerns how to add a delay.

[Conventional technology]

In the case of fbl f'i output, in the figure, there are III ij output buffers, (21$-j output buffers, and (31 output buffers).

Figure 8 shows a delay circuit in a general circuit, where qυ and 02J
are the buffer, Q3), and t141 are the resistance and capacitance of the delay circuit, respectively.

FIG. 4 tal is a circuit used to add a delay in the gate array.
1 is clock sword, □□□ is DA TA Hisakata, (c)
is the output of D1r/ of the first stage, (to) is the output of D% of the second stage, Figure 4 (b+ shows the waveform diagram of each person and output, and the amount shows the delay time of output - for output 4) show.

Next, the method of assigning delay time in a conventional gate array will be explained. In such a conventional gate array, in the case of the input of IJLI in Fig. 2, the input buffer 1!1
In the case of fb+ output, only the output buffer 121 is connected to the pad, so a delay circuit like the one shown in FIG. 8 cannot be created. Therefore, as shown in FIG. Using DF4 etc., first stage D
By using the output of the F/F as the input data of the second stage DF/, , the second stage output C2fH-1: has a delay time of C) relative to the first stage output (to). This is used in gate arrays, but in this case, you can only create a delay time in clock units like a box.

In addition, in order to obtain a large delay time, multi-stage DF/F
is required, and the circuit scale becomes large.

Since the configuration is as above, it is not possible to create the delay port Fl11, and it is possible to create a delay time using DF/F etc. and use it, but this delay time can only be created in clock units. do not have.

Furthermore, when adding a large delay time, there is a problem that many stages of DF/IF etc. are required, resulting in an increase in the scale of the circuit.

This invention was made in order to solve the above-mentioned problems, and in the input/output of the gate array, both the input buffer and the output buffer are connected to the pad, and the input buffer and the output buffer are operated simultaneously. Furthermore, it is an object of the present invention to provide a delay time by attaching an external capacitor to the pad.

[Means for solving problems]

Input/output in the gate array according to the present invention is achieved by connecting an input buffer and an output buffer 2 to the pad, operating the input buffer and output buffer simultaneously, and adding a delay time by attaching an external capacitor to the pad. It is something that

[Effect]

The input/output of the gate array in this invention is achieved by connecting the input buffer and the output buffer to the pad, operating the input buffer and the output buffer simultaneously, and adding a delay time by attaching an external capacitor to the pad. This is what I did.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, tE is the first delay circuit of the gate array.
Buffers constituting a circuit as shown in FIG. 1al include a +21d output buffer, 13H; an input/output pad, and 141 an external capacitor.

Next, a description will be given of how to assign the delay time of the gate array in the embodiment. In input/output, input cover m
, ffj 7a121 t'4. [Pad 131
and input buffer Fuji 1 and output buffer (2)
operate at the same time. Furthermore, a delay time can be added to the pad tel I/C by adding an external capacitor (4). This delay time is the capacity (41) and Figure 1 (
By combining the circuit impedances a and 1, an analog value can be taken.

In the above embodiment, a delay time is added by adding a capacitor externally without changing the output buffer system at all. However, as shown in FIG. In a gate array composed of transistors, when used as a delay circuit as a modified example, the delay capacitor t is driven by connecting only some of the transistors to the pads as shown in the 6th line [b+]. It is also possible to increase the output impedance of the inverter, and by configuring it in this way, a delay circuit with a long delay time can be configured.

〔Effect of the invention〕

As described above, according to the present invention, the input and output buffers of the gate array are connected to the pads, the input buffer and the output buffer are simultaneously operated with one force, and the pads are configured to have external capacitors attached to them. Therefore, there is an effect that a delay time of an analog value can be added to the gate array.

[Brief explanation of drawings]

FIG. 1 shows a delay circuit of a gate array according to an embodiment of the present invention, (al is a simplified actual layout diagram, (bl is a wiring diagram, FIG. 2 is a layout diagram of a conventional gate array, and (IL) is an input state, fbl is the output state, FIG. 8 is a conventional delay circuit diagram,
Figure 4 (&1 is a circuit diagram of DF/VC used to add delay to a conventional gate array, fbl is a delay waveform diagram created by these outputs, Figure 5
fbl is an actual layout diagram of another embodiment of the present invention. In the figure, the output buffer (31) is an input/output pad, and (4) is an external capacitor. In the figure, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a semiconductor integrated circuit in which elements are arranged in several rows in units of logic gates and the required functions are realized by interconnecting these gates, both the input buffer and the output buffer are connected to pads. , attach the capacitor externally to the pad,
A semiconductor integrated circuit characterized in that a delay is added by simultaneously operating an input buffer and an output buffer. (2) When the output transistor that constitutes the output buffer is configured by connecting multiple transistors in parallel and used as a normal output buffer, when all transistors are connected to the output terminal and used as a delay circuit. 2. The semiconductor integrated circuit according to claim 1, wherein only some of the pads are connected to the pad.