JPS63272065A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63272065A JPS63272065A JP10472887A JP10472887A JPS63272065A JP S63272065 A JPS63272065 A JP S63272065A JP 10472887 A JP10472887 A JP 10472887A JP 10472887 A JP10472887 A JP 10472887A JP S63272065 A JPS63272065 A JP S63272065A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- recessed
- grooves
- resistance
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000005121 nitriding Methods 0.000 abstract 2
- 238000001259 photo etching Methods 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に面積に比較して高抵抗
を得ることができる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device that can obtain a high resistance compared to its area.
従来、半導体装置の一素子として半導体基板に形成され
る抵抗には、半導体基板内に他の素子領域と絶縁分離し
た不純物拡散層で構成したもの、又は半導体基板上の絶
縁膜上に多結晶シリコン層を形成してこれに不純物を導
入した構成のものが提案されている。これらの抵抗は一
般に平坦かつ一様な厚さの抵抗体を半導体基板に対し水
平方向に用いるのが普通であり、したがって抵抗値は抵
抗体の長さ１幅、不純物濃度を変えることにより決定さ
れる。Conventionally, a resistor formed on a semiconductor substrate as an element of a semiconductor device is composed of an impurity diffusion layer insulated from other element regions in the semiconductor substrate, or a resistor made of polycrystalline silicon on an insulating film on the semiconductor substrate. A structure in which a layer is formed and impurities are introduced into the layer has been proposed. These resistors are generally made using a flat resistor with a uniform thickness in the horizontal direction with respect to the semiconductor substrate, so the resistance value is determined by changing the length, width, and impurity concentration of the resistor. Ru.
上述した従来の抵抗は、金属薄膜を用いた抵抗と比較し
て抵抗値の温度依存性が大きく、特に抵抗体の不純物濃
度が低い場合にその傾向が顕著に現れる。このため集積
回路上で高抵抗を必要とする場合、不純物濃度を下げて
抵抗値を上げても、その大きな温度依存性により、抵抗
体の発熱もしくは外部からの温度変化に対して抵抗値の
変動が著しく、集積回路の動作不良等の問題が生じる原
因となっている。The above-mentioned conventional resistor has a resistance value that has a greater temperature dependence than a resistor using a metal thin film, and this tendency is particularly noticeable when the impurity concentration of the resistor is low. Therefore, when high resistance is required on an integrated circuit, even if the impurity concentration is lowered and the resistance value is increased, the resistance value will fluctuate due to the heat generation of the resistor or external temperature changes due to its large temperature dependence. This is a significant cause of problems such as malfunction of integrated circuits.
このうち、抵抗体からの発熱の影響を避けるためには、
抵抗サイズを大きくすればよいが、これは集積回路の集
積度向上の点から不利である。また、温度依存性を避け
るため、不純物濃度を上げると、抵抗値を上げるために
長い抵抗体を形成する必要があり、これも集積度向上の
点から不利である。Of these, in order to avoid the effects of heat generation from the resistor,
The size of the resistor can be increased, but this is disadvantageous in terms of increasing the degree of integration of integrated circuits. Furthermore, if the impurity concentration is increased to avoid temperature dependence, it is necessary to form a long resistor to increase the resistance value, which is also disadvantageous in terms of increasing the degree of integration.
現在の集積回路における高抵抗の用途として、バイポー
ラ型或いはＭＯＳ型のスタティックＲＡＭのメモリセル
内に使用される抵抗が挙げられる。High resistance applications in current integrated circuits include resistors used in memory cells of bipolar or MOS static RAMs.
しかし、温度依存性の問題が生じない層抵抗値の限界が
約１００にΩ／曲程度であるため、集積度の向上ととも
に更に高い抵抗値が要求された場合にはこれを満足させ
ることは困難になる。However, since the limit of layer resistance without temperature dependence problems is about 100Ω/curve, it is difficult to satisfy this when even higher resistance values are required as the degree of integration increases. become.
本発明は、温度依存性の大きな低不純物濃度の拡散層を
使うことなく高抵抗の形成を可能とした半導体装置を提
供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which high resistance can be formed without using a low impurity concentration diffusion layer that is highly temperature dependent.
本発明の半導体装置は、分離絶縁膜により画成された半
導体基板の表面に凹凸の溝を形成するとともに、この凹
凸の溝の表面に不純物を拡散して溝の表面に沿って延在
する抵抗を構成し、平面面積を増大することなく抵抗の
実質長さを大きくし、高抵抗を得る構成としている。In the semiconductor device of the present invention, an uneven groove is formed on the surface of a semiconductor substrate defined by an isolation insulating film, and an impurity is diffused into the surface of the uneven groove to form a resistor extending along the surface of the groove. The structure is such that the effective length of the resistor is increased without increasing the planar area, and high resistance is obtained.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の上面図であり、第２図は第
１図のＡＡ線に沿う断面図である。FIG. 1 is a top view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA in FIG. 1.
これらの図において、シリコン基板１には公知のアイソ
プレーナ技術により分離領域である酸化膜２を形成して
いる。そして、この分離酸化膜２で囲まれたシリコン基
板１の表面には、写真蝕刻法及び反応性イオンエツチン
グによって凹凸の溝７を形成している。この凹凸の溝７
が形成されたシリコン基板１の表面には、不純物拡散法
を用いて不純物拡散層３を形成している。In these figures, an oxide film 2, which is an isolation region, is formed on a silicon substrate 1 by a known isoplanar technique. On the surface of the silicon substrate 1 surrounded by the isolation oxide film 2, uneven grooves 7 are formed by photolithography and reactive ion etching. This uneven groove 7
An impurity diffusion layer 3 is formed on the surface of the silicon substrate 1 on which the impurity diffusion method is used.
更に、この不純物拡散層３を形成したシリコン基板１の
表面にはシリコン窒化１１４を形成して不純物拡散層３
の露呈を防いでいる。そして、シリコン窒化膜４の両端
部に夫々写真蝕刻法によりコンタクト孔５を開孔し、こ
の上にアルミニウム電極６を選択的に形成して前記不純
物拡散層３に電気的な接続を行っている。Further, silicon nitride 114 is formed on the surface of the silicon substrate 1 on which the impurity diffusion layer 3 is formed, and the impurity diffusion layer 3 is formed.
prevents exposure. Then, contact holes 5 are formed at both ends of the silicon nitride film 4 by photolithography, and an aluminum electrode 6 is selectively formed thereon to electrically connect to the impurity diffusion layer 3. .
したがって、この構成によれば不純物拡散層３で構成さ
れる抵抗は、シリコン基板ｌの平面方向の長さに加えて
、凹凸の溝７の深さ方向の長さがプラスされるので、全
体としての長さは極めて長いものになる。本実施例にお
いて、溝７の深さを２μｍとし、更に溝のピッチを２μ
ｍとした場合、従来の水平方向のみに抵抗を形成した構
造に比べ、同一平面面積で約２倍の抵抗値を実現するこ
とができる。なお、溝７を深くすれば更に高抵抗化が可
能であることはいうまでもない。Therefore, according to this configuration, the resistance formed by the impurity diffusion layer 3 is the length of the silicon substrate l in the planar direction and the length of the uneven groove 7 in the depth direction, so that the resistance as a whole is is extremely long. In this example, the depth of the groove 7 is 2 μm, and the pitch of the groove is 2 μm.
m, it is possible to achieve about twice the resistance value in the same plane area compared to the conventional structure in which resistance is formed only in the horizontal direction. It goes without saying that if the groove 7 is made deeper, the resistance can be further increased.
このため、不純物拡散層３を低濃度化しても所望の高抵
抗を得ることが可能となり、また低濃度化により温度変
化による抵抗値の変動を抑制し、安定な抵抗を得ること
ができる。Therefore, even if the concentration of the impurity diffusion layer 3 is lowered, it is possible to obtain a desired high resistance, and by lowering the concentration, fluctuations in resistance value due to temperature changes can be suppressed, and stable resistance can be obtained.
第３図は本発明の他の実施例の断面図であり、上面構造
は第１図と同じである。また、第３図において第１図及
び第２図と同−又は均等な部分には同一符号を付しであ
る。FIG. 3 is a sectional view of another embodiment of the present invention, and the top structure is the same as that in FIG. 1. Further, in FIG. 3, the same or equivalent parts as in FIGS. 1 and 2 are given the same reference numerals.
第３図において、シリコン基板１には分離酸化膜２を形
成して絶縁分離領域を画成し、抵抗となるべきシリコン
基板１の表面に凹凸の溝７を形成し、その表面に不純物
拡散層３を形成している。In FIG. 3, an isolation oxide film 2 is formed on a silicon substrate 1 to define an insulating isolation region, an uneven groove 7 is formed on the surface of the silicon substrate 1 to serve as a resistor, and an impurity diffusion layer is formed on the surface. 3 is formed.
そして、この上にシリコン窒化膜４を形成して被覆し、
コンタクト孔５を開設した上でアルミニウム電極６を電
気的に接続して抵抗を構成している。Then, a silicon nitride film 4 is formed and covered on this,
A contact hole 5 is formed and an aluminum electrode 6 is electrically connected to form a resistor.
ここで、この実施例では、前記分離酸化膜２を次の工程
によって形成している。In this embodiment, the isolation oxide film 2 is formed by the following process.
即ち、反応性イオンエツチングによって凹凸の溝７をエ
ツチングするのと同時に分離酸化膜２を形成する領域を
同時にエツチングしておき、その後凹凸の溝７を形成し
た基板表面のみをシリカ等の塗布膜で表面が平坦になる
ように形成する。更に、気相成長法によるシリコン酸化
膜を厚く形成した後、分離領域のみに酸化膜が残るよう
にエッチバック法によりエツチングを行う。更に、塗布
膜のみエツチングを行えば、第３図に示すようにシリコ
ン基板１の表面に対して平坦な分離酸化膜２を得ること
ができる。That is, the region where the isolation oxide film 2 is to be formed is etched at the same time as the uneven groove 7 is etched by reactive ion etching, and then only the surface of the substrate on which the uneven groove 7 is formed is coated with a coating film of silica or the like. Form the surface so that it is flat. Furthermore, after forming a thick silicon oxide film by vapor phase growth, etching is performed by an etch-back method so that the oxide film remains only in the isolation region. Furthermore, by etching only the coating film, it is possible to obtain the isolation oxide film 2 that is flat with respect to the surface of the silicon substrate 1, as shown in FIG.
本実施例では第１実施例と同じ効果が得られるとともに
、更にアルミニウム電極６付近をより平坦化できる効果
が得られる。In this embodiment, the same effect as in the first embodiment can be obtained, and also the effect that the vicinity of the aluminum electrode 6 can be further flattened can be obtained.
以上説明したように本発明は、半導体基板の表面に凹凸
の溝を形成するとともに、この凹凸の溝の表面に不純物
を拡散して溝の表面に沿って延在する抵抗を構成してい
るので、平面面積を大きくすることなく実効的に長い抵
抗を形成することが可能となり、集積回路にける集積度
の向上に伴う高抵抗を得ることができる。As explained above, in the present invention, an uneven groove is formed on the surface of a semiconductor substrate, and impurities are diffused into the surface of the uneven groove to form a resistor extending along the surface of the groove. , it becomes possible to form an effectively long resistance without increasing the planar area, and it is possible to obtain high resistance as the degree of integration in integrated circuits increases.
第１図は本発明の一実施例の上面図、第２図は第１図の
ＡＡ線に沿う断面図、第３図は本発明の他の実施例の断
面図である。
■・・・シリコン基板、２・・・分離酸化膜、３・・・
不純物拡散層、４・・・シリコン窒化膜、５・−コンタ
クト孔、６・・・アルミニウム電極、７・・・凹凸の溝
。
第１図
第３図FIG. 1 is a top view of one embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 3 is a cross-sectional view of another embodiment of the present invention. ■...Silicon substrate, 2...Isolation oxide film, 3...
Impurity diffusion layer, 4... silicon nitride film, 5... contact hole, 6... aluminum electrode, 7... uneven groove. Figure 1 Figure 3
Claims (2)
凹凸の溝を形成するとともに、この凹凸の溝の表面に不
純物を拡散して溝の表面に沿って延在する抵抗を構成し
たことを特徴とする半導体装置。(1) An uneven groove is formed on the surface of a semiconductor substrate defined by an isolation insulating film, and an impurity is diffused into the surface of the uneven groove to form a resistor extending along the surface of the groove. A semiconductor device characterized by:
開設したコンタクト孔を通して電極と抵抗とを電気接続
してなる特許請求の範囲第１項記載の半導体装置。(2) A semiconductor device according to claim 1, wherein an insulating film is formed on the surface of the uneven groove, and the electrode and the resistor are electrically connected through contact holes formed in the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10472887A JPS63272065A (en) | 1987-04-30 | 1987-04-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10472887A JPS63272065A (en) | 1987-04-30 | 1987-04-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63272065A true JPS63272065A (en) | 1988-11-09 |
Family
ID=14388556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10472887A Pending JPS63272065A (en) | 1987-04-30 | 1987-04-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63272065A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103779335A (en) * | 2012-10-18 | 2014-05-07 | 德州仪器公司 | High-resistance thin-film resistor and method of forming the resistor |
-
1987
- 1987-04-30 JP JP10472887A patent/JPS63272065A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103779335A (en) * | 2012-10-18 | 2014-05-07 | 德州仪器公司 | High-resistance thin-film resistor and method of forming the resistor |
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