JPS6112055A - Capacity element - Google Patents

Abstract

PURPOSE:To produce a capacity element with large capacity per unit space and the minimum deterioration of withstand voltage between electrodes by a method wherein polysilicon is utilized as a lower electrode of capacity element and this electrode is selectively oxidized to form projections and recessions. CONSTITUTION:A polysilicon layer 3 as the first electrode is grown on a field oxide film on a semiconductor substrate 1 and then phosphorus is diffused therein at e.g. 930 deg.C to provide it with conductivity. After forming an oxide film 4 on the polysilicon layer 3 by means of oxidation process in the steam atmosphere at e.g. 900 deg.C, a silicon nitride film 5 is formed to be an oxidation resistant mask by means of pressure reduced vapor growing process. Later this silicon nitride film 5 is patterned to make e.g. the mask nitride film width 1.5mum and the gap 1.5mum utilizing photoresist. Next another oxide film 6 is formed at 950 deg.C. Finally the oxide films 4, 6 preliminarily formed by the preceding processes are removed by fluoric acid to bond a silicon nitride film 7 as a dielectric material by means of e.g. the pressure reduced vapor growing process and then the second electrode 8 may be formed to complete a capacity element.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention is formed on the surface of a semiconductor substrate. It relates to capacitors using thin film dielectric materials, and in particular to large area devices.

(2) Description of the prior art Conventionally, when trying to implement an analog circuit (D/A, A/D conversion circuit, operation, null amplifier) using a t1MO8 type semiconductor integrated circuit, the elements in the integrated circuit are MO8 type. Transistors, resistors, capacitors, etc. are required, but among these, the one that occupies the largest area on the chip is usually a capacitive element.

For example, if a MOSFET gate oxide film (~100 OA) is used as a dielectric to form a zopF' capacitive element on a silicon chip, the capacitance per unit area is ~3.4X10- Since there is 16F/Mm, it is approximately 6QOOOμm (equivalent to ~245μm square)
area is required. Such large area devices are not desirable from the viewpoint of high integration density of integrated circuits.

The methods conventionally attempted to improve this point have generally been to make the dielectric that constitutes the capacitive element thinner, or to
Or, by introducing a dielectric material with a high dielectric constant,
The idea was to increase the capacitance value per unit area. However, as the dielectric of the capacitive element becomes thinner, the withstand voltage between the capacitive electrodes decreases and the leakage current between the capacitive electrodes increases, resulting in the inconvenience of deteriorating the charge retention characteristics. arise.

In addition, even though it is called a dielectric material with a high dielectric constant, silicon nitride film (3i3N4.g = approximately 7) can be used if compatibility with the current silicon wafer process is taken into account. The introduction of a dielectric material having a dielectric constant has not yet been put to practical use. An object of the present invention is to provide a capacitive element. .

(4) Structure of the Invention The present invention provides a first polysilicon electrode formed on a semiconductor substrate via a thick insulating film, at least one similar dielectric material formed on the first polysilicon electrode, Second
In a capacitive element made of at least one similar conductive material that acts as an electrode, forming irregularities on the first electrode by selectively oxidizing the surface of the first polysilicon electrode. It is characterized by

(5) Principle and operation of the invention By providing unevenness on the first polysilicon electrode, the opposing area between the electrodes is made larger than the flat area, thereby increasing the capacitance per unit area.

(6) Embodiments of the present invention Next, embodiments of the present invention will be described with reference to one drawing.

FIGS. 1 to 4 are cross-sectional views showing embodiments of the present invention in the order of manufacturing steps.

In the actual manufacturing process, MOS
Since the FET, the capacitor, and the resistive element are formed at the same time, the process is complicated, but only the process for forming the capacitive element will be shown here.

In FIG. 1, a thick field oxide film 2 having a thickness of about 1.0 μm is formed on a semiconductor substrate 1. As shown in FIG. This process can also be used as a field oxidation process for element isolation in a normal MOS process.

Next, a polysilicon layer 3t, which will become a first electrode, is grown to a thickness of 1.0 μm on the field oxide film, and in order to provide conductivity, phosphorus is diffused at, for example, 930″O for 20 minutes, and the polysilicon layer is The sheet resistance is approximately 20Ω/mouth.

In FIG. 2, for example, 90
After oxidizing in a 0° C. steam atmosphere to form an oxide film 4 with a thickness of 500 A, a silicon nitride film 5y1oooi is grown as an oxidation-resistant mask by low pressure vapor phase growth. After that, this silicon nitride film 5 is coated with a 7-photoresist 51, for example, the mask nitride film width is 1.5 μm and the interval is 1.5 μm.
Pattern it so that it becomes m.

In FIG. 3, selective oxidation is performed in a 950 DEG C. steam atmosphere to form an oxide film 6 of 10 .mu.m. This oxide film also includes the prone oxide film 4 shown in FIG.

At this time, do in Figure 1 is the oxide film thickness, and dl is the distance from the polysilicon surface in the non-oxidized region to the polysilicon surface in the oxidized region, and usually d1 to -d
It is 0.

In the case of this example, do=1.3μm, but d
t = 0.5 μm.

In FIG. 4, the oxide film formed in the previous step is removed using hydrofluoric acid or the like, and a silicon nitride film 7 is deposited as a dielectric material, for example, by low pressure vapor deposition.

Thereafter, by forming the second electrode 8', the capacitive element is completed.

In this example, for the purpose of simplifying the explanation, the step of forming an interlayer insulating film for wiring between the electrodes of the capacitive element, the process of forming contact holes, and the step of forming wiring using AI, etc. are omitted. .

Now, when using one performance song, per unit area of capacitive element]
The capacity is about 1.3 times that of the conventional flat structure. This is due to the unevenness on the first polysilicon electrode, and the opposing distance between the electrodes is 1
This is because the pitch increased by 2Xdl=1.0 μm. To expect a greater effect, 1. For example, the film thickness during selective oxidation shown in FIG. 3 should be made thicker.

Alternatively, slight modifications such as reducing the pattern pitch of the oxidation-resistant mask silicon nitride film in FIG. 2 may be made.

According to one aspect of the present invention, as shown in FIG.

The uneven step portion on the first polysilicon electrode is not a sharp step, but a step with a slight taper, which is a characteristic of the one-selective oxidation method. This thing.

For example, if the dielectric material is made thinner in order to increase the capacitance per unit area, it is possible to alleviate the electric field concentration at the corner of the first stage and prevent deterioration of the withstand voltage between the electrodes of the capacitive element. can.

(7) Effects of the Invention As explained above, the present invention uses polysilicon as the lower electrode of a capacitive element, and forms unevenness by performing selective oxidation on this electrode, thereby increasing the surface area per unit area. A capacitive element with large capacity and less deterioration in voltage resistance between electrodes can be realized.

[Brief explanation of the drawing]

FIGS. 1 to 4 are cross-sectional views showing the entire manufacturing process of an embodiment of the present invention in order. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2, 4, 6... Gastric oxide film, 3... First polysilicon electrode, 5...
. . . Mask silicon nitride film, 7 . . . Dielectric silicon nitride film, 8 . . . Second polysilicon electrode.

Claims (2)

[Claims] (1) A first polysilicon electrode formed on a semiconductor substrate via a thick insulating film, at least one similar dielectric material formed on the first polysilicon electrode, and a second electrode. 1. A capacitive element made of at least one type of conductive material, characterized in that the first polysilicon electrode has irregularities on its surface. (2) The irregularities on the surface of the first polysilicon electrode are
2. The capacitive element according to claim 1, wherein the capacitive element is formed by selectively oxidizing polysilicon.