JPS63272047A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63272047A JPS63272047A JP10461787A JP10461787A JPS63272047A JP S63272047 A JPS63272047 A JP S63272047A JP 10461787 A JP10461787 A JP 10461787A JP 10461787 A JP10461787 A JP 10461787A JP S63272047 A JPS63272047 A JP S63272047A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- oxide film
- pad
- film
- nitride layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 10
- -1 nitrogen ions Chemical class 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 6
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000002513 implantation Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の製造方法に係り、特ＫＸ子分離領
域の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a KX isolation region.
従来、この種の素子分離領域の形成方法は、エルゼーク
ーイ等によって発表され比選択酸化法（ＬＯＣＯ８法）
を゛採用した「１９８４年電気化学学会８９８号、抜粋
８４−１．ＭＯ８型ＶＬＳｉ７）ポリシリコン緩衝層に
よる絶縁層形成方法第３３４〜３３９頁、ニー・ピンハ
ン、ピングマ共ＩＦＪ １ｃｉＡ示されるものがあり、
これを第２図（ａ）乃至（ｆ）に従来方法の工程図を示
して説明する。Conventionally, a method for forming this type of element isolation region is the specific selective oxidation method (LOCO8 method) published by Elzekooy et al.
"1984 Electrochemical Society of Japan No. 898, Excerpt 84-1. MO8 type VLSi7) Insulating layer formation method using polysilicon buffer layer, pp. 334-339, Ni Pinghan, Pingma IFJ 1ciA ,
This will be explained with reference to FIGS. 2(a) to 2(f) showing process diagrams of the conventional method.
先ず、第２図（ａ）に示す如く、Ｐｆｉ（１００）シリ
コン基板（以下基板という）ｌ上に尚０！酸化雰囲気中
にて／々ラッド化膜（Ｓｉｎｇ） ２ ｋ ５００λ成
黄形成する。次に、第２区（ｂ）に示す如く、該パッド
酸化膜２上にＬＰ−ＣＶＤ法を以て、パッドシリコン膜
３を１５００＾成長堆積する。そして、第２図（ｃ）に
示す如く、該ノ譬ツドシリコンｇＸ３上に、同様ノＬＰ
−ＣＶＤ法を用いて、シリコン窒化膜４ｔ−１５００λ
堆積し友後、ホトリソグラフィー技術を以て、素子領域
（アクティグ領域）と素子分離憤域（フィールド領域）
とを形成する九めのレソストｄターニングを行なう＠し
かる後、第２図（ｄ）に示す如く、このレソストをマス
クとして、前記パッドシリコン膜３及びシリコン窒化膜
４ｆ、エツチングし、開口部５を形成後、反転防止用の
チャネルストップイングラを、例えばＢ＋の加速′底圧
４０ＫｅＶ。First, as shown in FIG. 2(a), 0! A radd film (Sing) 2k 500λ is formed in an oxidizing atmosphere. Next, as shown in the second section (b), a pad silicon film 3 is grown to a thickness of 1500^ on the pad oxide film 2 by the LP-CVD method. Then, as shown in FIG. 2(c), a similar LP was applied on the similar silicon gX3.
- Using CVD method, silicon nitride film 4t-1500λ
After the deposition, the element area (activating area) and element isolation area (field area) are created using photolithography technology.
Then, as shown in FIG. 2(d), using this resist as a mask, the pad silicon film 3 and silicon nitride film 4f are etched to form the opening 5. After formation, a channel stopper for preventing reversal is applied, for example, at a B+ acceleration bottom pressure of 40 KeV.
注入量Ｉ Ｘ １０１３ｔｏｎｓ／ｃｄの条件において
行ない、不純物イオン注入層６を形成する。次いで、第
２図（６）に示す如く、前記基板上の不純物イオン注入
層６上に、１ｏｏｏ℃湿式高温酸化雰囲気中における酸
化を２時間８度行ない、フィールド酸化膜７を６０００
＾成長形成する。しかる後、第２図（ｆ）に示す如く、
前記シリコン窒化１１ｇ４を熱リン酸によシ除去し、続
いて前記パッドシリコン膜３をドライ若しくはウェット
エツチング除去し友後、前記・セット酸化膜２をフッ酸
溶液によりウェットエツチング除去する。斯くして、素
子領域人並びにフィールド酸化膜７を有する素子分離領
域Ｂを夫々形成していた。The impurity ion implantation layer 6 is formed by performing the implantation under the condition that the implantation amount is I x 1013 tons/cd. Next, as shown in FIG. 2(6), the impurity ion-implanted layer 6 on the substrate is oxidized 8 times for 2 hours in a wet high temperature oxidation atmosphere of 100°C to form a field oxide film 7 of 6000°C.
^Grow and form. After that, as shown in Figure 2(f),
The silicon nitride film 11g4 is removed using hot phosphoric acid, and then the pad silicon film 3 is removed by dry or wet etching. After that, the set oxide film 2 is removed by wet etching using a hydrofluoric acid solution. In this way, the element region and the element isolation region B having the field oxide film 7 were formed.
然し乍ら、上述し几従米の素子分離領域の形成方法にお
いては％第２図（ｆ）に示す如く、フィールド酸化膜７
の仕上り形状に段差部７ａが生じるため、後工程で形成
するポリシリコン、シリサイド及びアルミニウム寺の配
線材料が前記段差部７ａによって切れる、所謂段切れに
よシオープンになったり、或いはこれらの材料等金・イ
タ−ニア りｆるホトリソグラフィ一工程において、段
差部７ａでのフォーカスが合い難く所望寸法にならない
という問題点があった。勿論前記段差部７ａを低減する
ために、前記パッド酸化ｊ漠２を厚膜にすると共に、ノ
クツドシリコン腺３ｔ−４膜にするか、若しくはシリコ
ン窒化膜４を薄膜にすれば良いが、これではＬＯＣＯ８
法におけるバーズビークの発生により素子分離領域Ｂが
増大し、半導体集積回路の高集積化を妨げることになる
。However, in the method for forming the element isolation region described above, as shown in FIG. 2(f), the field oxide film 7 is
Because the stepped portion 7a is formed in the finished shape, the polysilicon, silicide, and aluminum wiring materials to be formed in a later process may be cut by the stepped portion 7a, or become open due to so-called step breakage, or these materials, etc. In one step of photolithography using gold/Itania resin, there was a problem in that it was difficult to focus on the stepped portion 7a and the desired size could not be obtained. Of course, in order to reduce the stepped portion 7a, the pad oxide film 2 may be made thicker, and the silicon nitride film 4 may be made thinner. So LOCO8
Due to the occurrence of bird's beak in the method, the element isolation region B increases, which impedes higher integration of semiconductor integrated circuits.
本発明の目的は上述の問題点に鑑み、フィールド酸化膜
の段差部寺の発生を防止して、前記フィールド酸化膜を
所定形状に形成できる半導体素子の製造方法を提供する
ものである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the occurrence of stepped portions of a field oxide film and form the field oxide film into a predetermined shape.
本発明は上述し比重的を達成するため、シリコン基板ｌ
上にノ９ツド酸化膜２及びノ９ツドシリコン膜３を順次
形成する工程と、該パッドシリコン膜３内に窒素イオン
を注入して、前記／９ツドシリコン膜３の表面寄りに窒
化シリコン層４を形成する工程と、少なくとも該窒化シ
リコン層４をエツチングして、開口部５を形成する工程
と、高温酸化雰囲気において、前記開口部５にフィール
ド酸化膜７を成長形成する工程と、その後、前記窒化シ
リコン層４．前記／４′ツドシリコン膜３及び前記ノ９
ッド酸化膜２ｔ−エツチング除去する工程とを含むもの
である。In order to achieve the above-mentioned specific gravity, the present invention
A process of sequentially forming a 9-sided oxide film 2 and a 9-sided silicon film 3 thereon, and implanting nitrogen ions into the pad silicon film 3 to form a silicon nitride layer 4 near the surface of the 9-sided silicon film 3. a step of etching at least the silicon nitride layer 4 to form an opening 5; a step of growing a field oxide film 7 in the opening 5 in a high temperature oxidizing atmosphere; Silicon layer 4. Said /4' silicon film 3 and said No. 9
This process includes a step of removing the pad oxide film 2t by etching.
本発明においては、シリコン基板上に予め形成し九バン
ドシリコン膜内に窒素イオンを注入して。In the present invention, nitrogen ions are implanted into a nine-band silicon film previously formed on a silicon substrate.
その表面寄りに窒化シリコン層を形成するので、該窒化
シリコン層の窒素イオンは前記ノ臂ツドシリコン、膜に
近づくに従って低缶度となる。又、前記・９ツドシリコ
ン膜は、次工程で形成し几開口部のフィールド酸化膜成
長時における横方向への拡散を抑制すると共に、前記・
々ラドシリコン膜及び窒化シリコン層の開口部側は酸化
剤を消費し酸化シリコン膜に転じる。Since the silicon nitride layer is formed closer to the surface, the concentration of nitrogen ions in the silicon nitride layer decreases as it approaches the arm silicon layer. In addition, the 9-doped silicon film is formed in the next step to suppress lateral diffusion during the growth of the field oxide film in the opening, and
The opening side of the rad silicon film and silicon nitride layer consumes the oxidizing agent and turns into a silicon oxide film.
本発明の半導体素子の製造方法に係る一実施例を第１図
（ａ）乃至げ）に基づいて従来例と四−構成部分には同
一符号を付して説明する。尚、第１図（ａ）乃至（ｆ）
は本発明方法の工程図である。An embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. In addition, Fig. 1 (a) to (f)
1 is a process diagram of the method of the present invention.
先ず、第１図（ａ）に示す如く％Ｐ型（１００）シリコ
ン基板（以下基板という）１上に、高温酸化雰囲気中に
おいて、・セット酸化膜２ ｔ ３ｏｏＡ成長形成する
。次に、第１図（ｂ）に示す如く、ＬＰ−ＣＶＤ法を以
て、前記パッド酸化膜２上にノ臂ツドシリコン膜３を１
２００＾堆積する。その後、第１図（ｃ）に示す如く、
該ノ９ツドシリコン膜３内に、加速′螺圧２０ＫｅＶ、
注入ｉｌｌ Ｘ １０１７ｉｏｎｓ／ｃｊ ノ条件Ｋｊ
！ＤＷ！４オンを注入する。而して、該窒素イオンとシ
リコン原子とは反応して、前記・臂ツドシリコン膜３の
表面寄りに窒化シリコン層４が形成される。ところで、
この窒化シリコン層４は必ずしも化学量論的（即ちＳｔ
、Ｎ、）ではなく、更に、前記パッドシリコン膜３には
加速′電圧が設定され、前記窒素イオンが飛程を有する
友め、前記窒化シリコン層４は・ぐラドシリコン膜３の
裏面に近づくに伴い、窒素原子が少ない化合物となる。First, as shown in FIG. 1(a), a set oxide film 2t3ooA is grown on a %P type (100) silicon substrate (hereinafter referred to as substrate) 1 in a high temperature oxidizing atmosphere. Next, as shown in FIG. 1(b), a silicon layer 3 is formed on the pad oxide film 2 using the LP-CVD method.
Deposit 200^. After that, as shown in Figure 1(c),
In the 9-sided silicon film 3, an acceleration screw pressure of 20 KeV,
Injection ill X 1017ions/cj conditions Kj
! DW! Inject 4 on. The nitrogen ions and silicon atoms react to form a silicon nitride layer 4 near the surface of the arm silicon film 3. by the way,
This silicon nitride layer 4 is not necessarily stoichiometric (i.e., St
, N, ), an accelerating voltage is set on the pad silicon film 3, and the nitrogen ions have a range, so that the silicon nitride layer 4 approaches the back surface of the pad silicon film 3. This results in a compound with fewer nitrogen atoms.
そして、第１図（ｄ）に示す如く、ホトリソグラフィに
よってパターニングされた図示略すレジストをマスクと
して、前記の窒化シリコン層４及びパッドシリコン膜３
ｔ−エツチングして、開口部５を形成する。続いて、基
板ｌの前記開口部５側に反転防止用のチャネルストラグ
イングラを、例えばＢ＋の加速電圧４０ＫｅＶ。Then, as shown in FIG. 1(d), the silicon nitride layer 4 and pad silicon film 3 are removed using a resist (not shown) patterned by photolithography as a mask.
T-etch to form openings 5. Subsequently, a channel straggler for preventing inversion is placed on the opening 5 side of the substrate 1 at a B+ acceleration voltage of 40 KeV, for example.
注入Ｍ Ｉ Ｘ １０１３ｔｏｎｓ／−の榮件の下で行
ない、不純物イオン注入層６ｔ−形成した後、前記レジ
ストを除去する。しかる後、第１図（ｅ）に示す如＜、
１０００℃湿式高温酸化雰囲気中において、２時間程度
の酸化全行ない、前記不純物イオン注入層６上に２イー
ルド酸化膜７ ｆｃ６０００＾成長形成する。その後。After the impurity ion implantation layer 6t- is formed by implantation under the conditions of 1013 tons/- of MI, the resist is removed. After that, as shown in FIG. 1(e),
The entire oxidation is carried out for about 2 hours in a wet high temperature oxidation atmosphere of 1000° C., and a 2-yield oxide film 7 fc6000^ is grown on the impurity ion implanted layer 6. after that.
第１図（ｆ）に示す如く、前記窒化シリコン層４ｔ−熱
リン酸によりエツチング除去しｔ後、前記パッドシリコ
ン膜３及び前記・卆ツド酸化膜２を順次ウェット或いは
ドライエツチングを以て、除去する。As shown in FIG. 1(f), after the silicon nitride layer 4t is removed by etching with hot phosphoric acid, the pad silicon film 3 and the solid oxide film 2 are sequentially removed by wet or dry etching.
斯くして、前記基板１が露出した素子領域へ及びフィー
ルド酸化膜７が形成された素子分ｍ幀域Ｂが夫々形成さ
れる。In this way, a device-sized area B is formed in the device region where the substrate 1 is exposed and in which the field oxide film 7 is formed.
尚、パッドシリコン膜３は、真空蒸着法や高周波放電プ
ラズマＣＶＤ法又は光ＣＶＤ法によるアモルファスシリ
コンでも良い。父、開口部５の形成時において、パッド
酸化１漠２又は基板１′ｆ、エツチングしでも良く、逆
に窒化シリコン層４のみエツチングしても良い。更に、
／リーニングされた輩化シリコン層４をマスクとして下
層１ｆＭをエツチングしても良い。Note that the pad silicon film 3 may be made of amorphous silicon formed by vacuum evaporation, high-frequency discharge plasma CVD, or photo-CVD. When forming the opening 5, the pad oxide layer 2 or the substrate 1'f may be etched, or conversely, only the silicon nitride layer 4 may be etched. Furthermore,
The lower layer 1fM may be etched using the stripped silicon layer 4 as a mask.
以上ｆｆ細に説明し文様に本発明によれば、シリコン基
板上にパッド酸化膜及びノ臂ツドシリコン膜を順次形成
した後、前記・９ツドシリコン膜内に窒素イオンを注入
して窒化シリ；ン層を形成後、次工程で形成し次間口部
にフィールドは化換金成長形成するので、該窒化シリコ
ン層の組成なシリコン基板に近づくに従って、窒素イオ
ン低密度且つシリコン高密度となる之め、応力の緩和が
できる。As described above in detail, according to the present invention, after sequentially forming a pad oxide film and a pad silicon film on a silicon substrate, nitrogen ions are implanted into the 9-pad silicon film to form a silicon nitride layer. After forming the silicon nitride layer, the field is formed in the next step by chemical conversion growth, so as the composition of the silicon nitride layer gets closer to the silicon substrate, the nitrogen ion density becomes lower and the silicon density becomes higher. It can be relieved.
よって、前記シリフン基板における結晶欠陥の発生が防
止でき、半導体素子特性が向上できる・又。Therefore, the occurrence of crystal defects in the silicon substrate can be prevented, and the characteristics of the semiconductor device can be improved.
前記・セットシリコン膜は、フィールド酸化膜成長時の
横方向への拡散を抑制すると共に、前記開口部側の・ぞ
ラドシリフン膜は酸化剤を消費し、酸化シリコン膜に転
じるため、フィールド酸化膜における横方向へのバーズ
ビークの発生が防止できると共に、変換差（仕上り寸法
とパターニング寸法との差）が低減でき、半導体集積回
路の尚密度化ができる。更に、開口部側の前記・９ツド
シリコン膜に近い窒化シリフン層もフィールド酸化膜形
成時において酸化されるので、滑らかな形状のフィール
ド酸化膜を形成できるため、後工程における配線材料の
段切れ防止ができると共に、ホトリングラフィにおける
ディフォーカスが防止できる等の特有の効果より前述の
問題を解決し得る。The set silicon film suppresses lateral diffusion during field oxide film growth, and the set silicon film on the opening side consumes oxidizing agent and turns into a silicon oxide film, so The occurrence of bird's beak in the lateral direction can be prevented, and the conversion difference (difference between finished dimension and patterning dimension) can be reduced, and the density of semiconductor integrated circuits can be further increased. Furthermore, since the silicon nitride layer near the 9-doped silicon film on the opening side is also oxidized during the formation of the field oxide film, it is possible to form a field oxide film with a smooth shape, which prevents disconnection of the wiring material in the subsequent process. In addition, the above-mentioned problem can be solved due to its unique effects such as being able to prevent defocusing in photolithography.
第１図（ａ）乃至（ｆ）は本発明方法に係る一実施例を
示す工程図、第２図（ａ）乃至Ｃりは従来方法の工程幽
である。
１・・・シリコン基板（基板）、２・・・パッド酸化膜
、３・・・パッドシリコン膜、４・・・窒化シリコン層
、５・・・開口部、６・・・不純物イオン注入層、７・
・・フィールド酸化膜。
第１図
第２ｖＡ
第２図FIGS. 1(a) to (f) are process diagrams showing one embodiment of the method of the present invention, and FIGS. 2(a) to (C) are process diagrams of the conventional method. DESCRIPTION OF SYMBOLS 1... Silicon substrate (substrate), 2... Pad oxide film, 3... Pad silicon film, 4... Silicon nitride layer, 5... Opening, 6... Impurity ion implantation layer, 7.
...Field oxide film. Figure 1 Figure 2vA Figure 2
Claims (1)
を順次形成する工程と、 該パッドシリコン膜内に窒素イオンを注入して、前記パ
ッドシリコン膜の表面寄りに窒化シリコン層を形成する
工程と、 少なくとも該窒化シリコン層をエッチングして、開口部
を形成する工程と、 高温酸化雰囲気において、前記開口部にフィールド酸化
膜を成長形成する工程と、 その後、前記窒化シリコン層、前記パッドシリコン膜及
び前記パッド酸化膜をエッチング除去する工程とを含む
ことを特徴とする半導体素子の製造方法。[Claims] A step of sequentially forming a pad oxide film and a pad silicon film on a silicon substrate, and implanting nitrogen ions into the pad silicon film to form a silicon nitride layer near the surface of the pad silicon film. a step of etching at least the silicon nitride layer to form an opening; a step of growing a field oxide film in the opening in a high temperature oxidizing atmosphere; A method for manufacturing a semiconductor device, comprising the step of etching away a silicon film and the pad oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10461787A JPS63272047A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10461787A JPS63272047A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63272047A true JPS63272047A (en) | 1988-11-09 |
Family
ID=14385403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10461787A Pending JPS63272047A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63272047A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04155829A (en) * | 1990-10-18 | 1992-05-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1987
- 1987-04-30 JP JP10461787A patent/JPS63272047A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04155829A (en) * | 1990-10-18 | 1992-05-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
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