JPS5950542A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5950542A
JPS5950542A JP16166082A JP16166082A JPS5950542A JP S5950542 A JPS5950542 A JP S5950542A JP 16166082 A JP16166082 A JP 16166082A JP 16166082 A JP16166082 A JP 16166082A JP S5950542 A JPS5950542 A JP S5950542A
Authority
JP
Japan
Prior art keywords
formed
substrate
film
si
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16166082A
Inventor
Yasuo Matsumoto
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16166082A priority Critical patent/JPS5950542A/en
Publication of JPS5950542A publication Critical patent/JPS5950542A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Abstract

PURPOSE:To increase the performance and integration degree by a method wherein the influence by the impurity diffusion of a field inversion preventing region is eliminated by compensating the area of an element forming region for its reduction, and then the upper surface of a field oxide film and the surface of the element forming region are formed nearly into the same flat. CONSTITUTION:A thermal oxide film 12 is formed by thermally oxidizing a P type Si substrate 11. An Si nitride film 13 is deposited as an oxidation resistant film, and a photo resist pattern 14 is formed. An Si nitride film 13' is formed by selectively etching and removing the Si nitride film 13. Next, boron ion implanted layers 15 are formed. Field oxide films 16 are formed by performing thermal oxidation. The P<+> type field inversion preventing regions 17 are formed thereunder. The substrate 11 is exposed by etching treatment. A P type single crystal Si layer 18 is so deposited on an island form part of the substrate 11 as to be at the same height as the upper surface of the field oxide films 16.
JP16166082A 1982-09-17 1982-09-17 Manufacture of semiconductor device Pending JPS5950542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16166082A JPS5950542A (en) 1982-09-17 1982-09-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16166082A JPS5950542A (en) 1982-09-17 1982-09-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5950542A true JPS5950542A (en) 1984-03-23

Family

ID=15739405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16166082A Pending JPS5950542A (en) 1982-09-17 1982-09-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5950542A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639526A (en) * 1986-06-30 1988-01-16 Tonen Sekiyukagaku Kk Manufacture of bumper for motorcar
JPH02309665A (en) * 1989-05-25 1990-12-25 Agency Of Ind Science & Technol Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639526A (en) * 1986-06-30 1988-01-16 Tonen Sekiyukagaku Kk Manufacture of bumper for motorcar
JPH02309665A (en) * 1989-05-25 1990-12-25 Agency Of Ind Science & Technol Semiconductor device and manufacture thereof

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