JPS63271974A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To render a threshold voltage stable and small in dispersion by a method wherein a second compound semiconductor layer is interposed between a first compound semiconductor layer and a gate.extension which compose an n-type semiconductor layer. CONSTITUTION:A non-doped GaAlAs layer 10 is interposed between a gate extension 8a and a non-doped GaAs layer 9, wherefore the effect of electric field on a channel region owing to the gate.extension 8a is alleviated, so that the current density of the end of an n-type GaAs layer 3 can be prevented from decreasing. And, as the gate.extension 8a is left unremoved to control the potential of the non-doped GaAs layer just thereunder so as to be smaller than that of a bulk, consequently the current side leakage to the non-doped GaAs layer 9 side is prevented. By these processes, the narrow channel effect can be alleviated, and even if a channel becomes narrower in width, a threshold voltage can be kept constant and small in dispersion.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a Schottky junction field effect transistor using a compound semiconductor. In particular, the present invention relates to a method of manufacturing a field effect transistor that alleviates the narrow channel effect and suppresses an increase in threshold voltage due to a decrease in channel width.

2. Prior Art An example of the manufacturing process of a conventional field effect transistor is GaA.
The s-substrate is shown as an example (FIGS. 4(A)-(C)). A photoresist 2 is applied on a semi-insulating GaAs substrate 1, and a window is formed in a portion where an n-type GaAs layer is to be formed by photolithography. Ion implantation was performed using photoresist 2 as a mask to form an n-type Ga
As layer 3 is formed (A). After removing the photoresist 2, a photoresist 5 is formed by opening the n medium-sized GaAs layer 4 by photolithography in the same manner as the n-type GaAs layer 3.
B), and the source electrode 6 and drain electrode 7 are formed in this part by ohmic contact. Then, a gate electrode 8 is formed between the source electrode 6 and the drain electrode 7 (C). FIG. 5 is a three-dimensional diagram of a field effect transistor manufactured in this manner.

Problems to be Solved by the Invention However, the field effect transistor formed in this manner has a narrow channel effect in which the threshold voltage increases as the channel width decreases. FIG. 6 is a characteristic curve diagram showing an increase in threshold voltage when the channel width is between 10 μm and 1 μm in the conventional example described above. The threshold voltage changes rapidly as the channel width decreases from 3 μm to 1 μm.

Therefore, there are two problems when using conventional field effect transistors. One problem is that in areas where the channel width is narrow, the threshold voltage varies greatly due to slight manufacturing variations in the channel width. One more
The first problem is that the threshold voltages of field effect transistors with different channel widths on the same substrate are not equal.

The reason why the narrow channel effect occurs, which causes the two problems mentioned above, will be explained below. In field effect transistors, the gate electrode is formed of an n-type GaAs layer 3 as shown in FIG. 4 for mask alignment margin and gate width.
The width is wider than that, and protrudes several μm onto the semi-insulating GaAs substrate 1. The portion of the gate electrode that protrudes beyond this n-type GaAs layer 3 is covered with a gate extension
e extension) 8a is responsible for the narrow channel effect. That is, the potential of the surfaces of the n-type GaAs layer 3 and the semi-insulating GaAs substrate 1 that are in contact with the gate electrode 8 is low (clipped) due to the potential applied to the gate electrode 8 and the Schottky barrier. The internal potential of the semi-insulating GaAs substrate directly under the gate extension 8a is also low due to the surface potential.Then, the low potential inside this semi-insulating GaAs substrate becomes n-type GaAs substrate.
The potential at the edge of the As layer 3 is lowered. Then, the current density becomes extremely low at the edge of the n-type GaAs layer 3. Therefore, although the end of the channel is a channel, almost no current flows through it. When the channel width is wide, whether or not current flows at the edge of the channel does not have a large effect on the total current flowing through the channel, but when the channel width is narrow, the total current decreases compared to when it is wide. Therefore, the current is easily turned off, and the threshold voltage increases.

As described above, the cause of the narrow channel effect is the electric field exerted on the channel region by the gate extension.

Therefore, ideally, (gate extension) = 0
It is desirable that the width be μm, that is, (radius of gate electrode) = (width of n-type GaAs layer).

However, when the width of the gate electrode becomes narrower than the width of the n-type GaAs layer, current flows at the edge of the n-type GaAs layer, resulting in poor operation of the field effect transistor.

Therefore, in consideration of manufacturing deviations, it was necessary to provide a gate extension as a mask alignment margin.

Furthermore, even if the problem of manufacturing accuracy is solved, n
type GaAs layer causes diffusion in the horizontal direction, so the actual n
The width of the type GaAs layer is wider than the width on the mask. Therefore, even if the gate is precisely formed using a mask, a side leakage current will flow near the boundary between the non-doped GaAs layer and the n-type GaAs layer. Therefore, the gate width is n-type G
It must be wider than the width of the aAs layer and requires a gate extension.

Furthermore, in order to connect the gate to the outside of the field effect transistor, it is necessary to provide a gate extension, and this extension serves as a gate extension.

In view of this point, the present invention alleviates the narrow channel effect and prevents the threshold voltage from changing even if the channel width becomes narrow ((,
It is an object of the present invention to provide a method for manufacturing a field effect transistor with small variations.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention includes a step of forming a semi-insulating second compound semiconductor layer on the first compound semiconductor layer, and a step of forming a semi-insulating second compound semiconductor layer on the first compound semiconductor layer. forming a third film on the layer; forming a desired opening in the third film; and selectively etching the second compound semiconductor layer using the third film as a mask. a step of implanting ions into the first compound semiconductor layer using the third film and the second compound semiconductor layer as a mask to selectively form an n-type semiconductor layer; The method includes a step of forming the semiconductor layer so that the semiconductor layer and both ends of the semiconductor layer extend to the second compound semiconductor layer.

According to the above-described structure, the present invention sandwiches a semi-insulating second compound semiconductor layer between the first compound semiconductor layer and the gate extension, thereby weakening the influence of the electric field exerted by the gate extension on the channel region. (This alleviates the narrow channel effect. Also, by optimizing the thickness of the second compound semiconductor layer, side leakage current is prevented.

Example As an example of the present invention, the first compound semiconductor layer is made of Ga.
The case where the second compound semiconductor layer is made of GaA 1As, and the third film is made of photoresist will be shown.

FIGS. 1A to 1C schematically show a method for manufacturing a field effect transistor.

First, non-doped GaAs is deposited on a semi-insulating GaAs substrate 1.
Layer 9 is grown, and undoped GaAlAs is grown on top of it.
Grow layer 10. Then, a photoresist 2 is applied, and a window is formed in a portion where n-type GaAs is to be formed by photolithography (A).

Then, using this photoresist 2 as a mask, for example CCl.
GaAl was etched by plasma etching using 2F2 gas.
Only the As layer 10 is selectively etched, and GaA I
A window is also formed in the As layer 10 at a portion where an n-type GaAs layer is to be formed. Then, ion implantation is performed using the photoresist 2 and the GaAlAs layer 10 as a mask to form an n-type GaAs layer 3 in self-alignment with the GaAlAs layer 10 (B).

After removing the photoresist 2 and providing an n-type GaAs layer to form a source electrode and a gate electrode, the gate electrode 8 is made of n-type GaAs using, for example, a lift-off method.
On layer 3 and both ends (gate extension) 8a
is formed so as to extend on the GaAlAs layer 10, and only the gate extension 8a is placed on the GaAlAs layer 10 in self-alignment (C).

FIG. 2 is a three-dimensional diagram of a field effect transistor manufactured in this manner.

The operation of the field effect transistor of this embodiment configured as described above will be explained below.

The potential of the surface of the n-type GaAs layer 3 in contact with the gate electrode 8 is clipped low due to the potential applied to the gate electrode 8 and the Schottky barrier. This plays an important role in the on/off operation of the current of the field effect transistor. The potential of the surface of the non-doped GaA IAs layer 10 in contact with the gate extension 8a is similarly low (clipped).
The internal potential of the non-doped GaAlAs layer 10 increases as it approaches the boundary with the non-doped GaAs layer 9 from the surface in contact with the gate extension 8a. Then, right below the gate extent 8a,
Furthermore, by appropriately setting the thickness of the non-doped GaAlAs layer 10, the surface potential of the non-doped GaAs layer 9 that is in contact with the non-doped GaAlAs layer 10 can have a value higher than that of the surface of the n-type GaAs layer 3 and lower than that of the bulk. can. Therefore, the decrease in the potential inside the non-doped GaAs layer 9 is alleviated, and the decrease in the potential at the end of the n-type GaAs layer 3 is also alleviated.

As described above, according to this embodiment, by providing the non-doped GaAlAs layer 10 between the gate extension 8a and the non-doped GaAs layer 9, the influence of the electric field exerted by the gate extension on the channel region is alleviated.
A decrease in current density at the edge of the n-type GaAs layer 3 can be prevented.

Further, since the potential of the non-doped GaAs layer 9 immediately below the gate extension 8a is controlled to be smaller than that of the bulk, side leakage of current to the non-doped GaAs layer 9 side can be prevented.

Furthermore, since the gate extension 8a is left, there is no limit to how the gate can be pulled out.

FIG. 3 is a characteristic curve diagram showing the channel width dependence of the threshold voltage of the field effect transistor manufactured in this example. Here, the dotted line shows the characteristic curve of the conventional field effect transistor, and the solid line shows the characteristic curve of the field effect transistor in this embodiment. From this, it can be seen that the narrow channel effect of the field effect transistor of this example is alleviated compared to the conventional field effect transistor.

In this example, GaAs is used for the first compound semiconductor layer, but any compound semiconductor may be used as long as it is a compound semiconductor (the same applies to the second compound semiconductor layer, and it may be the same as the first compound semiconductor layer). .

Also, for the third film, a film other than photoresist, such as a PMMA film, may be used.

Effects of the Invention As is clear from the above explanation, the present invention provides a gate extension by sandwiching a second compound semiconductor layer between a first compound semiconductor layer forming an n-type semiconductor layer and a gate extension. The tension can moderate the influence of the electric field on the n-type semiconductor layer, and can maintain an appropriate potential directly under the gate extension. Therefore, it is possible to provide a field effect transistor in which the narrow channel effect is alleviated, the threshold voltage does not change even when the channel width becomes narrow, and the variation is small, and the practical effects thereof are great.

[Brief explanation of the drawing]

Fig. 1 is a process cross-sectional view showing one embodiment of the method for manufacturing a field effect transistor according to the present invention, Fig. 2 is a characteristic curve diagram comparing the narrow channel effect of a field effect transistor and a conventional field effect transistor, and Fig. 4 5 is a process cross-sectional view showing an example of a conventional method for manufacturing a field effect transistor, and FIG. 5 is a characteristic curve diagram showing the narrow channel effect of a conventional junction field effect transistor based on the manufacturing method shown in FIG. be. 1...Semi-insulating GaAs substrate, 2...Photoresist, 3=n-type GaAs layer, 4@m*n+-type GaAs
layer, 5... photoresist, 6... source electrode, 7.
...Drain electrode, 8...Gate electrode, 8a...Gate extension, 9...Non-doped GaAs
Layer, 10...Non-doped GaAlAs layer Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 3 Channel width wch (μm) Figure 4

Claims (1)

[Claims] forming a second semi-insulating compound semiconductor layer on the first compound semiconductor layer; forming a third film on the second compound semiconductor layer; and forming only the third film on the second compound semiconductor layer. a step of forming a predetermined opening, a step of selectively etching the second compound semiconductor layer using the third film as a mask, and a step of masking the third film and the second compound semiconductor layer. a step of selectively forming an n-type semiconductor layer by implanting ions into the first compound semiconductor layer; and a step of forming a gate electrode into the n-type semiconductor layer.
1. A method for manufacturing a field effect transistor, comprising the step of forming a compound semiconductor layer so that the second compound semiconductor layer and both ends thereof extend to the second compound semiconductor layer.