JPS63269398A - Information processing system having loop memory - Google Patents

Abstract

PURPOSE:To send information to a loop memory in spite of the state of an information processor and to easily shift an operation to the next tone, by using the loop memory as a bus by using the loop memory circulated at high speed. CONSTITUTION:When a state where the identification information of a block is received or is possible to be written by referring the information setting the block circulating as a unit is shown, opposite destination information and transfer information sent from one of the information processors such as an arithmetic unit 3, a memory 4, and the I/Os 51 and 52, etc., are written on the loop memory 2, and also, the state is set where no information is received. And also, the opposite destination information read from the loop memory 2 shows either one of the information processors such as the arithmetic unit 3, the memory 4, and the I/Os 51 and 52, etc., and the state is set as the one where no identification information is received, and also, by sending it to either one of the transfer information read in the state where either one information is possible to be received, the identification information is set at the state where the information is received or possible to be written. In such a way, it is possible to input/output the information at high speed and frequently.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an information processing system having a loop memory, and more specifically, the present invention relates to an information processing system having a loop memory. The present invention relates to an information processing system that uses this loop memory and circulates information so that various information processing devices, including an arithmetic processing unit and memory, can be operated independently.

[Prior Art] Conventionally, as methods for circulating and storing digital information, there have been known methods such as a shift register method, an electronic/mechanical delay line method using a mercury tank, and a magnetostrictive delay line method.

[Problems to be solved by the invention] In the conventional memory circuit using circular memory, the delay time is limited, the memory sensitivity is not large, and the memory circuit cannot be used as a temporal memory circuit. It's just that it's being done. These are so-called buffer memory uses, and have a relatively large capacity! It is not used as a storage device or storage medium that requires 11 storage.

Moreover, when attempting to enlarge the storage field j4 using the conventional circular data storage method, there is a limit because a large delay time must be taken, and the access time increases, making it unusable for practical use.

On the other hand, storage devices such as conductor storage devices and magnetic disk storage devices can have a large storage area, but on the other hand, they require mechanical parts and connections using plugs. Moreover, it is susceptible to electrical noise, etc., has a relatively long access time, and requires various additional configurations to maintain data reliability. As a result, the configuration has become complicated.

In order to solve such problems, the present applicant proposed a loop memory using an optical loop, and filed an application as a "storage device" in March 1988. This storage device has the advantage of having a fast loop circulation speed and being able to store a relatively large capacity HA, and has only a few mechanical elements and short access time.

By the way, conventional information processing systems have a structure in which a processor, which is an arithmetic processing unit, memory, I/O, or their interfaces are connected to each other via a common bus, and information is transferred via a common bus. For this reason, bus controllers and other devices are used to differentiate information transfer, but each device connected to a common bus operates in accordance with the reference clock and in accordance with the bus usage timing. This has the drawback that efficient information exchange cannot be carried out due to waiting times and the like.

The present invention was made in view of the shortcomings of the prior art, and takes advantage of the characteristics of the loop memory described above to connect arithmetic processing devices and other information processing devices such as memory IJ and I/O. One objective is to provide an information processing system that can exchange information between devices via a loop memory and transfer information without synchronizing the operations of each device.

[Means for Solving the Problems] An information processing system using a loop memory according to the present invention that achieves the above object circulates and stores information between an arithmetic processing unit, a memory, and an information processing device dedicated to I10. The circulating information storage area of the loop memory is divided into blocks, and each divided block contains destination information, transfer information, and identification information for identifying whether or not this transfer information has been received. is entered, and the circulating block is placed at the 91st position, and the identification information of the block is referenced to indicate the state in which information has been received or the state in which information can be written. The destination information and transfer information sent from any one of the information processing devices are stored in the loop memory and the identification information is not received, and the destination information read from the loop memory is stored in the arithmetic processing device. , a transfer read out when one of the information processing devices such as memory and I/O is in a state where identification information is not received, and one of the information processing devices is in a state where information can be received. The information is sent to one of them, and the identification information is set in a state in which the information is received or in a state in which it can be written.

[Action] If you use a loop memory that circulates at high speed and use the loop memory as a bus, the arithmetic processing unit can store information in the loop memory regardless of the status of each information processing device such as memory or I/O. Since the data can be sent to IJ, 1-1, it is possible to easily shift to 1 for the next process. In addition, each device on the receiving side only needs to receive the information at the next timing when the data is circulated when it is not possible to receive the information, and can receive the information independently of the status of the sending side.

By the way, an optical loop memory that forms a transmission closed loop with an optical fiber and a circulation circuit can shorten the delay time and store a large amount of information while confining it in the circulation loop. Moreover, since the speed of light is approximately 3XIO8m per second, the amount of information trapped therein is correspondingly enormous.

Furthermore, since information is transmitted and circulated using light, access time is extremely short. Therefore, by using such an optical loop memory, it is possible to input and output information at high speed and frequently. Therefore, it is particularly suitable for the information processing system as described above.

[Embodiment 1] An embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a computer system to which an information processing system having a loop memory of the present invention is applied;
FIG. 2 is an explanatory diagram of the information storage area divided into blocks, FIG. 3 is an explanatory diagram of the transfer data format of each block, FIG. 4 is a block diagram of the optical fiber circulation storage device, and FIG. The figure is a block diagram of another optical fiber circular storage device.

In addition, in each of these figures, equivalent parts are indicated by the same reference numerals.

In FIG. 1, numeral 1 denotes a computer system including a loop memory 2, and the loop memory 2 is configured as a common path. 3 is its arithmetic processing unit; 4
is a memory, 5 is an I10 controller, and 10 is a read/:! having a counter that circulates in synchronization with the circulation of information in the loop memory 2. This is an F-inclusive control circuit.

Here, the loop memory 2 includes a write circuit 7 provided as an integrated circuit with the optical transmitting circuit 7a, and an optical transmission line 2c1 for receiving the output data converted into light from the optical transmitting circuit 7a. The optical receiving circuit 9a receives the information circulating from the optical receiving circuit 2C and converts it into an electrical signal.The optical receiving circuit 9a receives the signal from the optical receiving circuit 9a and is configured as an integral circuit therewith.

Further, the arithmetic processing unit 3, memory 4, and I10 controller 5 are each connected to a write circuit 7 of the loop memory 2 via a connection switching circuit 6, and further connected to a read circuit 9 of the loop memory 2 via a connection switching circuit 8. It is connected to the. The connection switching circuit 6 is also connected to the readout circuit 9 and receives a signal from the connection switching circuit 9.

Then, the data loaded into loop memory 2 is -F
It is written from the write circuit 7, passes through the optical transmission path 2b, is read out by the read circuit 9, and reaches the write circuit 7 via the circulation circuit 2a, where it circulates.

The arithmetic processing unit 3, memory 4, and I10 controller 5 are
When the connection switching circuit 8 is not in a state to receive data read from the reading circuit 9, a busy signal is sent to the connection switching circuit 8, and when the connection switching circuit 9 receives this busy signal, the read information is transferred to the device. It doesn't work to connect to.

Note that 51.52 indicates the I1 of the printer, display, external storage device, etc. connected to the I10 controller 5.
0 device.

Here, the arithmetic processing device 3 includes a microprocessor 3a, a buffer memory 3b, and the like. Further, the connection switching circuit 6 includes a multiplexer, a decoder, a counter, etc.
Connection switching circuit 8 includes a multiplexer and a decoder. These connection switching circuits 6 and 8 selectively connect the arithmetic processing unit 3 to any one of the memory 4 and the I10 controller 5 according to information read from the loop memory 2, respectively.

The connection switching circuit 6 sequentially switches connections in response to the output from the counter 10a of the read/write control circuit 10 synchronized with the circulation of data in the loop memory 1. On the other hand, the connection switching circuit 8 Memory 2: The destination device address of the data stored in the IF is decoded by the decoder, and each corresponding device (processing unit,
Memo U, I10 controller, etc.) and transfers the read data to the selectively connected device.

The read/write control circuit 10 includes a counter 100a,
A clock pulse generation circuit 10b generates a lock signal corresponding to each bit of information, that is, one period corresponding to the maximum set information amount stored therein for one period of data circulation, and a head position detection circuit 10c. The counter 10a has its value reset by the signal from the head position detection circuit 10c, and the value of the counter 10a is reset by the signal from the clock pulse generation circuit 10c.
The count value is updated by the clock pulse b.

Therefore, the value of the counter 10a corresponds to each data bit, but the lower three bits are discarded and
The count value is updated for each byte.

Furthermore, as described later, this 1-byte counter l
The connection switching circuit 6 receives the output of Oa, counts it by the number of bytes of one block using an internal counter, and switches the connection in units of blocks within the connection switching circuit 6.

As shown in FIG. 2, the loop memory 2 has circulating storage areas 100a and 100b.

It is divided into blocks 100c, 100d, . . . , and information is read/loaded in three blocks, and the information is circulated in blocks.

Here, the block 100a is allocated as the write area of the arithmetic processing device 3, the block 100b is the write area of the memory 4, the block 100C is the write area of the I10 controller 5, and the block 100C is the write area of the information processing device other than these. etc. ! These blocks 100a to 100d are repeatedly arranged in a continuous loop.

Also, such a block may be the same block, e.g.
00a in a row, then block 100
A number of the same blocks may be placed consecutively, such as b, and then the next block may be placed.

Note that the method of dividing the information storage area of the loop memory 2 described above is only an example. Also, assigning blocks to each device in this way means that the entire loop's storage area is 1
This is to prevent the memory from being occupied by one 'Affi.If the loop has a large storage capacity, it is not necessary to allocate it to each device, but instead to sequentially allocate it to the free blocks that circulate. Just enter it. In such a case, if the circulation speed is not very fast, it will take a long time to access the information and there will be no benefit. Quotas work.

By the way, the method of allocation to each block depends on the storage address of the loop memory 21- being set in advance in each device of the arithmetic processing unit 3, memory 4, and I10 controller 5.

Here, for each block,! ) The format of the input data is as shown in Figure 3. In FIG. 3, 11 is a destination device address field for receiving transfer data, 12 is a read/write designation address field, and 13 is a control code field.
a is an identification information area, and the rear part is a control information area that stores various control information for instructing read/'IF inclusion, etc. 14 is a transfer data storage column. Note that information is written to/read from the loop memory 2 in units of blocks. Further, if the identification information is, for example, 1-bit flag information, "1" indicates the state to be received, and &1 Q N indicates the received state.

Next, to explain the overall operation, first, when transferring data from the arithmetic processing unit 3 to the memory 4, the write address corresponding to the block assigned to itself on the memory loop and the destination device are stored in the buffer memory 3b. The address, write/read designation address information, control information indicating read or write, and transfer data are set. For example, when data is transferred and written to memory 4, the destination address is the device address assigned to memory 4, control information indicating writing is set as control information, and the specified write address and 71 should be entered. data is set in each column.

The connection switching circuit 6 receives the output from the counter 10a of the read/write control circuit 10 in synchronization with the circulation of data in the loop memory 1, counts it, and selectively switches the connection to each device in block correspondence. When connected to the arithmetic processing unit 3, the data in the buffer memory 3b is transferred to the write circuit 7. Then, the writing is completed and the identification information is set to the state where it should be received (in the previous example, the flag “
1''), a reset signal is sent to the buffer memory 3b via the circuit in the connected state, the contents of the buffer memory 3b are reset, and the connection is switched to the next device 9, for example, the memory 4. Note that the reset signal is sent from the counter of the connection switching circuit 6 which receives the output signal from the counter 10a at the timing when the last data is written to the block in response to the 1) iI write output signal.

Furthermore, the data in block 1ooa is read out by the readout circuit 9 before entering +'f, and the data stored in the identification information area of the column 13 is read out and referred to. and the identification information is still to be received,
When the other party indicates that the data has not been received (state B in which the flag remains 1" in the previous example), writing to the block 100a is not performed. In this case, the contents of the buffer memory 3b are Not reset, processing unit 3
1 of the following data from! F-inclusion is not performed. and,
It will wait until the next block 100a.

The data thus stored in the loop memory 2 via the IF is transmitted via the optical transmission line 2b and reaches the readout circuit 9. The signal is then sent to the connection switching circuit 8 via the readout circuit 9. The connection switching circuit 8 reads out the data stored in the identification information area of the column 13, and determines the state of the identification information to be received! ji! (In the previous example, when the flag is 1"), the data in the destination device address column 11 is decoded by the decoder and output to the destination device address when the destination destination is not busy. By switching the connection as shown in the figure, the address information in the specified address column 12 indicating the specified write address and the transfer data column 1 are displayed.
The read transfer data in 4 and the control information in the control column 13b are both transferred to the connected device. In the current example, the destination device address indicates memory 4, so it is connected to memory 4, the read information is sent to memory 4, and the data transferred to the address position in designated address column 12 is -F included. When the connection switching circuit 8 receives the signal that the writing is completed from the memory 4, the connection switching circuit 8 inputs the identification information (in the previous example, the flag 0'') indicating that the data has been received in the identification information area of the column 13. set) to indicate that it has been received.

However, at this time, when the memory 4 is in operation and cannot receive information, the connection circuit 8 does not perform the connection operation or the data transfer operation described in 1lii. Therefore, this data circulates in the loop memory 2 as it is. Therefore, the same data that circulates after another round is stored in memory 4.
will be accepted.

If the memory 4 is still not in a state where it can receive it, it will wait until it is circulated several times before receiving it.

In this way, information can be transferred and received independently of the operation of its own RA device.

The following is a case where data is written from the arithmetic processing device 3 side to the memory 4 side, but when the arithmetic processing device 3 reads data from the memory 4, the information in the control information column 13 is used as read information, State where identification information should be received (flag 1
”) and send it to the memory 4. In the case of reading, write the destination device address in the transfer data field 14. Therefore, block data format-1 - In particular, it is recommended to provide a destination address field. not present.

When the memory 4 receives the read control information and the specified address information from the connection switching circuit 8, the memory 4 writes the information read from the specified address to the write address assigned to itself in the loop memory 2''. The destination device address (previously transferred as the destination address together with the read control information), a control signal indicating at inclusion, etc. are sent to the connection switching circuit 6 according to the format shown in FIG. Then, a busy signal is output to the connection switching circuit 8 side. The connection switching circuit 6 writes the data from the memory 4 to the loop memory 2 at the timing when the block 100a corresponding to the memory 4 is read out, as in the case of the arithmetic processing unit 4, and when the writing is completed. At this point in time, it is set to a state where identification information should be received (flag 1''), and a reset signal is sent to the memory 4 through the connected circuit in the same manner as described above.

The following is the relationship of data transfer between the arithmetic processing unit 3 and the memory 4, and the same process is performed for the relationship between the I10 controller 5 and the memory 4 or the arithmetic processing unit 3.

Therefore, the details are omitted.

Next, a specific example will be described in which the loop memory 2 is an optical fiber circulating storage device. 200 in Figure 4 is
This is an optical fiber circular storage device, and is one of the specific examples of the loop memory 2. 2c is an optical fiber forming the optical transmission path. Further, the optical transmitting circuit 7a and the writing circuit 7 are represented here as an optical transmitting section 19, the optical receiving circuit 9a and the reading circuit 9 are represented as an optical receiving section 20, and the reading/writing control circuit 10 is represented as an optical transmitting section 19. Control circuit 21
It becomes.

By the way, the number one data format in this optical fiber circulation storage device 200 is as shown in FIG.
Now, suppose that the address of the destination device that receives the transfer data in column 11 is 1 byte, the read/write specified address in column 12 is 2 bytes, and the control code in column 13 is the front 13
7 bits for a, 1 bit for identification information, 8 bits
Assuming that a byte is allocated and the transferred data is 1 byte, it is convenient to receive information and control if it can be read out in parallel with a width of 40 bits (5×8).

Therefore, one block will be explained below as having a 40-bit configuration.

The optical fiber 2c forming the optical transmission line is optically coupled at its .

The length of the optical fiber 20 can be any length in the range of several meters to several tons of kilometers depending on the purpose, for example,
An optical fiber 2c is wound around a bobbin, and a light emitting element 19a and a light receiving element 20a are integrally coupled to both ends of the optical fiber 2c.

In addition to the light-receiving element 21a, the optical transmitter 19 includes a parallel-to-serial converter circuit 15 into which lt-inclusive data is set from the outside, and a circular storage path for the data converted into serial data by the parallel-to-serial converter circuit 15. A data sending OR gate 16 which receives the signal from the data sending OR gate 16 and amplifies it to drive the light emitting element 19a, and an AND which receives the output signal from the optical receiver 20. It is equipped with a gate 18.

Here, the output of the AN+) gate 18 is the data sending OR
The information received by the gate 16 is sent to the amplifier i17, converted into light via the light emitting element 19a, and sent back to the optical fiber 2C.

On the other hand, the optical receiver 20 includes an amplifier 22 that amplifies the information received by the light receiving element 20a, a waveform shaping circuit 23 that shapes the waveform to restore the attenuated and corrupted digital waveform, and an output signal from the waveform shaping circuit 23. The serial-to-parallel conversion circuit 24 receives a signal, and the latch circuit 25 latches the output of the serial-to-parallel conversion circuit 24. The output of the waveform shaping circuit 23 is transmitted to the optical transmitter 1
9's A N I) gate 18. This forms a loop-shaped circulation path including the optical fiber 2c. Note that the waveform shaping circuit 23 is constructed of a 1) type flip-flop that generates a waveform in response to a clock pulse.

Read/1! ) The integrated control circuit 21 includes a counter 31 and
It consists of a comparison circuit 32, a one-shot circuit 33, a head position decoder 34, a clock generation circuit 35, and the like.

Here, if the counter 31 is an n-ary counter, the time required to count the maximum count value n in response to the clock pulse from the clock pulse generation circuit 35 transmits information from one end of the optical fiber 2C to the other. It is greater than or approximately corresponds to the period (time). The count value of this counter 31 indicates the position of the information.

That is, if information indicating the beginning of data is written when writing information and counting is started using this as a reference, the counter 31 is thereafter started in accordance with the timing when the information indicating the beginning is read out. By that,
The position of the written information and the counter 31 can be synchronized. As a result, the position of the data can be known from the value of the counter 31. Therefore, when reading or writing at a specific position, it is sufficient to write in accordance with the count value of the counter 31 and read with reference to the count value. In other words, 111 of the counter 31 indicates the specified address for reading information and including -F.

Note that the signals obtained by decoding the outputs of the first to fourth stages of the counter 31 are used as the trigger signal T of the parallel-serial conversion circuit 15, and this trigger signal T is generated every eight clock pulses. Note that this trigger signal T
is a parallel-serial conversion circuit 15 and a latch circuit 25
, and is sent to the connection switching circuit 6.

The connection switching circuit 6 receives the trigger signal T and sends a connection switching signal to the multiplexer 62 when the counter circuit 61 receives the signal T for six [1] signals.

Multiplexer 62 switches the connection to the next device in response to this signal. Decoder 63 receives identification information from latch circuit 25, decodes it, and enables multiplexer 62 when the identification information references the identification information and indicates a received state. Note that in the present case, since a 1-bit flag is used as identification information, the decoder 62 actually requires only one buffer circuit, and does not require a function as a decoder.

The comparison circuit 32 compares the current count value of the counter 31 with the address value provided from the connection switching circuit 6, and when they match, enables a write side control signal to the parallel-to-serial conversion circuit 15, etc. of the optical transmitter 19. The signal is sent out as a signal, and a read side control signal is sent out to the latch circuit 25 of the optical receiver 20. Therefore, read information is latched in response to a matching output. Note that the comparison process of the comparison circuit 32 is performed by discarding the lower three bits of the counter. As a result, this coincidence detection process is performed every 8 bits of the clock pulse of the clock generation circuit 35. Moreover, the match detection credibility is
It exists for a period of 8 bits of clock pulse.

The one-shot circuit 33 is a circuit that generates No. 15 indicating the top position, and generates a signal of "1" (or HIGH level (hereinafter referred to as "H")) for a certain period of time. The fixed period is, for example, a period of 8 bytes as a clock pulse. One-shot circuit 33 performs system reset i.
When the signal is received at the terminal 36, a signal indicating the leading position is sent from the one-shot circuit 33 to the data sending OR gate 16 and the counter 31. As a result, the head position information of "H" is sent to the loop-shaped memory path for a certain period of time, and
The counter 31 is reset at the falling timing of -γ of this head value information, and starts counting from the next clock pulse. New information is then written into the loop-shaped memory path in response to this clock pulse.

The clock generation circuit 35 preferably has a frequency that approximately corresponds to the frequency of one bit of information when a set maximum amount of information is stored in the optical transmission line of the optical fiber 2c, and here, for example, the frequency is 200 MHz. Generates a clock pulse with a frequency of approximately

Next, the overall operation of this optical fiber circulating storage device 1 will be explained.

First, to explain the information writing operation, one block of information, 40 bits of data, supplied from the outside is input in five 8-bit parallel steps.
At one time, 8-bit data is converted into serial data by the parallel-serial conversion circuit 15, and the data is sent out.
The light is sent to the amplifier 17 via the R gate 16 and power amplified, thereby driving the light emitting element 19a, and the generated light is sent out to the optical transmission line of the optical fiber 2c.

This will result in old inclusion. Here, the timing at which the parallel-serial conversion circuit 15 is driven is determined by receiving the coincidence detection signal of the comparison circuit 32 as an enable signal and in response to the trigger signal T of the counter 31. Send data. In this way, 40 bits, or 5 bytes of data are transferred to the third
The line written according to the format shown in the figure is a write-in operation.

It should be noted that the match detection process of the comparator circuit 32 is performed every 8 bits of the clock pulse because the lower 3 pins are discarded. Therefore, the match detection process is performed every 8 bits, and occurs in correspondence with the count value of the counter 31, in other words, the address. Further, its length is equivalent to 8 pintos in terms of clock pulses. Therefore, i! F
The data is written serially in synchronization with the value of the counter 31, every 8 bits of the clock pulse.

Now, the optical information sent out from the light emitting element 19a propagates through the optical fiber 2c and reaches the light receiving element 20a, where it is received. The light-receiving electric signal of the light-receiving element 20a is
The signal is amplified by the amplifier 22 and waveform-shaped by the waveform shaping circuit 23, and the output signal is sent to the AND gate 18 of the optical transmitter 19. As a result, the information received is
After passing through the D gate 18 and the data sending OR gate 16, the power is amplified again by the amplifier 17 and reaches the light emitting element r19a. Here, the light emitting element 19a is driven, and the write information is circulated. Furthermore, ANr) Gate 1
The other two inputs of 8 are maintained at "H" in the steady state.

Here, at the time of writing the first information, AND'
A system reset signal is input to the input terminal 36 of the port 7'-18. This is the so-called clear faith't (CL
When the 7-stem reset signal goes to LOW level (reset), the circulation of the written information is cut off, and the subsequent -) write data disappears. At this time, the one-shot circuit 33 is simultaneously driven and a head position signal of "H" is generated for a certain period of time.

Further, when rewriting data at a specific position, an address corresponding to the rewriting is given to the comparison circuit 32. At this time, since the coincidence output of the comparison circuit 32 is inputted to the AND gate 18 via the inverter 37, this input becomes "L" at the time when a coincidence is detected. In this way, one of the inputs of the AND'y'- gate 18 before the L of sending out the 8-bit input data when adding 2 is set to "L I+".
By doing this, it is possible to erase the data for 8 points that has already been stored. At this time, new 8-bit data is written from the data sending OR gate 16.

Therefore, when inputting data to i'ff, it is only necessary to input the address signal Sj from the outside to the comparator circuit 32, and when the count value of the counter 31 matches, A N
I) When gate 18 is closed and there is circulating data, the data at that address is cleared.

Then, in accordance with this timing, write data is input as serial data from the parallel-serial conversion circuit 15 via the data sending OR gate 16.

Except for the above two cases, the two inputs of the AND gate 18 are "H" (or "1"), so the written information passes through as is.

Therefore, all information can be erased by setting the system reset signal to "0" corresponding to one cycle of the circulation path. Note that when performing such erasing, the output of the one-shot circuit 33 is not output (this is not shown).

The following is a write operation of information. Next, a read operation will be explained. 8 serial signals
It receives each bit and sequentially converts it into 8-bit parallel data.

Then, in response to the trigger signal T from the counter 31,
A latch circuit 25 latches the 8-bit parallel data from the serial-parallel conversion circuit 24. The latch circuit 25 is equipped with five 8-bit parallel registers, and holds 8-bit data cyclically and sequentially in the five registers, resulting in a total of 8x5 40-bit 8-bit pattern data. Retained. Therefore, the data corresponding to the format block shown in FIG. 3 is always held.

Therefore, if the connection switching circuit 8 receives the data from the latch circuit 25, uses its decoder to decode the destination device address and identification information, and switches the connection using its multiplexer, data can be transferred depending on the destination.

The embodiment shown in FIG. 5 transmits information in a multiplexed manner using spectral spectroscopy m41°42.
．． 45 are optical transmitting units 19. A circulation path consisting of an optical receiving station 20 and a read/write processing unit 30 is shown. In this way, light of multiple wavelengths can be connected to the same optical fiber 2C.
Information can be multiplexed by transmitting it to an optical transmission line and separating it into spectra.

When multiplexed in this way, one of each multiplexed optical transmission line is connected to the arithmetic processing unit 3, the memory 4, and the I10.
If it is assigned to the controller 5 or the like and the readout circuit of the optical receiver is selected by the connection switching circuit, it can be distributed to the other party via the readout circuit. Note that the light emitting element 19a.

The light receiving element 20a is a part of the optical transmitter and the optical receiver, respectively, but for convenience of explanation, they are shown as protruding parts.

In the case of multiplexing in this manner, it is of course possible to provide a number of optical loops without multiplexing and to share the readout circuit side.

As explained above, in the embodiment, the loop memory is constructed using an optical fiber, but it is of course possible to use a loop using magnetism or an ultrasonic transmission line. be.

In the specific example shown in Figure 4, a 1-bit loop optical fiber transmission path is used, but it is also possible to change the wavelength and transmit multiple bits in parallel to the same optical fiber, or to connect optical fiber loops in parallel. It is also possible to provide a plurality of loops in parallel and transmit bits in parallel.

In the embodiment, writing and information transfer are managed using identification information, but the identification information indicating the state in which the block should be received originally indicates that the transfer information of the block has not yet been received. Conversely, a state indicating that a block has been received originally means that new information can be written to the block.

Further, although the identification information is decoded and written by the connection switching circuit, this may be done by each device such as the arithmetic processing unit or memory. The same goes for decoding at the other end.

Also, the read/write configuration of the optical loop in Fig. 4 is -
This is an example and is not limited to this.

Furthermore, the data structure in the block in the embodiment is just an example, and various types can be used, and reading does not require reading out the entire block in parallel (it is sufficient to read out only the data necessary for switching control). .

In the embodiment, the arithmetic processing unit is connected to the loop memory via its buffer memory, but this may also be directly connected like the memory. Furthermore, the memory may also be connected to the loop memory via a buffer memory.

In particular, if the circulation cycle of the loop memory is an integer multiple of the machine cycle of the microprocessor of the processing unit or a threshold value slightly more than that, the blocks of the processing unit will cycle in the time of the machine cycle or an integral multiple thereof. hand(
Therefore, data can be loaded directly from the arithmetic processing unit into the loop memory, and can be processed efficiently.

[Effects of the Invention] As can be understood from the following explanation, in this invention, if a loop memory that circulates at high speed is used and the loop memory is used as a bus, the arithmetic processing device can
Information can be sent to the loop memory regardless of the status of each information processing device such as memory or I/O, making it easy for next processing. 11. You can move to In addition, each device on the receiving side only needs to receive the information at the next timing when the data is circulated when it is not possible to receive the information, and can receive the information independently of the status of the sending side.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer system to which an information processing system having a loop memory of the present invention is applied;
FIG. 2 is an explanatory diagram of the information storage area divided into blocks, FIG. 3 is an explanatory diagram of the transfer data format of each block, FIG. 4 is a block diagram of the optical fiber circulation storage device, and FIG. The figure is a block diagram of another optical fiber circular storage device. ■...Computer system, 2...Loop memory, 3...Arithmetic processing unit, 6, 8...Connection switching circuit,
7... Interpretation circuit, 9... Readout circuit, 10...
Counter circuit, 100a, 100b, 1oOc, 100d...block, 11...destination device address field, 12...
Read/write designated address column, 13... Control code column, 13a... Identification information area, 13b... Control information area, 14... Transfer data storage column, 15... Parallel-serial 2m circuit, 16...Data sending OR gate, 17...Amplifier, 18...AND gate, 19...
- Optical transmitter, 20... Optical receiver, 15.24... Parallel-serial conversion fj1 circuit, 21a... Light receiving element, 21b... Light emitting element, 22... Waveform shaping circuit,
25... Latch circuit, 30... Read/11) input processing section, 31... Counter, 32... Comparison circuit, 3
3... One-shot circuit, 34... Leading position decoder, 35... Clock generation circuit, 200... Optical fiber circulation storage device. Patent Applicant 1” El Chuo Electronic Materials Co., Ltd.

Claims (5)

[Claims] (1) It is equipped with an arithmetic processing unit, a memory, an information processing device such as I/O, and a loop memory that circulates and stores information, and the circulating information storage area of the loop memory is divided into blocks, and these divisions are divided into blocks. In each block, destination information, transfer information, and identification information for identifying whether or not this transfer information has been received are written. destination information and transfer information sent from any one of the information processing devices such as the arithmetic processing device, the memory, and the I/O when the information indicates a received state or a writeable state; The destination information is written to the loop memory and the identification information is not received, and the partner information read from the loop memory is written to the processing device,
It indicates any one of the information processing devices such as the memory and the I/O, and the identification information is not in the received state, and the one is in the state where the information can be received. An information processing system having a loop memory, characterized in that the information processing system sends the transfer information read out to any one of the memory devices to put the identification information in a state in which the information is received or in a state in which the information can be written. (2) The circulating information storage area of the loop memory is divided into blocks and allocated to an arithmetic processing unit, memory, and information processing device such as I/O, and among the circulating blocks, the arithmetic processing unit, the memory, When the block allocated to each of the information processing devices such as the I/O etc. refers to the identification information in accordance with the timing when it is circulated, and indicates a state in which information has been received or a state in which information can be written,
2. An information processing system having a loop memory according to claim 1, wherein destination information and transfer information are written in said loop memory. (3) The arithmetic processing device has a processor, and the circulation cycle of the loop memory is equal to or slightly larger than the machine cycle of the processor or an integral multiple thereof. An information processing system comprising the loop memory according to item 2. (4) The loop memory is equipped with a read and write circuit, and the write circuit, an arithmetic processing unit, a memory, and an I/O
An information processing system having a loop memory according to claim 2, characterized in that the information processing device is selectively connected in accordance with the timing when the blocks assigned to the device are circulated. . (5) The loop memory is equipped with a reading and writing circuit, and the reading circuit, an arithmetic processing unit, a memory, and an I/O
as set forth in claim 2, wherein the information processing device is selectively switched and connected, and the switching is performed by decoding destination information read out from the readout circuit. An information processing system with loop memory.