JP3139291B2 - Display control means and display panel driving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting parallel data sent from a processor into serial data, and a method of selecting a plurality of display elements based on the serial data and blinking the selected display elements to thereby change the state of a device to be displayed. The present invention relates to a display panel driving device including a plurality of display panel control circuits for displaying, and in particular, it is possible to sequentially supply the serial data to the next display panel control circuit, thereby facilitating the addition of display panels. The present invention relates to a display panel driving device that can share the processor with a processor that controls the display target device.

For example, in a large-capacity storage device, storage shelves for storing a large number of recording media such as magnetic tape cartridges are provided, and the recording media are respectively stored in a plurality of cells for storing the recording media provided in the storage shelves. The storage medium is stored, and an accessor equipped with a mechanical hand takes out a necessary recording medium from the cell of the storage shelf, transports the recording medium to a recording / reproducing unit, sets it, and writes or reads data.

When the writing or reading of the data is completed, the recording medium is taken out of the recording / reproducing unit again, transported to and stored in the cell of the storage shelf, and the recording medium which has become unnecessary in accordance with an instruction from the host device. The medium is conveyed to the loading / unloading mechanism and made to be taken out by the operator, and the recording medium put into the loading / unloading mechanism by the operator is transported to the recording / reproducing unit and set, or transported to the cell and stored.

[0004] Whether or not a recording medium is stored in the cell is displayed on a display panel to allow an operator to recognize. Therefore, when the above-mentioned cells are added, the number of display panels is also increased. However, it is desired that this cell can be easily added and that a dedicated processor is not required for display.

[0005]

2. Description of the Related Art FIG. 6 is a block diagram for explaining an example of the prior art. The processor 1 sends a control signal to the display panel 60, for example, when displaying whether or not a recording medium is stored in a cell in the mass storage device, and LE provided respectively
D is selected to supply a drive current, and the LED corresponding to the cell where the recording medium is present emits light, thereby displaying the presence or absence of the recording medium for each cell.

[0006] Then, a cell is added to the display panel 61.
Is added, a control signal for the display panel 61 is sent to the display panel 61 to display whether or not a recording medium is present in the added cells.

The processor 1 converts parallel data into serial data under the control of firmware and supplies the serial data to the display panels 60 and 61. That is, for example, 8-bit data is sequentially circulated in synchronization with a clock, and the operation of transmitting one bit at a time when a clock is input is repeated eight times, thereby converting parallel data into serial data.

[0008]

As described above, conventionally, when the number of display panels is increased, the number of dedicated control signals also needs to be increased. Therefore, a dedicated control signal line is required for each display panel. The burden on the processor increases.

That is, since the parallel data must be converted into serial data and transmitted, the time required for the conversion increases as the number of control signals increases, and the time spent for display control is increased. However, there is a problem that the processor is required, and it is not easy to increase the number of display panels.

In view of the above problems, the present invention reduces the load on the processor, reduces the time spent for display control, and enables the processor for controlling the display target device to also perform the display control. It is an object of the present invention to eliminate the need for a display-only processor and to facilitate the addition of a display panel.

[0011]

FIG. 1 is a block diagram for explaining the principle of the present invention. The display panel driving device that displays the state of the display target device captures parallel data composed of a predetermined number of bits based on a write signal transmitted by the processor 1 and sequentially outputs one bit at a time in accordance with a clock. Parallel / serial conversion means 2 for converting the serial data having the predetermined number of bits into serial data, and serial data of the predetermined number of bits input from the input side are sequentially shifted from the first bit in accordance with the clock and stored. When serial data exceeding the predetermined number of bits is input, storage means 5 for sequentially transmitting one bit at a time from the output side in the order of input, and the processor 1 transmits the serial data of the predetermined number of bits stored in the storage means 5. The number of display elements corresponding to the predetermined number of bits is latched based on Display control means 3 has one or more of and a drive unit 4 for displaying by corresponding respectively driven to the state of each bit of data.

When a plurality of the display control means 3 are provided, the display control means 3 connected to the parallel / serial conversion means 2 side is connected to the output side of the storage means 5 of the display control means 3 to be connected next. 3, the input side of the storage means 5 is connected, and the latch signal transmission of the processor 1 is necessary for storing the serial data of the predetermined number of bits in the storage means 5 in the number of the display control means 3. It is done at time intervals multiplied by time.

The processor 1 repeats the processing of transmitting the parallel data, transmitting the write signal, and transmitting the latch signal at predetermined time intervals.

[0014]

With the above arrangement, the parallel / serial conversion means 2 takes over the processing of converting parallel data of display data into serial data, which has been conventionally performed by the processor 1, so that the load on the processor 1 is reduced. You.

When the display control means 3 is to be added, the input side of the storage means 5 of the display control means 3 to be added is connected to the output side of the storage means 5 of the existing display control means 3, and the processor 1 performs display. Since the latch signal may be transmitted at a time interval obtained by multiplying the number of control means 3 by the time required for storing the serial data of the predetermined number of bits in the storage means 5,
The display control unit 3 can be easily added.

[0016]

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention. FIG. 3 is a detailed block diagram of a P / S converter.
FIG. 3 is a detailed block diagram of a display control unit.

The processor 1 sends a data latch signal to the display panels 7 and 8, and through the LATCH terminals of the display control units 9 to 12 of the display panels 7 and 8, LTs (latch circuits) 36 to 43 shown in FIG. To set the latch signal.

Therefore, the LTs 36 to 43 are connected to the opposing F
The outputs of F (flip-flops) 28 to 35 are latched. Subsequently, the processor 1 sends 1-byte parallel data to the P / S converter 6 simultaneously with the write signal WR. The 1-byte parallel data is supplied to the register 17 shown in FIG. 3, and the write signal WR is supplied to the C terminal of the register 17 and the counter 14.

The 1-byte parallel data supplied to the register 17 is stored by the write signal WR.
Each bit is sent from the terminal to the OR circuits 19 to 26 constituting the multiplexer 18, respectively.

The counter 14 is reset by the write signal WR and sends the count value “000” to the decoder 16 and the NAND circuit 15. Therefore, the NAND circuit 1
5 sends a logical "1" to the AND circuit 13, so that CL
The clock supplied from the K terminal enters the counter 14.

The decoder 16 supplied with the count value "000" sends the logic "0" to the OR circuit 19 of the multiplexer 18, and outputs the logic "1" to the OR circuit 19 of the multiplexer 18.
The signals are sent to the circuits 20 to 26.

Therefore, the logic "1" is input to the AND circuit 27 of the multiplexer 18 from the OR circuits 20 to 26,
From the OR circuit 19, the terminal of the register 17 is logic "
If "1", logic "1" is input. If the terminal of the register 17 is logic "0", logic "0" is input.

Accordingly, the logical value of the terminal of the register 17 is output to the DATA terminal of the multiplexer 18. That is, the logical value of the terminal of the register 17 is "
If the logical value of the terminal of the register 17 is "1", the logical value "0" is sent to the DATA terminal.
A logical "1" is sent to the DATA terminal.

When the clock enters the counter 14 from the CLK terminal via the AND circuit 13, the counter 14 sends a count value “001” to the decoder 16 and the NAND circuit 15. Therefore, the decoder 16 sends the logic "0" to the OR circuit 20 of the multiplexer 18, and sends the logic "1" to the OR circuit 19 and the OR circuits 21 to 26. Also, NAND
The circuit 15 sends a logical “1” to the AND circuit 13.

Therefore, in the same manner as described above, the multiplexer 18 sends the logical value of the terminal of the register 17 to the DATA terminal. That is, if the logical value of the terminal of the register 17 is "0", a logical "0" is sent to the DATA terminal. If the logical value of the terminal of the register 17 is "1", the logical "1" is sent to the DATA terminal. Is sent.

In the same manner as described above, the clock is
The count value of the decoder 16 is incremented each time the data is input, and the logical values of the register 17 are sequentially sent to the DATA terminal of the multiplexer 18.

Therefore, the parallel data written in the register 17 is supplied to the DATA terminal of the multiplexer 18.
It is converted to serial data and sent. When the count value “111” is transmitted from the counter 14, the NAN
Since the logic "0" is supplied from the D circuit 15 to the AND circuit 13, the supply of the clock input from the CLK terminal to the counter 14 is stopped.

Therefore, the above operation is stopped until the processor 1 writes the next 1-byte parallel data into the register 17. One byte of serial data transmitted from the DATA terminal of the multiplexer 18 is sequentially transmitted to the DATA terminal of the display control unit 9 of the display panel 7 bit by bit.

The display controller 9 has a configuration as shown in FIG. 4. The serial data input from the DATA terminal has the first bit input to the FF 28, is stored in the FF 28 by the clock input from the CLK terminal, and is transmitted to the next FF 29 and LT 36. Is done.

The next bit from the multiplexer 18 is F
When the clock is transmitted to F28 and a clock is input, the first bit stored in FF28 is stored in FF29, and the next bit is stored in FF28.

In this way, the FFs 28 to 35 sequentially store the respective bits by sequentially shifting the 8-bit serial data and transferring the serial data to the next FF.
The second bit is FF34 and the third bit is FF33
The fourth bit is FF32 and the fifth bit is FF31
The sixth bit is FF30 and the seventh bit is FF29.
The eighth bit is stored in the FF.

The processor 1 is provided with the display panels 7 and 8, and the display panels 9 and 12 are provided with the display control units 9 to 12, respectively. Therefore, it is recognized that it is necessary to write 8-byte data. Then, a process of writing the next 1-byte parallel data to the register 17 is executed.

Therefore, in the same manner as described above, the second byte of serial data is transmitted to the DATA terminal of the multiplexer 18 and is input to the DATA terminal of the display control unit 9.
Therefore, the 8-bit data stored in the FFs 28 to 35 of the display control unit 9 is sequentially pushed out from the DATA 'terminal and sent out to the DATA terminal of the display control unit 10, and the FF 28 of the display control unit 10 is operated in the same manner as described above. To FF35, and the FF28 to FF35 of the display control unit 9 store 8-bit serial data of the second byte.

When the processor 1 writes the third byte of parallel data into the register 17, the first byte of serial data is transferred to the FFs 28 to F of the display control unit 11 of the display panel 7.
F35, the second byte of serial data is stored in FF28 to FF35 of the display control unit 10 of the display panel 7, and the third byte of serial data is stored in the display panel 7.
Are stored in FF28 to FF35 of the display control unit 9 of FIG.

By repeating the above operation, the processor 1
Writes the 8th byte of parallel data into the register 17, and when the multiplexer 18 finishes sending out the 8th byte of the serial data, the display controller 12 of the display panel 8
Stores the first byte of serial data, the display control unit 11 of the display panel 8 stores the second byte of serial data, and the display control unit 10 of the display panel 8 stores
The third byte of serial data is stored, and the display panel 8
, The fourth byte of serial data is stored in the display control unit 9, the fifth byte of serial data is stored in the display control unit 12 of the display panel 7, and the display control unit 11 of the display panel 7 The 6th byte of serial data is stored, the 7th byte of serial data is stored in the display control unit 10 of the display panel 7, and the 8th byte of serial data is stored in the display control unit 9 of the display panel 7. Is done.

Here, the processor 1 comprises display panels 7 and 8
The latch signals set in the LTs 36 to 43 of the display control units 9 to 12 are reset. Therefore, each LT 36 to 43
As described above, when the latch signal is set, the logical values indicated by the bits latched from the FFs 28 to 35 facing each other are sent to the LED drive circuits 44 to 51, respectively.

At this time, the processor 1 controls the display panels 7 and 8
Since the enable signal is transmitted through the ENB terminal of each of the display control units 9 to 12, the LED drive circuits 44 to 51 are enabled, and if any of the LTs 36 to 43 is transmitting a logic "1", The corresponding LED among the LEDs 52 to 59 is driven to allow the current supplied from the power supply Vc to flow to emit light.

For example, when the FF 28 stores the logic "1", the LED 52 emits light, and when the FFs 29 to 35 store the logic "0", the LEDs 53 to 59 do not emit light.

FIG. 5 is a flowchart for explaining the operation of FIG. The processor 1 starts the display control operation by an interrupt generated every 1 ms, for example. The processor 1 checks whether the data to be written into the register is the first byte in step (1), and if it is the first byte, the latch signal in step (2) Is set.

Then, data is written to the register 17 in step (3). That is, when 1-byte parallel data is written into the register 17, the process is terminated. When the next interrupt occurs, the processor 1 checks whether the first byte is written in step (1). If not, the processor 1 checks whether the eighth byte is written in step (4). For example, in step (5), data is written to the register 17, and the process is terminated.

Therefore, data writing from the second byte to the seventh byte is executed by interruption every 1 ms. When the next interrupt occurs, the processor 1 checks whether the first byte is written in step (1). If not, the processor 1 checks whether the eighth byte is written in step (4). In the case of writing, the data is written to the register 17 in step (6), the latch signal is reset in step (7), and the process is terminated.

Therefore, as described above, by resetting the latch signal, the blinking of the LEDs 52 to 59 is controlled by the logical values latched by the respective LTs 36 to 43. That is, since the display data is updated every 8 ms, as described above, for example, the state of the presence or absence of the recording medium in the cell of the mass storage device is switched and displayed every 8 ms. However, the delay time does not matter in human condition monitoring.

Further, it is easy for the processor 1 to execute the processing shown in FIG. 5 at an interruption every 1 ms, and it is possible to sufficiently execute control of a display target device such as a large-capacity storage device. . Therefore, there is no need to provide a processor dedicated to display control, and the processor that controls the large-capacity storage device can also perform display control.

In this embodiment, an example has been described in which 64 LEDs are selected and displayed using 8-byte data.
If the display switching time interval is lengthened, the number of bytes of data transmitted by the processor 1 can be increased, and more LEDs can be selected, so that the number of displays can be increased.

[0045]

As described above, according to the present invention, by increasing the interrupt processing interval for the processor within the shortest time necessary for recognizing a change in the state of the display target device, a larger number of devices can be obtained. Can be displayed, and a display dedicated processor is not required, and the number of display panels can be easily increased.

Therefore, it is possible to reduce the cost of the display device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a detailed block diagram of a P / S converter.

FIG. 4 is a detailed block diagram of a display control unit.

FIG. 5 is a flowchart illustrating the operation of FIG. 2;

FIG. 6 is a block diagram illustrating an example of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 2 Parallel / serial conversion means 3 Display control means 4 Driving means 5 Storage means 6 P / S conversion part 7, 8, 60, 61 Display panel 9-12 Display control part 13, 27 AND circuit 14 Counter 15 NAND circuit 16 Decoder 17 Register 18 Multiplexer 19-26 OR circuit 28-35 Flip-flop 36-43 Latch circuit 44-51 LED drive circuit 52-59 LED

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/04 G09G 3/20 G09G 3/32

Claims (3)

(57) [Claims] A serial data input from an input terminal is sequentially converted into a predetermined number of bits from a head bit according to a clock.
Storage means for storing the number and, when serial data exceeding the predetermined number of bits is input, sequentially transmitting one bit at a time from the output terminal in the order of input; and a latch signal connected to the processor and transmitted from the processor. When reset, the output of data of a predetermined number of bits stored in the storage means to the display panel drive device side is started, and the data is stored in the storage means while the latch signal is set. A latch circuit that keeps outputting the data that was last output regardless of the value of the output data, and the data output from the latch circuit is displayed on the display panel
And a display panel driving device . 2. A processor connected to an input side of a storage means provided in the first display control means, and an output side of the storage means provided in the first display control means is provided with a second display control means. a provided to connect the input side of the storage means, the processor is configured to send data to the input side of the storage means provided in the first display control means, the number of the number of predetermined bits of said display control means At a time interval obtained by multiplying the time required for storing the serial data in the storage means, the latch control for the data from the storage means is performed.
A display panel driving device for transmitting a latch signal . 3. The display panel driving device according to claim 2, wherein the processor controls the display control means to control the data.
The processes of delivery and the latch signal transmission of data at predetermined time intervals, a display panel driving device according to claim 2, characterized in <br/> that repeatedly executed in correspondence to the number of said display control means .