JPS6326928B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This invention relates to an integral type analog-to-digital conversion circuit that keeps the discharge current of a constant current discharge circuit constant regardless of fluctuations in the power supply voltage, and prevents fluctuations in the power supply voltage from being included in conversion errors. For the purpose of
supplying the output voltage of a drive voltage generation circuit that generates a constant drive voltage until it drops to a first predetermined voltage value lower than the nominal supply voltage of a predetermined DC power source; an output voltage of a reference voltage generation circuit that generates a reference voltage lower than the constant drive voltage up to a second predetermined voltage value lower than the first predetermined voltage value; is supplied to the reference voltage generation circuit through a first resistor, and is supplied to a second input for setting the charge discharge control voltage of the operational amplifier through a voltage divider circuit comprising a second and third resistor. It was configured to supply an output voltage.

[Industrial application field]

The present invention is an integral type analog device that maintains the discharge current of a constant current discharge circuit constant regardless of fluctuations in the power supply voltage.
Related to digital conversion circuits.

[Conventional technology]

There are various types of integral type analog-to-digital converter circuits, but in the integral type analog-to-digital converter circuit shown in Figure 9, conversion errors inevitably occur due to the circuit configuration when the power supply voltage fluctuates. Put it away. That is, the analog input voltage _V
The voltage is increased by V _BE and passes through the input buffer amplifier 1 and the switch 2, charging the capacitor 3 for a certain period of time. After this time has elapsed, the switch 2 is opened and the charge in the capacitor 3 is discharged via the constant current discharge circuit 4. During this time, the voltage of the capacitor 3 is constantly compared to the threshold voltage V _th of the comparison circuit 5.
is compared, and the voltage of capacitor 3 is the voltage
While the voltage is higher than V _th , the comparator circuit 5 generates a high level voltage. Then, from the time of the discharge circuit until the voltage of the capacitor 3 becomes less than the voltage V _th ,
By counting pulses of a predetermined period, the analog input voltage is converted into a digital value.

[Problem that the invention seeks to solve]

In this conventional integral type analog-to-digital conversion circuit, power is supplied to the non-inverting input + and the inverting input - of the operational amplifier 6 of the constant current discharge circuit 4, and a current I _R that determines the constant discharge current of the constant current discharge circuit 4 is set. The voltages V _CC and V _REF (V _REF is obtained by dividing the voltage V _CC with resistors R1 and R2 as shown in Figure 10) are voltage fluctuations of the power supply that supplies the circuit that generates the voltage V _CC . Since the current I R changes accordingly, the above-mentioned current I _R also changes. Therefore, as shown in FIG. 11, the slope I _R /C _H (C _H is the capacitance of the capacitor 3) of the discharge characteristic curve changes as shown by the dotted line. as a result,
Since _the conversion _{time tX} for _V It will be different from the digital value. In other words, A/D conversion errors occur due to fluctuations in the power supply voltage. The above-mentioned power supply voltage fluctuation occurs, for example, when the engine of an automobile equipped with the above-mentioned type of integral analog-to-digital conversion circuit is started.

The present invention was created in view of the above problems, and an object of the present invention is to provide an integral type analog-to-digital conversion circuit that does not cause conversion errors due to fluctuations in power supply voltage.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. In this figure, 14 is a capacitor that charges the analog input voltage value to be converted used in the integral type analog-to-digital conversion circuit at a constant rate for a predetermined period of time and stores a charge corresponding to the voltage value. 16 is a charge discharge transistor for discharging the charge stored in the capacitor 14. 15 is one operational amplifier 2 having first and second inputs for setting a constant current to the charge discharging transistor 16.
This is a constant current discharge circuit equipped with 2. A drive voltage for this constant current discharge circuit 15 is supplied from a drive voltage generation circuit 28. The drive voltage generating circuit 28 receives the supply voltage of a predetermined DC power supply and generates a constant drive voltage until the voltage fluctuation drops to a first predetermined voltage value lower than the nominal supply voltage. The output voltage of the reference voltage generation circuit 19 is applied to the first input of the operational amplifier 22 through the first resistor 21.
The circuit of the present invention is configured such that the output voltage of the reference voltage generation circuit 19 is supplied to the second input via the voltage divider circuit composed of the second and third resistors 23 and 24. has been done. The reference voltage generating circuit 19 receives the power supply voltage of the predetermined DC power supply and generates a second predetermined voltage value whose voltage fluctuation is less than the nominal power supply voltage and lower than the first predetermined voltage value. A constant reference voltage lower than the driving voltage is generated until the voltage drops to .

[Effect]

The analog voltage converted by the circuit of the present invention is applied to the capacitor 14, and the capacitor 14 is charged at a constant rate for a predetermined period of time.

From this charging stop time, the charge is discharged at a constant rate through the charge discharging transistor 16 of the constant current discharging circuit 15, and the time until the charging voltage drops to a predetermined voltage is measured using pulses of a predetermined period. . The pulse count value is used as a digitally converted value.

The operational amplifier 22 constituting the constant current discharge circuit for generating this count value is operated under the supply of the above-mentioned drive voltage, and the above-mentioned reference voltage is connected to the first and second inputs thereof. through the resistor 21, and the second and third resistors 2 constituting the voltage dividing circuit.
3 and 24. As a result, a constant discharge current flows through the charge discharging transistor 16.

Therefore, even if the supply voltage of the DC power supply fluctuates to an extent that does not reach the lower limit of the range as described above,
The above-mentioned constancy of the discharge current is maintained. Therefore, the conversion error due to that variation does not enter into the converted value.

〔Example〕

FIG. 2 shows the integral type analog-to-digital converter circuit 10 of the present invention, and its driving voltage V _CC and reference voltage V _REF discharge circuit are shown in FIG. In Figure 2, 12 is a power supply for level up (voltage value
V _BE ), 11 is an input buffer that receives the analog input voltage _V
It is connected to the collector of the discharging NPN transistor 16 of No. 5 and the + input of the comparator circuit 17. The emitter of the transistor 16 is connected via a resistor R to a reference potential, for example, ground potential. The other electrode of the capacitor 14 is also connected to a reference potential (earth potential). In addition, - of the comparator circuit 17
A threshold power supply 18 is connected between the input and a reference potential, such as ground potential. The voltage of this power supply 18 is expressed as V _th .

The constant current discharge circuit 15 is a reference voltage generation circuit 19
(See Figure 5) has an operational amplifier 22 whose + input is connected to the output terminal 20 via a resistor 21, and the - input of this operational amplifier 22 is connected between the output terminal 20 and a reference potential, for example, ground potential. A resistive voltage divider circuit (e.g. consisting of resistors 23 and 24) 25 connected to
is connected to the output of the operational amplifier 22, and the output of the operational amplifier 22 is
NPN transistor 26 and transistor 16
is connected to the base of transistor 26
The collector is connected to the + input of the operational amplifier 22, and its emitter is connected via a resistor 27 to a reference potential, for example, ground potential.

The input buffer 11, operational amplifier 22, and comparison circuit 17 are connected to an output terminal 29 of a drive voltage generation circuit 28 (see FIG. 3) that drives them.

The reference voltage generation circuit 19 and the drive voltage generation circuit 28 described above are well-known circuits that generate voltage fluctuations due to the operation of other load circuits (not shown), such as an automobile engine starting circuit equipped with an analog-to-digital conversion circuit. The connection terminal is connected to a DC power supply, such as a battery, that is subject to
Indicated by 0.

These circuits 19 and 28 have the same circuit configuration, and the voltage value divided by the resistor 31 and the resistor 32 and the voltage value divided by the resistor 33 and the resistor 34 are the output of the constant voltage generation circuit 36. The drive voltage generation circuit 28 includes a constant current source 37 and an NPN transistor Q.
1, the battery voltage is a predetermined value,
For example, at 11 volts or more, a constant current is passed through the resistors 31 and 32, so fluctuations in the battery voltage do not appear at the output terminal 29, but when the voltage drops below the predetermined voltage, the voltage at the output terminal 29 V _CC is the voltage drop of the constant current source 37 and the base of the transistor Q1 from the above predetermined voltage.
It is configured to be lowered by the emitter voltage drop, for example, by about 1 volt in total. Therefore, this drive voltage generating circuit 28 exhibits a drive voltage-battery voltage characteristic L1 as shown in FIG. 4 in the above-mentioned specific numerical example. In the drive voltage generation circuit 28, Q2 and Q3 are NPN type transistors, and 3
8 is a constant current source. For example, if the output voltage of the constant voltage generating circuit 36 is selected to be 1.23 volts, the resistance value of the resistor 31 is selected to be 1.23KΩ, and if V _CC is 10V, the resistance value of the resistor 32 is selected to be 8.77KΩ. . Note that V _CC is typically set at 4.75 to 15 volts.

In addition, in the reference voltage generation circuit 19, when the battery voltage is at a predetermined value, for example, 5 volts or more, a constant current is passed through the resistors 33 and 34 by the constant current source 39 and the NPN transistor Q4. Therefore, fluctuations in battery voltage are caused by output terminal 2.
Although it does not appear at 0, when it becomes lower than the predetermined voltage, the voltage V _REF at the output terminal 20 becomes lower than the predetermined voltage by the voltage drop of the constant current source 39 and the base-emitter voltage drop of the transistor Q4. for example, by about 1 volt in total. Therefore, this reference voltage generating circuit 19 exhibits a reference voltage-battery voltage characteristic L2 as shown in FIG. 4 in the above-mentioned specific numerical example. In the reference voltage generation circuit 19, Q5, Q
6 is an NPN type transistor, and 40 is a constant current source. For example, if the output voltage of the constant voltage generating circuit 36 is selected to be 1.23 volts, then the resistance value of the resistor 33 is 1.23KΩ, and if V _REF is 5 volts, then
The resistance value of resistor 34 is selected to be 3.77KΩ.

In general, integrated circuits are required to satisfy the condition of V _CC V _REF +2 volts between this V _REF and the above-mentioned V _CC . However, the 2 volts in the above inequality is not necessarily limited to this.

An example of the operational amplifier 22 of the constant current discharge circuit 15 is shown in FIG. 5, and this is a known circuit.
This operational amplifier 22 has PNP type transistors Q7 and Q8 which proportionally divide and flow the current of a constant current source 41 which receives a voltage V _CC , and each receives a reference voltage V _REF at its base via the above-mentioned connection circuit and connects it to a connection point. The NPN transistor Q9, which generates a constant bias voltage at the transistor 42 and receives this bias voltage, is configured to generate a voltage at its emitter that drives the transistors 26 and 16 at a predetermined operating level. A constant current I _R also flows through transistor 16 as a result of I _R being energized. In the operational amplifier 22, Q10,
Q11 is an NPN type transistor. The operational amplifier 22 is constructed so that the emitter voltage of the transistor Q9 is kept substantially constant within the permissible variation range of the voltage V _CC , so that the current I _R is kept constant. And I _R is made proportional only to the reference voltage that determines the full scale.

The operation of the circuit of the present invention having the above-mentioned configuration will be explained.

A DC power supply that supplies power to the analog-to-digital conversion circuit of the present invention, for example, when the circuit is installed in a car, the battery voltage is constant within a range that can generate the drive voltage V _CC of the analog-to-digital conversion circuit at a constant level. For example, if the drive voltage V _CC is within 10V as shown in FIG.
The reference voltage V _REF is also at a constant voltage of 5 volts as shown in FIG. 4, for example.

Therefore, the analog-to-digital conversion circuit does not produce conversion errors as described in the description of the conventional circuit above. That is, the analog input voltage _V
is increased by V _BE , and after passing through the input buffer 11, when the switch 13 is closed (see (6-1) in Figure 6), the capacitor 14 is charged at a constant rate for a predetermined time (see (6-1) in Figure 6). (See 6-2)). The charging voltage of the capacitor 14 is constantly compared with the threshold voltage V _th in the comparator circuit 17.
When the charging voltage reaches V _th , from that time on, the output of the comparator circuit 17 becomes high level ((6-
3)) occurs.

When the predetermined time has elapsed, the switch 13 is opened and charging of the capacitor 14 is stopped, and at the same time the charge of the capacitor 14 is discharged at a constant rate I _R /C _H (C _H is the charge of the capacitor 14 through the constant current discharge circuit 15). It is discharged by electrostatic capacitance).

Further, a counting operation is started simultaneously with the start of this discharge.

Then, a time comes when the charging voltage of the capacitor 14 drops to V _th . At this time, comparison circuit 1
The output of 7 becomes low level. In response to this transition to low level, the above-described counting operation is terminated, and the digital value of the analog input voltage is displayed from the count value.

Among the factors that determine the counting operation time in such conversion, I _R is a factor that may be changed by fluctuations in battery voltage. As long as the battery voltage is within the range mentioned above, I _R is determined. Since the reference voltage to be used is at a constant value, it is at a constant value. Therefore, even if the battery voltage fluctuates within the battery voltage range as described above, no conversion error will occur due to this variation.

Although the above-mentioned variation in battery voltage was slight, suppose that a heavy load circuit such as an engine starting circuit is connected to the battery and the battery voltage drops significantly. For example, near the lower limit of the allowable drive voltage of an analog-to-digital conversion circuit, e.g.
Suppose that the voltage drops to volts (V _CC V _REF + 2 volts).

Even if the supply battery voltage reaches such a level, the drive voltage generation circuit 28 continues to supply V _CC (permissible drive voltage) that allows each circuit part of the analog-to-digital conversion circuit to operate normally, and
As can be seen from the characteristic curve of FIG. 4, the reference voltage generating circuit 19 also continues to supply the constant current discharge circuit with the reference voltage V _REF having the same value as in the conversion operation described above, which is 5 volts in the above numerical example.

Therefore, even if there is such a drop in battery voltage, each circuit part of the analog-to-digital conversion circuit is supplied with a voltage that allows them to operate normally, and the factors that determine the counting operation time are Since I _R , which is a voltage-dependent variable factor in
There is no risk of introducing conversion errors into the converted digital value. In addition, conversion accuracy can be maintained,
Conversion reliability is maintained at a high level even under the usage environment described above.

Next, the embodiment shown in FIG. 7 will be described.

In this embodiment, a multiplexer 43 connects the input buffer 11 so that a plurality of analog input voltages can be converted by the analog-to-digital conversion circuit shown in FIG.
The analog-to-digital conversion circuit has the same configuration as the analog-to-digital converter shown in FIG. 2, except that it is provided on the input side of the circuit, and these same components are given the same reference numerals and their explanations will be omitted. Note that A ₀ , A ₁ , and A ₂ are channel address terminals.

Also, the conversion operation for each analog input voltage is
Further, the operation and effect are also the same as those of the above embodiment, and therefore, the explanation thereof will be omitted.

Furthermore, Figure 8 shows a modification example using a CMOS element.
It is almost the same as Fig. 7.

In the above embodiment, the case where there is a single DC power supply was explained, but the drive voltage generation circuit and the reference voltage generation circuit may be separate DC power supplies, and in that case, the voltage of those DC power supplies is The present invention is equally applicable to cases where the characteristics change as described above due to fluctuations in .

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even if the power supply voltage fluctuates within a predetermined range, there is no possibility that a conversion error will be introduced into the converted digital value.

Therefore, a high degree of conversion accuracy can be maintained, and
It is possible to maintain high conversion reliability in a usage environment where the power supply voltage fluctuates.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, and Fig. 3 is a diagram showing the V _CC and
V _REF generation circuit diagram, Figure 4 shows V _CC of the circuit in Figure 3,
V _REF -Battery voltage characteristic curve diagram, Figure 5 is a detailed diagram of the operational amplifier, Figure 6 is various curve diagrams for explaining fluctuating operation, Figures 7 and 8 show other embodiments of the present invention. The figure shown in Figure 9 is a conventional integral type analog.
A digital conversion circuit diagram, FIG. 10 is a reference voltage generation circuit diagram of FIG. 9, and FIG. 11 is a discharge characteristic curve diagram of a conventional conversion circuit. In FIGS. 1 to 3, 5, 7, and 8, 10 is an integral type analog-to-digital conversion circuit, 13 is a switch, 14 is a capacitor, and 15
is a constant current discharge circuit (charge discharge transistor 1
6, operational amplifier 22), 19 is a reference voltage generation circuit;
21, 22, 23 are first, second and third resistors;
28 is a drive voltage generation circuit.

Claims (1)

[Claims] 1. A constant current discharging circuit including a charge discharging transistor 16 and one operational amplifier 22 having first and second inputs for setting a constant current to the transistor 16, After charging the capacitor 14 at a constant rate of the analog input voltage for a predetermined period of time, the charged charge is discharged through the charge discharging transistor, and the charging voltage of the capacitor is set to a predetermined value from the discharge start time. In an integral type analog-to-digital conversion circuit that converts an analog input voltage into a digital value by counting pulses of a predetermined period until reaching a drive voltage generation circuit 28 that generates a constant drive voltage until it drops to a first predetermined voltage value that is lower than the supply voltage; and a second drive voltage that is lower than the first predetermined voltage value.
a reference voltage generation circuit 19 that generates a constant reference voltage lower than the driving voltage until the voltage drops to a predetermined voltage value; the operational amplifier 22 is driven by the driving voltage, and the reference voltage is The reference voltage is applied to the first input of the operational amplifier 22 through the first resistor 21, and the voltage obtained by dividing the reference voltage by the second and third resistors 23 and 24 is applied to the second input of the operational amplifier 22. An integral type analog-to-digital conversion circuit characterized in that an integral type analog-to-digital conversion circuit is applied to an input.