JPS63267068A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make chrominance components of plural horizontal lines simultaneity so as to output them by providing plural read registers and simultaneously reading signal charges of plural lines. CONSTITUTION:Lights receiving elements 2, 2...2, transfer registers 5, 5...5 transferring the signal charges accumulated in the light receiving elements 2, 2...2 and plural read registers 10 and 11 reading the signal charges transferred by the transfer registers 5, 5...5 are provided. With plural read registers 10 and 11, the signal charges of plural horizontal lines are simultaneously read. With using and applying a single plate type filter array for a single plate type color camera, the chrominance components of plural horizontal lines are made simultaneity so as to be outputted, whereby it comes to be unnecessary to provide a one horizontal delay circuit and make the chrominance components of plural horizontal lines simultaneity. Thus, a signal processing circuit can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a solid-state imaging device suitable for use in, for example, a single-panel color camera.

[Summary of the invention]

The present invention includes a light-receiving element, a transfer register that transfers signal charges accumulated in the light-receiving element, and a plurality of readout registers that read out the signal charges transferred by the transfer register. By reading out the signal charges of the horizontal lines simultaneously, the signal processing circuit can be simplified and all pixels can be connected.

It is designed so that it can also be used for delivery.

[Conventional technology]

Conventionally, a solid-state imaging device for use in a single-panel color camera has been proposed, the planar structure of which is schematically shown in FIG.

This solid-state imaging device adopts the so-called interline transfer method and is a solid-state imaging device with a P-type silicon substrate (1
) on the surface side of the photodiode (2)
(2)...(2) is arranged in a matrix of 492 (vertical)
510 (Horizontally) Individually arranged light receiving sections (3) are provided, a subject image is formed on the surface of the light receiving section (3), and a signal charge corresponding to the brightness of this pulsating object image is sent to each light receiving element ( 2)
(2)・−(2) are stored. In this case, on the surface of this light receiving part (3) there are 4
A color filter array consisting of 92 (vertical) x 510 (horizontal) color filters arranged in a mosaic pattern.
1(2)...(2), the signal charge based on the colored light passing through each filter is transmitted to each light receiving element (2) (
2) It is configured to accumulate in (2). still,
This color filter array (4) has G (green), B (blue), G... on the first horizontal line L1 and the second horizontal line L2, respectively.
・A primary color filter of B is arranged and the first horizontal line L1
and G, R (red), G... on the fourth horizontal line L4, respectively.
- R primary color filters are arranged, and this arrangement is repeated from the fifth horizontal line L11 onwards.

In addition, light-receiving elements (2) (2) arranged in a matrix
...(2) A so-called vertical register (5) (5) consisting of a charge-coupled device (hereinafter referred to as COD) which forms a transfer register is provided for each column of (2), and each light receiving element (
2) Read out the signal charges accumulated in (2)...(2) using a frame accumulation method (frame readout method),
That is, the signal charges accumulated in each light-receiving element (2) (2)...(2) are read out every alternate horizontal line for each field, interlaced, and the signal charges are transferred vertically, that is, downward in the plane of the paper. It is designed to be transmitted towards the target.

In addition, a horizontal register (6) consisting of a CCD serving as a read register is provided on the output side of the vertical register (51(5)...(5)), and the vertical register (5) (51(5)...
- The signal charge transferred by (5) is transferred horizontally, ie, toward the left side of the page, every horizontal line.

Further, on the output side of this horizontal register (6), for example, a floating dephasing amplifier (F
floating diffusion amplifier
er) consists of an output section (a sword is provided, and a horizontal register (
An image signal based on the signal charge transferred by 6) is outputted to an output terminal (8) derived from this output section (7).

In this solid-state imaging device, a color filter array (4) as shown in FIG. 8), as shown in FIG. 9, in the first field, G, B, G,
-B color signal, third horizontal line L3 G, R, G,...
・R color signal, ... 491st horizontal line L 411 G, R, G, .
,...B color signal, G, R, G of the fourth horizontal line L4
,...R color signal,...492nd horizontal line L4S
L, G, R, G, . . . 1 color signals are sequentially output. Then, from the third field onward, the same reading as in the first field and the second field is repeated.

[Problem that the invention seeks to solve]

Incidentally, in such a conventional solid-state imaging device, the G signal is obtained on all horizontal lines, but the R signal and the B signal are sequentially output for each horizontal line. Therefore, in a single-chip color camera using such a conventional solid-state imaging device,
For example, as shown in Fig. 1θ, after synchronizing the preceding and following horizontal lines, R, G
, B signals are obtained, and then these R, G, and B signals are supplied to a predetermined encoder to form a composite color signal. For this reason, such a single-chip color camera requires a one-horizontal period delay circuit for synchronizing the color signals of the preceding and succeeding horizontal lines, which has the disadvantage of complicating the signal processing circuit accordingly.

Further, in such a solid-state imaging device, in order to obtain a high-resolution image, it is required to be able to read out all pixels in each field.

In view of the above, it is an object of the present invention to provide a solid-state imaging device that eliminates the above-mentioned disadvantages and is also capable of supporting all-pixel readout.

(Means for Solving the Problems) The solid-state imaging device according to the present invention includes a light receiving element (2) (2)...(2) and a light receiving element (2) as shown in FIGS. 1 and 2, for example. 2) Transfer register (5) that transfers the signal charge accumulated in (2)-...(2) (5)...(
5) and this transfer register (5) (5)...(5)
It is equipped with a plurality of readout registers (10) (11) for reading out the signal charges transferred by the above, and the signal charges of a plurality of horizontal lines can be read out simultaneously by the plurality of readout registers (10) (11). .

[Effect]

In the present invention, a plurality of successive registers (10)
(11) is provided so that the signal charges of multiple lines can be read out simultaneously. For example, when using the single-chip color filter array (4) shown in Fig. 3 for use in a single-chip color camera, multiple lines The horizontal line color signals are synchronized and output.

(Embodiment) Hereinafter, an embodiment of the solid-state imaging device according to the present invention will be described with reference to FIGS. 1 to 7. In this example,
An interline transfer type solid-state imaging device that can read signal charges of two horizontal lines at the same time will be described. In FIGS. 1 and 2, parts corresponding to those in FIG. 8 are given the same reference numerals.

In this example, a P-type silicon substrate (
A light receiving element (2) consisting of a photodiode is placed on the surface side of 1).
(2) - (2) is provided in a matrix of, for example, 492 (vertical) x 510 (horizontal) light receiving sections (3), and a subject image is formed on the surface of this light receiving section (3), A signal charge corresponding to the brightness of this subject image is transferred to each light receiving element (2) (
2) Make it possible to accumulate in (2). In this case, 492 (vertical) x 510 pixels as shown in FIG.
A color filter array (4) consisting of (horizontal) color filters arranged in a mosaic pattern is arranged.
) for each color filter on each light-receiving element (2) (2)-...(
2), the signal charge based on the colored light passing through each color filter is transmitted to each light receiving element (2) (2)...(2)
so that it can be stored in This color filter array (4) has G on the first horizontal line L1 and the second horizontal line L2, respectively.
B, G, . . . B primary color filters are arranged, and G, R, G are arranged on the third horizontal line L3 and the fourth horizontal line L4, respectively.
, -...R primary color filters are arranged, and this arrangement is repeated from the fifth horizontal line onwards.

In addition, light receiving elements arranged in a matrix (2) (2) -
・A vertical register (5) (5)...(5) consisting of COD forming a transfer register is provided for each column of (2), and the data is accumulated in each light receiving element (2)(2)...(2). The signal charge stored in each light receiving element (2) (2)...(2) is read out by the frame accumulation method (frame readout method), that is, the signal charge accumulated in each light receiving element (2) (2)...(2) is read out for each field and for each alternate horizontal line. , for example, in the first field, the first horizontal line L1
, third horizontal line L3...491st horizontal line L4
11 Read out the signal charges of the light receiving elements (2) (2) .
4th horizontal line L4...492nd horizontal line L4@2
Interlacing is performed by reading out the signal charges of the light-receiving elements (2) (2)-(2), and the signal charges can be transferred vertically, that is, downward in the plane of the paper. In this case, this vertical register (5) (5)...(
5) enables driving by a so-called four-phase drive system. Specifically, as shown in FIG. 2, a charge transfer region (12) (12)...(12) consisting of an N-type region is provided on the surface side of a P-type silicon substrate (1), and this charge transfer region is provided. 5i on transfer area (12) (12)-(12)
(Transfer type th (13At) (13^2) (13A
3) (13A) is provided (this figure shows only the transfer electrode of the final bit), and this transfer electrode (13Al(13A) is provided).
^2) < 13A3) Figure 4 A in (13A4)
~4th phase drive pulse φv1. shown in the fourth diagram. φV21φ
Make it possible to supply V3 +φv4. Note that (3G) indicates a channel stop area.

Further, a first gate section (14) is provided on the output side of the vertical register (6) (6)...(5), and a first horizontal register consisting of COD is connected via this first gate section (14). (
10)' and a second horizontal register (11) of the same <COD is provided via the second gate part (15).

Here, the first gate part (14) is an N-type region (12) (12), which forms the charge transfer region of the vertical register (5) (5)...(5), as shown in FIG. 12) form an N-type region (16) (16)-(16),
This N type region (16) (16) - (16) is used as a gate region, and this N type region (16) (16
)・-(16) is provided with a gate electrode (17) made of polycrystalline silicon via an insulating layer, and this gate electrode (17
) by supplying the first gate pulse φG1 shown in FIG. 4E to the vertical register (ri) (5)・-U
S) charge transfer region (12) (12)...(12
) is transferred to the first horizontal register (1
Make it possible to transfer to 1.

Further, the first horizontal register αl connects the N-type region (18) extending in the horizontal direction to the first gate portion (14) as shown in FIG.
) is provided so as to be in contact with the gate region (16) (16)--(16), and this N-type region (18) is used as a charge transfer region, and an insulating layer is provided on this charge transfer region (18). Transfer electrode made of polycrystalline silicon (19S1)
(19Tt) (1952) (19T2)...(
1951) (19T1) and transfer electrodes (19T1) were provided.
St ) (19TL) ... (19St) (
19TL) and (1952) (19T2)...(
1952) (19T2) in Figures 4F and 4, respectively.
Supplying two-phase drive pulses φH1 and φH2 shown in Figure H,
The signal charges transferred from the vertical registers (51(5)...(5) can be transferred in the horizontal direction, that is, toward the left side of the page. In this case, the transfer electrodes (1951)
(1952) and cof) Transfer electrode (19St) (1
952) below the charge transfer region ('18Sz) (1
8S2) become the so-called storage electrode and storage area, respectively, and the transfer electrode <19Tz)
(19T2) and this transfer electrode (19ft) (
Charge transfer region (18Tt) (19T2) below
8T2) to become a so-called transfer electrode and a transfer region, respectively. Here, in this example, the impurity concentration of the charge transfer region (1851) (18S2) below the transfer electrode (19St) (19S2) is calculated as the impurity concentration of the charge transfer region (18Tz) (18T2) below the transfer electrode (19Tz) (19h). Transfer electrode (19Sz) so that the impurity concentration is higher than that of
(1952) and this transfer electrode (19Sz)
(19S2) Lower charge transfer region (18Sx) (
18S2 ) as a storage electrode and a storage area, respectively, and a transfer electrode (19Tx ) (19T2
) and the electrode transfer regions (18Tt) (18T2) under these transfer electrodes (19Tl) (19C2) are used as transfer electrodes and transfer regions, respectively, and during signal charge transfer, the charge transfer regions (18Ss) and (1852)
The potential level of each charge transfer region (18Tl
) and (18T2), so that they are deeper than the horizontal level.

Further, the second horizontal register (11) is provided with a charge transfer region (20) consisting of an N-type region parallel to the charge transfer region (18) of the first horizontal register (10), and this charge transfer region (20) A transfer electrode (21S
x) (21Tl) (2152) (21T2
)...(21Sx ) (21Tz ), and transfer electrodes (21Sz ) (21
1) and (21S*) (21T2), two-phase drive pulses φ%41 and φH shown in FIGS. 4F and 4H, respectively, are applied.
2, the first gate section (14), first horizontal register section (10) and second gate section (15
) so that the signal charge transferred through the gate can be transferred in the horizontal direction, that is, toward the left side of the page. In this case, the transfer electrode (21SL) of this @2 horizontal register (11)
(21Tl) (2152) (21T2) are the transfer electrodes (19S & 2) of the first horizontal register (10), respectively.
) (19Tt) (1952) (19T2
) and the transfer electrode (21S1).
(2152) and (21Tt) (21T2) become a storage electrode and a transfer electrode, respectively. That is, similarly to the first horizontal register (10), the m load transfer area (20St) (2052) below the transfer electrodes (21Sz) (2152) is used as a storage area, and the area below the transfer electrodes (21T1) (21T2) is used as a storage area. The charge transfer regions (20Tt) (20T2) are made to serve as transfer regions.

Further, the second gate section (15) provided between the first horizontal register (10) and the second horizontal register (11) is connected to the gate region (16) (16) of the first gate section (14).
)...(16) is connected to the first horizontal register (1
0) storage area (1BSL) (18S1
)...(18Sz) and this storage area (18Sz)
t)(18Si)...Storage area (20
52) (2032)...(2032) and the N-type region (
22) (22)...(22), this N-type region (22) (22)...(22) is used as a gate region, and this gate region (22) (22)...
- P type for areas other than (22).

Channel stop region (23) formed by diffusing impurities
(23)...(23) and on these N-type regions (22) (22)--(22) and channel stop regions (23) (23)...-(23) via an insulating layer. gate electrode (2) made of polycrystalline silicon.
4), and this gate electrode (2
4), the second gate pulse φG2 shown in FIG. 4G is supplied so that the signal charge can be transferred from the first horizontal register (10) to the second horizontal register (11).

Furthermore, a first output section (25) consisting of a floating diffusion amplifier is provided on the output side of the first horizontal register (10) and the second horizontal register (11), respectively.
) and a second output section (26), and these first
A first output terminal (27) and a second output terminal (28) are derived from the output section (25) and the second output section (26).

Next, the operation of the solid-state imaging device of this example will be explained with reference to FIGS. 4 to 7.

In the solid-state imaging device of this example, the light receiving element (2) (2
)...The signal charge accumulated in (2) is read out from this light receiving element (2) (2)...(2) to the vertical register +5) 15)...(5) during the vertical blanking period. The data is then transferred to the first horizontal register (10) and the second horizontal register (11) using the horizontal blanking period. Here, in the first field, the light receiving elements (
2) (2) - (21 signal charge is vertical register (5)
(5).-(5) and transferred to the first horizontal register (10) and the second horizontal register (11). Also, in the second field, even number line L2 *
L4...Lss* light receiving element (2) (2)-(
21 signal charges are vertical register (6) (5)・-(6
), this signal charge is transferred to the horizontal register (9), and from the third field onward, the operations during the first field and the second field are repeated.

Here, FIG. 5 shows the potential level of the surface area of the P-type silicon substrate (1) along the v-v' line in FIG. The signal charge Q1-1 accumulated in the leftmost light receiving element (2) of the third horizontal line and the signal charge Q3-1 accumulated in the leftmost light receiving element (2) of the third horizontal line are transferred to the second horizontal register (11) and First horizontal register (10>
FIG. 5A shows the state at time t1 when the horizontal blanking period shown in FIG. The last bit charge transfer area (
12) and the charge transfer area 1 bit before the slow ending bit (1
2) shows the state transferred. At this point t1
Now, as shown in Fig. 4, the transfer electrode (13at > (13
A2 ) is supplied with high level voltage VW, and the transfer electrode (
Since low level voltage VL is supplied to 1383) (13A4), signal charge Q1-1 is accumulated in the charge transfer region (12) under the transfer electrode (13AL) (13A2) of the final bit, and the signal charge Charge Q3-1 is the transfer electrode (13Az) (13A゛2) one bit before the final bit.
is stored in the charge transfer region (12) below.

After that, the signal charge Q t-1 is transferred to the second horizontal register (1
1), and the signal charge Q3-1 is also transferred to the first horizontal register (10).
The transfer of 1-1 will be explained.

After time ti, at time t2, the voltage of transfer type 8i (13As) changes from low level voltage VL to high level voltage VH, and then at time t3, the voltage of transfer electrode (13^1) changes from high level voltage VH to low level. Then, at time L4, the voltage of the transfer electrode (13A4) changes from the low level voltage VL to the high level voltage VH, and then at time ts, the voltage of the transfer electrode (13A2) changes from the high level voltage VH to the low level. Since the level voltage is VL, the potential state of the charge transfer region (12) passes through the states shown in FIGS. 5B, 5C, and 5, and becomes the state shown in FIG. -1 is also transferred as shown in FIGS. 5B, 5C and 5th diagram, and as shown in FIG. 5E, the charge transfer region (12
).

Next, at time t6, the gate electrode (
17) is changed from the low level voltage VL to the high level voltage VH, the signal charge Q1-1 is stored in the first horizontal register (10) to which the high level voltage VH' has been supplied since time t1. The data is transferred to the area (18SL).

Next, at time t7, the voltage of the transfer electrode (13A3) is changed from high level voltage VH to low level voltage VL, and then at time t$, the voltage of transfer electrode (13A4) is changed from high level voltage VH to low level voltage VL. , followed by time t
At step 10, the voltage of the gate electrode (17) of the first gate part (14) is changed from the high level voltage vI4 to the low level voltage VL, and the voltage of the gate electrode (2) of the second gate part (15) is changed from the high level voltage vI4 to the low level voltage VL.
4) is changed from the low level voltage VL'' to the high level voltage V)I#, so the potential state is as shown in Figure 5G.
After passing through the state shown in FIG. 5I, the state shown in FIG.
Storage area (1851) of horizontal register (10) of
and is accumulated across the gate region (22) of the second gate portion (15).

Next, at time t1, the voltage of the storage electrode (19Si) of the first horizontal register (10) becomes a high level voltage ■H'
to the low level voltage vL', and then at time t 12
storage electrode (21) of the second horizontal register (11) at
32) is changed from the low level voltage VL' to the high level voltage vH', and then at time 113 the voltage at the second gate section (
The voltage of the gate electrode (24) of 15) is a high level voltage v
Since the low level voltage VL' is applied from H', the signal charge Q1-1 is accumulated in the gate region (22) of the second gate part (15) at time t11 as shown in FIG. At time t12, the second gate part (1
5) gate area (22) and the second horizontal register (11
), and then at time t13, as shown in FIG. 5M, it is stored in the storage area (2052) of the second horizontal register (11). Which state will be maintained until the end of the period? The signal charge Q1-1 accumulated in the leftmost light receiving element (2) of the first horizontal line L1 in this manner is transferred to the second horizontal register (11).

Next, the transfer of the signal charge Q3-x accumulated in the leftmost light receiving element (2) of the third horizontal line L3 will be explained.

This signal charge Q)-1 is accumulated in the charge transfer region (12) under the transfer electrode (13Az) (13A2) one bit before the final bit at time t1, but after that, at time t1
2, the voltage of the transfer electrode (13^3) is low level voltage VL
Then, at the time t3, the voltage of the transfer electrode (13Az) is changed from the high level voltage VW to the low level voltage VL, and then at the time t4, the voltage of the transfer electrode (13Az) is changed from the high level voltage VW to the low level voltage VL.
The voltage of the transfer electrode (13A4) is changed from the low level voltage VL to the high level voltage VH, and then at time t6 the voltage of the transfer electrode (13A4) is changed from the low level voltage VL to the high level voltage VH.
2) voltage changes from high level voltage VH to low level voltage V
Then, at time t6, the voltage of the transfer electrode (13Az) changes from the low level voltage VL to the high level voltage VW, and then at the time t6, the voltage of the transfer electrode (13A3) changes from the high level voltage VH to the low level. The voltage at the transfer electrode (13A2) decreases from the low level voltage VL to the high level voltage vH at time t.Then, at time t11, the voltage at the transfer electrode (13^4) decreases to the high level voltage vH. to the low level voltage VL, and then to the time tt.
At o, the voltage of the transfer electrode (13^3) is low level voltage VL
Then, at the time t11, the voltage of the transfer electrode (13^1) is changed from the high level voltage vH to the low level voltage VL, and then at the time 112, the voltage of the transfer electrode (13A4) is changed to the low level voltage VW. The level voltage VL is changed to the high level voltage VH, and then at time tL3, the voltage of the transfer electrode (13A2) is changed from the high level voltage VH to the low level voltage VL, so the potential state is the fifth potential state.
The state shown in FIG. 5M is reached after passing through the states shown in FIGS. As shown in the figure, the final pit transfer electrode (13A3) (13＾鴫)
It is stored in the lower charge transfer region (12).

Next, at time t14, the voltage of the gate electrode (17) of the first gate section (14) is changed from the low level voltage VL to the high level voltage VH, so the signal charge Q3-1 is increased at the time t14.
14 and the first horizontal register (10) as shown in FIG.
is transferred to the storage area (1BSL).

Next, at time t1g, the voltage of the transfer electrode (13A3) is changed from the high level voltage VN-7 to the low level voltage Vt, and then at time tsta, the voltage of the first horizontal register (10) is changed from the high level voltage VN-7 to the low level voltage Vt.
The voltage of the storage electrode (1951) is changed from the low level voltage ■L' to the high level voltage vH', and then at time t
At time tll, the voltage of the transfer electrode (13A4) is changed from high level voltage VW to low level voltage VL, and then at time tll.
At time l, the voltage of the gate electrode (17) of the first gate part (14) is changed from the high level voltage VH to the low level voltage VL, and then at the time tzs, the voltage of the gate electrode (17) of the first horizontal register (10) is changed from the high level voltage VH to the low level voltage VL. ) is changed from high level voltage vH' to low level voltage VL', the potential states are shown in Figure 5 0, Figure 5 P, Figure 5 Q, and Figure 5 R (Figure 6 A). Figure 5 S (Figure 6 B) after the state
As a result, the signal charge Q3-t is transferred to the storage area (18S) of the first horizontal register (10).
z ) to the storage area (1852) of the first horizontal register (10). In this way, the signal charge Q3-1 is transferred to the horizontal register (10) of c5t and accumulated in the storage area (1852). In addition,
In this FIG. 5, Q5-1 is the WS5 horizontal line L6
shows the signal charge accumulated in the leftmost photodetector (2),
Q7-1 is the light receiving element (2
) indicates the accumulated signal charge.

In the solid-state imaging device of this example, all the light receiving elements (2) (2)...(
The signal charges accumulated in 2) and all the light receiving elements (2) of the first horizontal line L1 (2)...(2) are stored in the storage area of the first horizontal register (10), respectively. (18S2) (1852)...(18S
2) and the storage area (20S2) (2052)...(2052) of the second horizontal register (11) and are stored therein, but later, when the horizontal valid period comes at time t20, the first horizontal Since the high-speed two-phase drive pulses φH1 and φH2 shown in FIGS. 4F and 4H are supplied to the register (10) and the second horizontal register (11),
The signal charges of the third horizontal line L3 accumulated in the first horizontal register (10) and the signal charges of the first horizontal line L1 accumulated in the second horizontal register (11) are respectively transferred to the first output section ( 25) and a second output section (26). In this example, since the color filter array (gradient is provided) as shown in Fig. 3, the first output terminal (27)
As shown in FIG. 7A, the G, R,
G...R color signals are obtained, and the second output terminal (28)
As shown in FIG. 7B, the first horizontal line L1 is G, B,
G...B color signals are obtained, and from then on, the first output terminal (
27), G, R, G-R color signals of the seventh horizontal line L7, ... G, R, G-R color signals of the 491st horizontal line L4sx are obtained, and the second output terminal (28 ) has the fifth
Color signal of horizontal line L6...489th horizontal line L
4) G, B, G-...B color signals are obtained.

Also, in the second field, the first output terminal (2
7), as shown in FIG. 7C, G of the fourth horizontal line L4,
R, G - R color signal, G of the 8th horizontal line L8,
R, G...R color signals, . . . G, R, G-...R color signals of the 492nd horizontal line L482 are obtained, and the 7th As shown in the figure, the second
G, B, G-B color signals of the horizontal line L2, G, B, G, -B color signals of the 6th horizontal line L@...490th
G, B, G-...B color signals of the horizontal line L411G are obtained.

In this way, the solid-state imaging device of this example is provided with the first horizontal register (10) and the second horizontal register (11), and the color signals of two adjacent horizontal lines, that is, the color signals of the third horizontal line L3, are provided. G, R, G...R color signals and G, B, G-8 color signals of the first horizontal line L1,...491st horizontal line L 411 G, R, G-...R color signals G and B of the color signal and the 489th horizontal line L48.

G...B color signal, G and R of the fourth horizontal line L4.

G...R color signals and G and B of the second horizontal line L2.

G-B color signal...G of the 492nd horizontal line L412.

R, G-R color signals and 490th horizontal line L4110
Since the G, B, and G-B color signals can be sequentially obtained from the first output terminal (27) and the second output terminal (28), the solid-state imaging of this example In a single-chip color camera using this device, R and B are obtained by performing predetermined sampling of the color signals of the two horizontal lines obtained at the first output terminal (27) and the second output terminal (28). .

A G signal can be obtained, and by supplying the R, B, and G signals to a predetermined encoder, a decoded color signal can be obtained.

Therefore, in a single-chip color camera using the solid-state imaging device of this example, a one-horizontal period delay circuit is provided as in the case of using the conventional solid-state imaging device shown in FIG. There is no need to synchronize the signals, and there is an advantage that the signal processing circuit can be simplified accordingly.

In addition, according to the solid-state imaging device of this example, it is possible to read out the signals of two horizontal lines at the same time, so it is possible to cope with increasing the density of the light receiving section, and it is also possible to cope with all pixel readout. can obtain high-resolution images, so the so-called I! The present invention has the advantage that it can be applied to DTV, and that the degree of freedom in color coding of a single-panel color filter array is increased, and image quality can be improved.

In the above embodiment, the so-called G stripe R/B line sequential color filter array (4) shown in FIG. 3 was used to make it applicable to a single-chip color camera. Instead of this, various other color filter arrays can be used, and it can also be applied to a two-chip color camera and a three-chip color camera.

Furthermore, in the above embodiments, the case where the present invention is applied to an interline transfer type solid-state imaging device has been described;
Instead, it can also be applied to a frame transfer type solid-state imaging device.

Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and can take various other configurations without overstating the gist of the present invention.

〔Effect of the invention〕

According to the present invention, when a single-chip color filter array is used in a single-chip color camera, the color signals of a plurality of horizontal lines are output in a synchronized manner. In the camera, there is no need to provide a one-horizontal period delay circuit to synchronize the color signals of multiple horizontal lines as in the case of using the solid-state imaging device shown in FIG.
There is an advantage that the signal processing circuit can be simplified accordingly.

Furthermore, according to the present invention, since color signals of multiple horizontal lines can be obtained simultaneously, it is possible to cope with increasing the density of the light receiving section, and it is also possible to cope with all pixel readout. Since it is possible to obtain images with high resolution, the so-called I! It has the advantage that it can be used for DTV, and that the degree of freedom in color coding of the single-panel color filter array is increased, and image quality can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a schematic configuration of an embodiment of a solid-state imaging device according to the present invention, FIG. 2 is a plan view showing essential parts of the present invention, and FIG. 3 is a color filter used in the example shown in FIG. 4 is a waveform diagram for explaining the present invention; FIG. 5 is a diagram showing the potential level of the surface area of the substrate along line v-v' in FIG. 2; and FIG. The figure is Vl-V in Figure 2.
A diagram showing the potential level of the surface area of the substrate along the l' line, FIG. 7 is a diagram showing the color signals obtained at the first output terminal and the second output terminal, and FIG. 8 is a diagram showing the conventional FIG. 9 is a plan view showing a schematic configuration of the solid-state imaging device; FIG. 9 is a line diagram showing color signals obtained at the output terminal of the solid-state imaging device of the example in FIG. 8; and FIG. 10 is a line for explaining the example in FIG. It is a diagram. (1) is a P-type silicon substrate, (2) is a light receiving element, (3)
is the light receiving section, (color is the color filter array, (5) is the vertical register, (10) is the first horizontal register, (11) is the second
horizontal register, (14) is the first gate part, (15)
is the second gate part, (25) is the first exit part, (26)
is the second output section, (27) is the first output terminal, (28)
is the second output terminal.

Claims (1)

[Claims] It is equipped with a light receiving element, a transfer register that transfers signal charges accumulated in the light receiving element, and a plurality of readout registers that read out the signal charges transferred by the transfer register, and the plurality of readout registers read out the signal charges transferred to the plurality of horizontal lines. What is claimed is: 1. A solid-state imaging device characterized in that signal charges of 1 and 2 are simultaneously read out.