JPS63267069A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain the picture of high resolution by matching a vertical register to the one bit of one light receiving element and simultaneously reading the signal charges of plural horizontal lines by plural horizontal registers. CONSTITUTION:The light receiving elements 2, 2...2, the vertical registers 9, 9...9 for transferring the signal charge stored in the light receiving element vertically, the plural horizontal registers 10, 11 for horizontally transferring the signal charge transferred by the vertical register and output parts 12, 13 for detecting the signal charge transferred by the plural horizontal registers are provided. The vertical registers 9, 9...9 are matched to the one bit of the vertical register with respect to the one light receiving element 2 and the signal charge of the plural horizontal lines are simultaneously transferred to the plural output parts 12, 13 by the plural horizontal registers 10, 11. Accordingly, all picture elements are read. Thereby, the picture of the high resolution can be obtained and a signal processing circuit can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device suitable for use in, for example, a single-panel color camera.

[Summary of the invention]

The present invention provides an interline transfer type solid-state imaging device in which a vertical register is configured to correspond to one focus of one light receiving element, and a plurality of horizontal registers are provided to simultaneously read signal charges of a plurality of horizontal lines. This makes it possible to read out all pixels and obtain a high-resolution image, and also to simplify the signal processing circuit.

[Conventional technology]

Conventionally, a solid-state imaging device for use in a single-panel color camera has been proposed, the planar structure of which is schematically shown in FIG.

In this FIG. 12, (1) shows a P-type silicon substrate, and in this solid-state imaging device, a light receiving element (2) consisting of a photodiode is provided on the surface side of this P-type silicon substrate 11).
) +21...(2) in matrix form 492 (vertical > x si.

(Horizontal) Individually arranged light receiving sections (3) are provided, a subject image is formed on the surface of the light receiving section (3), and a signal charge corresponding to the brightness of this subject image is transmitted to each light receiving element 12) (21・・・
・It is designed to accumulate to +21. In this case, on the surface of the light receiving part (3), there is a 49
A color filter array (4) consisting of 2 (vertical) x 510 (horizontal) color filters is arranged, and each color filter of this color filter array (4) is connected to each light receiving element (2) (21
... Corresponding to (2), the signal charge based on the colored light passing through each color filter is transmitted to each light receiving element (21 (21...
(2) is made to accumulate. Note that this color filter array (4) has G (green) on each of the first horizontal line L1 and the second horizontal line L8.

B (blue), G...B primary color filters are arranged, and G and R are arranged on the third horizontal line L and the fourth horizontal line L, respectively.
(Red), G...R primary color filters are arranged, and this arrangement is repeated from the fifth horizontal line L onwards, and is a so-called G stripe R/B line sequential color filter array. It is called.

In addition, light receiving elements (2) (2) arranged in a matrix...
・A vertical register +51 (5)...(5) consisting of a charge-coupled device (hereinafter referred to as COD) is provided for each column of (2), and each light receiving element (23(2)...(2) The signal charge accumulated in each light receiving element (2) is read out by a frame accumulation method (frame readout method).
...The signal charges accumulated in (2) are read out every field and every alternate horizontal line to perform interlacing, and the signal charges are transferred in the vertical direction, that is, toward the bottom of the page. .

In addition, a horizontal register (6) consisting of a CCD is provided on the output side of this vertical register +51 +51...(5), and signal charges transferred by the vertical register (5) (5)...(5) is transferred in the horizontal direction, ie, toward the left side of the page, one horizontal line at a time.

The output side of this horizontal register (6) is equipped with, for example, a floating dephasing amplifier (
Floatlng diffusion as+pli
an output terminal (8) from which an image signal based on the signal charge transferred by the horizontal register (6) is derived from the output section (7);
It is made so that you can get it.

Here, in this solid-state imaging device, the 13i! A color filter array (4) as shown in FIG. G of horizontal line L1
, B, G, . . . color signal of B, G of third horizontal line L,
, R, G, . . . R color signals, . . . G, R, G, .
G, B, G, ...B color signals of t, fourth horizontal line L
, G, R, G, . . . R color signals of the 492nd horizontal line L9, 8 are sequentially output. Then, from the third field onwards, the same reading as in the first field and the second field is repeated.

[Problem that the invention seeks to solve]

Incidentally, in such a conventional solid-state imaging device, the G signal is obtained on all horizontal lines, but the R signal and the B signal are sequentially output for each horizontal line. Therefore, in a single-chip color camera using such a conventional solid-state imaging device,
For example, as shown in Figure 15, after synchronizing the preceding and following lines, R, G, B
A signal is obtained, and then the R, G, and B signals are supplied to a predetermined encoder to produce a decoded color signal.

For this reason, the single-chip color camera requires a one-horizontal period delay circuit for synchronizing the color signals of the preceding and succeeding horizontal lines, which inconveniently complicates the signal processing circuit.

Further, in such a solid-state imaging device, it is required to be able to read out all pixels in each field in order to obtain a high-resolution image.

It is an object of the present invention to provide a solid-state imaging device that meets such demands and eliminates the above-mentioned disadvantages.

[Means for solving problems]

The solid-state imaging device according to the present invention includes a light receiving element (2) (2)...(2) and a light receiving element (2) (21...(2)) as shown in FIGS. 1 to 3, for example. Vertical register (9) that vertically transfers signal charges accumulated in
...(9) and this vertical register (Q) (9)...
- A plurality of horizontal registers α and αυ that horizontally transfer signal charges transferred by (9), and an output section (b) that detects signal charges transferred by these plural horizontal registers 01011 (2) The vertical registers (91(9)...(9) correspond to one bit of the vertical registers (91(Q)...(9)) to one light receiving element (2), and The horizontal register QIQυ simultaneously outputs the signal charges of multiple horizontal lines to multiple output sections (b)Q.
'It was designed to be forwarded to J.

(Function) In the present invention, the vertical register +9) +9)・
...(9) is vertical register 1 for l light receiving element (2).
91 +91... (9) 1 bit is made to correspond, and multiple horizontal registers 01 (1 ml) are provided so that the signal charges of multiple horizontal lines can be read out simultaneously, so all pixels can be read out. Therefore, high resolution images can be obtained.

In addition, in the present invention, a plurality of horizontal registers αΦ■ are provided so that the signal charges of a plurality of horizontal lines can be read out simultaneously, so a color filter array as shown in FIG. 4, for example, is used. When applied to a single-chip color camera, the color signals of multiple horizontal lines are output simultaneously. Therefore, unlike when using the solid-state imaging device shown in FIG. 12, there is no need to provide a one-horizontal period delay circuit to synchronize the signals of multiple horizontal lines, and the signal processing circuit is simplified accordingly. .

〔Example〕

Hereinafter, an embodiment of the solid-state imaging device according to the present invention will be described with reference to FIGS. 1 to 8. In this example,
An interline transfer type solid-state imaging device will be described in which the vertical register has a three-phase electrode structure and the signal charges of two horizontal lines can be read out simultaneously. In FIGS. 1 to 3, parts corresponding to those in FIG. 13 are given the same reference numerals.

In this example, as shown in FIG.
A light receiving element (2) consisting of a photodiode is placed on the surface side of 11.
A light receiving section (3) is provided in which, for example, 492 (vertical) x 510 (horizontal) pieces of (2) are arranged in a matrix,
A subject image is formed on the surface of this light receiving section (3), and a signal charge corresponding to the brightness of this subject image is transferred to each light receiving element (2)...
・Let it accumulate in (2). In this case, the light receiving part (3
) A color filter array 04J shown in FIG. 4 is arranged on the surface,
Each color filter of this color filter array (2) is made to correspond to each light receiving element (2)...(2), and a signal charge based on the colored light passing through each filter is transmitted to each light receiving element (2).
(2)...Let it accumulate in (2). This color filter array (goods) has G
, B, G, . . . B color filters are arranged, and the second horizontal line Ll+ the fourth horizontal line L8゜...492nd
The so-called G stripe R/ is constructed by arranging color filters of G, R, G, .
The B-line sequential system will be used.

In addition, light receiving elements (2) (21.
...(2) Vertical register 19 consisting of CCO for each column
1 (9)...(9) are provided, and the light receiving element (2+ +2
1...(2) The signal charges accumulated in the area can be transferred in the vertical direction, that is, downward in the plane of the paper. In this case, this vertical register (9) (9)...(9) has a three-phase electrode structure, and the three-phase drive pulse φ shown in FIGS. 5A to 5C
The structure is such that it can be driven by 1, φv, and φV, and one bit corresponds to one light-receiving element. Specifically, these vertical registers (9) (9)...
(9) is a light receiving element (2) as shown in Figures 2 and 3.
12)...these light receiving elements 12) for each column of (2)
+2)...The charge transfer region consisting of an N-type region extending in a strip shape in the vertical direction adjacent to (2) is read out through the gate region QIQ...(to) and drive pulse φ is applied to these charge transfer regions a-〇訃...(to)
Transfer electrode (1) made of polycrystalline silicon to which V2 is supplied
7a*) (17As)...(17A,) and a transfer electrode (17A+) made of polycrystalline silicon to which driving pulse φ11 is supplied (17A+) (17^,)...(17A+) are each connected to an insulating layer made of S10°. Transfer electrodes made of polycrystalline silicon (17^寥) (
17A*)...(17At). In this case, the transfer electrode to which the drive pulse φv3 is supplied (17^2> (17^,)... (17^,) is the light receiving element +2 that constitutes each horizontal line) 12)...
(2) Located below (bottom of the paper), the charge transfer area 090
9...The part above α9 should be a wide part that protrudes upward (upwards of the page). In addition, the transfer electrodes (17^1) (17^l)... (17AI
) is a light receiving element (21 (21...) constituting each horizontal line.
・Arranged above (2) (above the page), the charge transfer area α9
09...09 Make sure that the upper part becomes a wide part that protrudes downward (downward in the paper), and connect the transfer electrode (17A, ) (17A
, )...(17Ai).
Transfer electrode through camphor (17A,) (17A,)...
A part of the wide part of (17A,) is overlapped. Also, on the plane, the transfer electrode (17^s) (17A3)...
(17^3) wide part and transfer electrode (17A,) (17
A, )...(17^1) A gap should be provided between the wide part and the wide part. Then, the charge transfer area (1909.0
9) Upper transfer electrode (17AI) (1783) ・
(17Aa) wide part and transfer electrode (17A,) (1
7^1)... Polycrystalline silicon layer (178g) (178m)...(
17B, ) is formed, and this polycrystalline silicon layer (17B) (17Bl)...(17B) is formed as a transfer electrode (17
^s) (17^,)...(17^,) wide part and transfer electrode (17A+) (17A+)...(17A,)
A transfer electrode (17At) that supplies a drive pulse φv8 to a portion facing the charge transfer region @(2)...(to) via an insulating layer α in a gap with a wide portion of the transfer electrode (17At)
-(17At). In this case, the width of this gap is the readout gate DI area Ql (to)...O provided adjacent to the left side of the light receiving element (2) +21...(2).
The width of the transfer electrode (17
AI) (17At)...(17^m) is arranged so that its right side part covers the readout gate region Ql01...a19 and the left end part of the light receiving element (21(21...(2)). This transfer electrode (17ai) (17Al)
By supplying the readout pulse P7 having the voltage value VT shown in FIG. 5B to (17^8), the signal charges accumulated in all the light receiving elements (2) (21...(2) are All transfer electrodes (17A,) (17＾g)
...(17At) Lower charge transfer region 0909-...α
so that they can be read out at the same time. That is, the transfer electrodes (17A, ) (17^rich) and (17As) constitute one pin point of the vertical register (9).

In addition, a first horizontal register α made of a CCD is provided on the output side of the vertical register (91 (91...(9)), and a second horizontal register αD made of the same < ccn is provided via the gate part α. .This first horizontal register α [
As shown in Fig. 2, the N-type region (■) extending in the horizontal direction is provided so as to be in contact with the charge transfer region α of the vertical register section +9) (91...(9)) and α9...α. This N-type region (2) is used as a charge transfer region, and transfer electrodes (21S+) (21T+) (215T) (21S+) (21T+) (215T) (21T+) made of polycrystalline silicon are placed on this charge transfer region (21) via an insulating layer.
(21S+) (21T+) are provided, and the transfer electrodes (215,) (21Tl) and (213g)
(21T,) are the two-phase drive pulses φ□ and φ shown in FIG. 5 and FIG. 5F, respectively. vertical register +91
(9)...The signal charges transferred from (9) can be transferred in the horizontal direction, that is, toward the left side of the page.

In this case, the transfer electrode (2151) (213 rich) and the charge transfer region (2O5+) (205t) below this transfer electrode (2131) (213m) are respectively made into a so-called storage electrode and a storage region, and the transfer electrode (
21T+) (21Tl) and this transfer electrode (21T+)
) (21Tg) lower electrode transfer area (20T+) (
207*) to form a so-called transfer electrode and a transfer region, respectively. That is, in this example, the impurity concentration of the charge transfer region (2051) (205g) below the transfer electrode (21St) (21S rich) is
21Tl) (21Tx) lower charge transfer region (20Tl) (21Tx)
↑+) (20Tt) so that the impurity concentration is higher than that of the transfer electrode (21S+) and (21Tt) during signal charge transfer.
h) lower charge transfer region (203I) and (203,
) is made deeper than the potential level of the charge transfer regions (20T, ) and (20T) below the transfer electrodes (21T, ) and (21Tg), respectively.

Further, the second horizontal register αυ is the first horizontal register O
A charge transfer region (22) consisting of an N-type region is provided parallel to the charge transfer region (to) of I, and this charge transfer region (22) is provided.
22) Transfer electrode (23Sl) (23
T, ) (23Sl) (23ft)...(23S,)
(23Tl), transfer electrodes (2351') (23T l ) and (233m) (
By supplying the two-phase drive pulses φI and φ■ shown in FIG. 5 and FIG. In other words, the image can be transferred toward the left side of the page. In this case, this second horizontal register OD
Transfer electrode (23S,) (23T,) (2ast)
(23Tl) are the first horizontal register 01 (7) transfer electrode (21S+) (21T+) (213t) (2
1h) and the transfer electrode (23s+
) (23sg) and (23T ,') (23T ton)
serve as a storage electrode and a transfer electrode, respectively. That is, the charge transfer region (22S+) (22S rich) below the transfer electrode (235+) (233i) is used as a storage region, and the transfer electrode (21Tl) (21T
l) Lower charge transfer region (22T, ) (227t)
to form the transfer area.

Also, the first horizontal register Ql and the second horizontal register αD
The gate section (2) provided between the vertical register +
91 (91...(9) charge transfer region α9(19.
... Storage area of the first horizontal register OI connected to a9 (20S1) (20g, )... (20S
) and this storage area (20SI) (2O3+)・
...second horizontal register α half a bit before (203,)
Storage area of D (22S,) (22S,) ---
(225t) and N-type region (24) (24)...(
24), and this N-type region (24) (24)...
・(24) is the gate region, and this gate region (
24) (24)...Regions other than (24) are channel stop regions (2) formed by diffusing P-type impurities.
5) (25)...(25) and an insulating layer on these N-type regions (24) (24)...(24) and channel stop regions (25) (25)...(25) A gate electrode (2s
This gate electrode (26
) is supplied with the gate pulse φG shown in Figure 5 to transfer the signal charge from the first horizontal register a [to the second horizontal register α].
Make it possible to transfer to υ.

Also, the first horizontal register 01 and the second horizontal register Q
Floating diffusion/diffusion on the output side of D.
A first output section @ and a second output section (to) consisting of an amplifier are provided, and from these first output section @ and second output section a1, a first output terminal (27) and a second output terminal (27) are respectively provided. Derive the output terminal (28>).

Next, the operation of the solid-state imaging device of this example will be explained with reference to FIGS. 5 to 8.

In the solid-state imaging device of this example, the light receiving element (21 (21
... e) are read out during the vertical blanking period, and then transferred toward the first and second horizontal registers 01 and Qll using the horizontal blanking period. Here, Figure 6 shows Vl- in Figure 2.
By indicating the potential level of the substrate surface area along the Vl'' line with a solid line (29), the signal charge Ql-1 accumulated in the light receiving element (2) at the left end of the first horizontal line L1 during the first field and the The signal charge ag-1 accumulated in the leftmost light receiving element (2) of the second horizontal line L8 is read out to the charge transfer area (5) of the vertical register (9) and transferred to the second and first horizontal registers, respectively. Figure 6A shows how it is transferred towards αD and Ql.
is a predetermined time point L+ of the vertical blanking period shown in FIG.
A read pulse P is supplied to the transfer electrode (17A*), and the signal charges Ql-1 and Ql-1 are respectively transferred to the vertical register (
9) of the first bit (the bit corresponding to the light receiving element (2) of the first horizontal line) and the charge transfer area α9 below the transfer electrode (17A) and the second bit (the bit corresponding to the light receiving element (2) of the second horizontal line). ) corresponding to the bit) portion of the transfer electrode (17A
, ) is shown in the lower charge transfer region α, and then these signal charges Q1-8 and Qffi-1 are read out.
are transferred to the second horizontal register αD and the first horizontal register O1, respectively. Hereinafter, the transfer of the signal charge Ql-1 will be explained first.

After time t1, at time t, the voltage of about 17A changes from the read pulse voltage V! to the normal high level voltage VN.
Then, during the horizontal blanking period, time t,
Since the voltage of the transfer electrode (17As) changes from the low level voltage V to the high level voltage V, the potential state of the charge transfer region a changes from the state shown in FIG. 6B to the state shown in FIG. 6C. Therefore, the signal charge Q1-1 is transferred to the storage region (20
s I) and stored therein.

Next, at time t9, the voltage of the transfer electrode (17^m) is changed from high level voltage VN to low level voltage VL, and then at time 1. The voltage of the transfer electrode (17^,) is high level voltage v
, l to the low level voltage VL, and the gate part a
The voltage of the gate electrode (26) of ll is the low level voltage vL
Since the high level voltage vIl# is generated from #, the potential state changes from the state shown in Fig. 6 to the state shown in Fig. 6F, and the signal charge Ql-1 is transferred to the first horizontal register α [
The data is stored across the storage area (20S, ) of the gate area (20S, ) and the gate area (24) of the gate section α-.

Next, at time t7, the storage electrode (21S,) of the first horizontal resistor Ql is changed from the high level voltage v,4' to the low level voltage V%, and then at time t-, the storage electrode (21S,) of the second horizontal resistor αD (23S,) is changed from the low level voltage VLl to the high level voltage v,1', and then at time t, the gate electrode (26) of the gate component changes from the high level voltage vII# to the low level voltage vL#. Therefore, the signal charge Q,-1 is accumulated in the gate region (24) of the gate portion α at time t, as shown in FIG. 6G, and then at time t, as shown in FIG. 6H. It is stored across the gate area (24) of the gate section 01 and the storage area (22S, ) of the second horizontal register Ql, and then the second horizontal storage area is stored as shown in FIG. It is accumulated in the storage area (22s,) of register +Ill, and this state is maintained from then on until the horizontal valid period.

In this way, the light receiving element (2) at the left end of the first horizontal line L
) is transferred to the second horizontal register QD.

Next, the transfer of the signal charge am-t accumulated in the leftmost light receiving element (2) of the second horizontal line Lx will be explained.

This signal charge Q, -1 is stored in the vertical register (9) at time t1.
The second bit of the transfer electrode (17A) is read out to the charge transfer region (to) below the transfer electrode (17A,).
17A,) is changed from the read pulse voltage Vt to the normal high level voltage VN, then at time t, the voltage at the transfer electrode (17A3) is changed from the low level voltage vL to the high level voltage VN, and then at time t4. transfer electrode (ITA)
t) voltage changes from high level voltage VN to low level voltage V
L, followed by time 1. At time t, the voltage of the transfer electrode (17A,) is changed from the low level voltage VL to the high level voltage vll, and then at time t, the voltage of the transfer electrode (17^3) is changed from the low level voltage vL to the high level voltage VN, Subsequently, at time t, the voltage of the transfer electrode (17AI) is changed from low level voltage Vt to high level voltage VM, and then at time t
, the voltage of the transfer electrode (ITA,) is high level voltage VM
Since the low level voltage vL is set from , the potential state changes to the state shown in FIG. 6H after passing through the states shown in FIGS. 6B to 6G, and the signal charge Ql-1 becomes as shown in FIG. 6H. 0 transferred to the electrode transfer area a9 below the transfer electrode (17A,) of the first bit at time t9.
, ) changes from the low level voltage Vt to the high level voltage V
N, the signal charge Qt is the 6th signal charge at this time t.
figure! As shown in , the data is transferred to the storage area (20S, ) of the first horizontal register Qll.

Next, at time t1°, the voltage of the transfer electrode (17^g) is changed from the high level voltage VN to the low level voltage VL, and then at time t1g, the voltage of the transfer electrode (17^,) is changed from the high level voltage V% to the low level voltage VL. level voltage ν, and then at time t
1 and the storage electrode of the first horizontal register a (21s
, ) is changed from the high level voltage V,' to the low level voltage vL', so the potential state is as shown in Fig. 6J.
, the state shown in FIG. 6L (FIG. 7A) is reached, and the state shown in FIG. 6N (FIG. 7B) is reached. ) to the storage area (2
0Sm). In addition, in this Figure 6, os-
1 indicates the signal charge accumulated in the leftmost light receiving element (2) of the third horizontal line L, and Q9-1 indicates the signal charge accumulated in the leftmost light receiving element (2) of the third horizontal line L.
It shows the signal charges accumulated in the leftmost light receiving element (2).

In the solid-state image device of this example, all the light receiving elements (21 (21...(2
) and all the light receiving elements (21 (21-...) of the first horizontal line L1 are stored in the storage area (2OS, ) of the first horizontal register a, respectively. (20S,)...(203g) and the second
Storage area (223g) of horizontal register αD (
22Sg)...(22st), but after that, when the horizontal effective period comes at time t's, the fifth figure and the second horizontal register On are stored in the first horizontal register Q1 and the second horizontal register On. High-speed two-phase drive pulses φ1 and φ shown in H
(2) is supplied, the signal charges of the second horizontal line L□ accumulated in the first horizontal register Ql and the signal charges of the first horizontal line L accumulated in the second horizontal register QO are and the second output section (2). In this example, since a color filter array (2) as shown in FIG. 4 is provided, the first output terminal (2)
7), as shown in FIG. 8A, G of the second horizontal line Lx,
I? , G, . . . R color signals are obtained, and the second output terminal (28) receives the G, B, G, . . . B color signals of the first horizontal line L, as shown in FIG. 8B. After the color signal is obtained, the first output terminal (27) receives the G, R, G of the fourth horizontal line L.
,... R color signal,... 492nd horizontal line L4,
2 G, R, G, . . . R color signals are obtained, and the second
The output terminal (28) of the color signal of the third horizontal line Ls,
...G, B, G of the 491st horizontal line L9,1...
-B color signal can be obtained.

Also, in the second field, the first output terminal (2
7), as shown in FIG. 8C, G of the second horizontal line L8,
R, G, . . . R color signal, G of the fourth horizontal line L.

R, G, . . . R color signals 1. ...G of the 492nd horizontal line Lelt.

R, G, . . . R color signals are obtained, and the second output terminal (28) receives the first horizontal line L as shown in the eighth diagram.
.

G, B, G, . . . B color signals, third horizontal line L,
G, B.

G,...B color signal,...491st horizontal line Lv
+G, Il.

G, . . . B color signals are obtained.

In this way, in the solid-state imaging device of this example, the vertical registers (9) 191...(9) have a three-phase electrode structure, and one bit corresponds to one light receiving element. +9) ... A first horizontal register Ql and a second horizontal register (Ill) are provided on the output side of (9), and one signal of two horizontal lines is read out simultaneously, so that one field It is possible to read out all pixels at once.

Therefore, according to the solid-state imaging device of this example, a high-resolution image can be obtained. Incidentally, in this example, we have described a case in which a solid-state imaging device is configured with a G stripe R/B line sequential system with 510 horizontal pixels, but when performing all pixel readout as in this example, horizontal pixels It is possible to obtain a diagonal resolution equivalent to that of a solid-state imaging device with 760 G, R, and B stripes.

As described above, in the solid-state imaging device of this example, the first horizontal register α and the second horizontal register αD are provided, and color signals of two adjacent horizontal lines, that is, G and R of the second horizontal line L, are provided. , G,...R color signals and G of the first line L,
, B, G, . . . color signal of B, G of fourth horizontal line L#
.

B, G, . . . color signals of B and G of the third horizontal line L,
,B,G.

...B color signal, ...492nd horizontal line Lees
G, R, G.

・-R color signal and G of the 491st horizontal line L9,1,
B, G.

... Since the B color signals can be obtained sequentially and simultaneously at the first output terminal (27) and the second output terminal (28), the solid-state imaging device of this example can be used. In the single-panel color camera used, the 2
R, G, and B signals can be obtained by performing predetermined sampling on the color signals of two horizontal lines.
, G, and B signals to a predetermined encoder, a decoded color signal can be obtained.

Therefore, in a single-chip color camera using the solid-state imaging device of this example, a one-horizontal period delay circuit is provided as in the case of using the conventional solid-state imaging device shown in FIG. There is no need to synchronize the signals, so
There is an advantage that the signal processing circuit can be simplified.

In the above embodiment, as shown in FIGS. 2 and 3, a polycrystalline silicon layer (178g) (17B*) is formed in a vertical direction above the charge transfer region Q9α...+19.
...(17B,) is formed, and this polycrystalline silicon layer (
17B proverb) (178m)...(178g) is the transfer electrode (17A3) (17As) ・The wide part of (17^S) and the transfer electrode d7^1) (17AI)...(17A
A transfer electrode (17AI) that supplies a drive pulse φ□ to the part facing Q9 between the charge transfer region (to) α through the insulating layer α- between the wide part of the charge transfer electrode (17AI) (17＾3)
...(17^8), but instead, as shown in Figs. 9 and 10, the transfer electrode (17^m) (17^ proverb)... Transfer (17＾mushroom) to electrode (17As) (17＾,)...(17＾,
) wide part and transfer electrode (17^,) (17^1)...
These transfer electrodes (17AI) (17At)... (17^
8) may be connected to the aluminum wiring layer (31) through the contact hole (30) in the insulating layer α. In this case, in addition to obtaining the same effect as described above, the transfer electrode (17＾wealth) transfer electrode (17ﾾri and (
17A,) can be reduced,
The propagation distortion of the drive pulse φv8 can be improved.

In this case, as shown in Fig. 11, the transfer electrode (17^
g) and (17Ax), a polycrystalline silicon layer (32) is provided in the shape of a principe, and the transfer electrode (17^Snow) and (17A
x) may be connected.

Furthermore, in the above embodiment, a case has been described in which the so-called G stripe R/B line sequential color filter array 04) shown in FIG. In addition, various other color filter arrays can be used, and it can also be applied to a two-panel color camera and a three-panel color camera.

Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

(Effects of the Invention) According to the present invention, since all pixels can be read out, there is an advantage that a high-resolution image, particularly an image with improved diagonal resolution, can be obtained.

Furthermore, according to the present invention, when applied to a single-chip color camera using a single-chip color filter array, the color signals of multiple lines are output in a synchronized manner. In this case, unlike when using the solid-state imaging device shown in Fig. 12, there is no need to provide a one-horizontal period delay circuit to synchronize the color signals of multiple horizontal lines, and the signal processing circuit is simplified accordingly. There is a benefit of being

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a schematic configuration of an embodiment of a solid-state imaging device according to the present invention, FIG. 2 is a plan view showing main parts of the example shown in FIG. 1, and FIG. 4 is a line diagram showing the color filter array used in the example in FIG. 1, FIG. 5 is a waveform diagram for explaining the example in FIG.
Figure 7 is a diagram showing the potential state of the substrate surface along the line 1-Vl' in Figure 2. Figure 8 is a diagram showing the potential state of the substrate surface along the line ■-■' in Figure 2. FIG. 9 is a diagram showing the color signals obtained at the first output terminal (27) and the second output terminal (28) in the example shown in FIG. 1O is a sectional view taken along the line X-X' in FIG. 9, FIG. 11 is a plan view showing the main parts of still another embodiment of the present invention, and FIG. 12 is a schematic configuration of a conventional solid-state imaging device. A plan view, FIG. 13 is a diagram showing the color filter array used in the example in FIG. 12, FIG. 14 is a diagram showing the color signal obtained at the output terminal (8) in the example in FIG. 12, and FIG. The figure is a diagram for explaining the example in FIG. 12. (1) is a P-type silicon substrate, (2) is a light receiving element, (3)
is the light receiving section, (9) is the vertical register, (to) is the first horizontal register, αD is the second horizontal register, (2) is the first output section, 0 is the second output section, (17^ 1) (17A,
) and (17^,) are the transfer electrodes of the husband-husband vertical register,
(2) is a gate section.

Claims (1)

[Scope of Claims] A light receiving element, a vertical register that vertically transfers signal charges accumulated in the light receiving element, and a plurality of horizontal registers that horizontally transfers the signal charges transferred by the vertical registers. and a plurality of output parts for detecting the signal charges transferred by the plurality of horizontal registers, and the vertical register corresponds one bit of the vertical register to one light receiving element, and the plurality of output parts detect the signal charges transferred by the plurality of horizontal registers. 1. A solid-state imaging device, characterized in that the horizontal register is configured to simultaneously transfer signal charges of a plurality of horizontal lines to the plurality of output sections.