JPS63266874A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To reduce the generation of blooming by installing a capacitive device where one electrode is connected to a semiconductor region in a photoelectric converter of a vertical switch MOS for a solid-state image sensor and the other electrode is connected to a gate electrode of this vertical switch MOS. CONSTITUTION:A capacitive device PC is installed in such a way that one electrode is connected to semiconductor regions N<+> of a photoelectric converter for a solid-state image sensor and that the other electrode is connected to a gate electrode of a vertical switch MOS. When the photoelectric converter is irradiated with the light, the information is stored therein. Then, if a reset signal line RP is selected during a horizontal retrace period, it is made possible to prevent one part of surplus photoelectrons from leaking to output signal lines HS when the strong light enters. If vertical scanning lines VL are selected in order to read out the information, an increase in a potential of the vertical scanning lines VL increases the potential of the photoelectric converter due to a coupling action of the capacitive device PC; accordingly, it is made possible to keep the photoelectric converter in a momentary unsaturated state; the surplus photoelectrons do not leak to the output signal lines HS; thereby it is made possible to reduce the blooming.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device, and particularly to a technique that is effective when applied to a horizontal readout type MOS solid-state imaging device.

[Conventional technology]

Horizontal readout (TSL: 7ransvcrsa)
A MOS type solid-state imaging device of the Sjgna]l,jnc) type is known. The solid-state image sensor in the light receiving section of this solid-state image sensor is a horizontal switch MOS field effect transistor (
It is constructed by connecting in series a MOS (hereinafter referred to as MOS), a vertical switch MOS, and a photoelectric conversion element (photodiode element).

The horizontal switch MOS is controlled by a horizontal scanning shift register section (horizontal scanning circuit) with a horizontal scanning line extending in the column direction interposed therebetween. The vertical switch MOS has a vertical scanning line extending in the row direction intersecting the horizontal scanning line and an interlace scanning control section, and a vertical scanning shift register section (
vertical scanning circuit). In order to prevent field afterimages, this TSL type solid-state imaging device reads information from the solid-state imaging device by performing simultaneous two-row scanning and interlace scanning by an interlace scanning control section.

An output signal line extending in the same row direction as the vertical scanning line is connected to the drain region of the horizontal switch MOS. The output signal line is connected to each of the output circuit (readout circuit) and the horizontal retrace period reset section. The horizontal retrace period reset section is configured to reset false signals accumulated in the output signal line during the horizontal retrace period. Further, the output signal line is reset at high speed every time the photodiode is read out during the horizontal scanning period. In other words, this TSL type solid-state imaging device has the feature of being able to reduce smear and obtain high image quality.

On the other hand, conventionally, the horizontal switch M that is commonly provided in each column
Instead of the OS, as described above, the TSL type solid-state imaging device provides a horizontal switch MOS, which is smaller than the OS, for each cell (pixel). This solid-state imaging device has a feature that it can reduce fixed noise caused by variations in spike noise that occur during switching of the horizontal switches M and O8.

For TSL type solid-state imaging devices, for example,
Video information (LL May 1986 issue, p19-p24
It is described in.

[Problem that the invention seeks to solve]

In the TSL type solid-state imaging device, the photoelectric conversion element of the solid-state imaging element of the light receiving section is formed by a PN junction formed by one N1 type semiconductor region of a vertical switch MOS and a P type semiconductor region in which it is provided. It consists of This photoelectric conversion element becomes saturated when the platform receives strong light, and when the photoelectric conversion element reaches the saturated state, it stops accumulating photoelectrons (signals) and becomes unable to accumulate excessive photoelectrons. A part of these excess photoelectrons leaks to the output signal line beyond the vertical switch MOS and horizontal switch MOS, causing blooming.

In the conventional TSL type solid-state imaging device, there is a problem in that the photoelectric conversion element tends to be saturated (the blooming margin is small), and the above-mentioned blooming occurs frequently.

An object of the present invention is to provide a TSL type solid-state imaging device.
The object of the present invention is to provide a technology that can reduce blooming.

Another object of the present invention is to provide a TSL type solid-state imaging device, at least when the solid-state imaging device is operating a signal continuously.
The object of the present invention is to provide a technology that can reduce blooming.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

41 A brief summary of typical inventions disclosed in this application is as follows.

In a TSL type solid-state imaging device, a capacitive element is provided in which one electrode is connected to the semiconductor region on the photoelectric conversion element side of a vertical switch MOS of the solid-state imaging device, and the other electrode is connected to the gate electrode of the vertical switch MOS. .

The capacitive element is composed of a plurality of vertical switch MOSs having a common gate electrode and connected in series.

Further, the capacitive element is configured by extending a part of a vertical scanning line connected to the gate electrode of the vertical switch MOS above the photoelectric conversion element.

[Effect]

According to the above-mentioned means, when the gate electrode of the vertical switch MOS is selected, the photoelectric conversion element can be brought into a non-saturated state by the coupling action of the capacitive element by this selection signal, so that this non-saturated state Blooming can be reduced by reading information from the solid-state image sensor at this time.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a TSL type MOS type solid-state imaging device.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔Example〕

(Embodiment 2) A TSL type solid-state imaging device which is Embodiment I of the present invention is shown in FIG. 1 (schematic configuration diagram) and FIG. 2 (equivalent circuit diagram).

As shown in FIG. 1, the TSL type solid-state imaging device (solid-state imaging chip) CHI includes a photodiode array ARR in which a plurality of cells (pixels) are arranged in rows and columns in the center.

The first diode array ARR is composed of a light receiving section SA and an optical black section OB.

The light receiving section SA is configured to convert an optical signal incident through an optical lens into an electric charge and store the electric charge. The optical black section OB is configured to form a reference value (optical black level) in order to correct noise due to dark current components.

Around the right side of the photodiode array ARR, there is a horizontal retrace period reset section RES and an interlace scan control section I.
NT, vertical scanning shift register section (vertical scanning circuit)
Vreg is provided. A horizontal scanning shift register section (water scanning circuit) Hreg is provided around the lower side, and an output circuit (continuation circuit) OUT is provided on the left side.

As shown in FIG. 2, the photodiode array AR
R light receiving section SA, vertical scanning lines VLI, VL2 . ...,
Horizontal scanning lines HLI, HL2. ..., output signal line H8I
, H82, . . . The vertical scanning lines VL extend in the row direction, and a plurality of vertical scanning lines VL are arranged in the column direction. The water NIL scanning lines 1-IL extend in the column direction and are arranged in plural in the row direction. Output signal line I-
IS extends in the same row direction as the vertical scanning line VL,
Multiple pieces are arranged in the row direction.

The pixel includes a horizontal switch MOSQh and a vertical switch M
It is composed of an OSQv (Qvl, Qv2) and a photoelectric conversion element (photodiode) PD (PDI, PD2).

One semiconductor region of the horizontal switch MOSQh and the other semiconductor region of the vertical switch MOSQv are connected, and both are connected in series. Photoelectric conversion element PD
I is connected to the other semiconductor region of the vertical switch MOS Qvl, and the photoelectric conversion element PD2 is connected to the other semiconductor region of the vertical switch MOS Qvl.
It is connected to one semiconductor region of QV2.

The gate electrodes of the horizontal switches MOSQh of the plurality of solid-state image sensors arranged in the column direction are connected to one horizontal scanning line HL. The horizontal scanning line HL is connected to a horizontal scanning shift register section Hreg. The horizontal scanning shift register unit Hreg is configured to sequentially scan a plurality of horizontal scanning lines HL arranged in the row direction and select pixels in the row direction using the input signal Hin and the clock signal φhitφh2.

Vertical switch MOSQ of multiple pixels arranged in row direction
The gate electrodes of v (each of Qvl and Qv2) are connected to one vertical scanning line VL. One end of the vertical scanning line VL is connected to a vertical scanning shift register section Vreg with an interlaced scanning control section INT interposed therebetween. The vertical scanning shift register section Vreg receives an input signal V j
n and a clock signal φVllφv2, the selection signal 1, R2, . ing.

The interlaced scan control unit INT switches the switch M, OS Q Fe or Q by the selection signal Fe or Fo for the field 1
Driving MOS that controls F o and transmits selection signal R
It is configured to select Qd. Drive MOSQ
d gate electrode and one semiconductor region (vertical scanning line VL)
A boost capacitor is provided between the two. The other semiconductor region of the drive MOSQd receives a vertical scanning signal φ3.
Or φ4 is applied. In other words, vertical scanning signal φ3
Alternatively, φ4 is applied to the vertical scanning line VL by the driving MOS Qd based on the selection signal R. Drive MOSQd
is the vertical scanning signal φ or φ without causing a voltage drop corresponding to the threshold voltage due to the boost capacitor. can be applied to the vertical scanning line VL.

This interlaced scanning control unit INT is configured to be able to perform two-fold sequential scanning and interlaced scanning. That is, first, the interlaced scanning control unit INT selects two adjacent vertical scanning lines VL (for example, VLI, VL2, V
L3 and VL4). Next, the interlaced scan control unit INT selects 1 by using another field selection signal F.
Two vertical scanning lines V of even field B shifted by a line □
L (e.g. VL2 and VL '3, VL4 and VL5)
is configured to select.

The other end of the vertical scanning line VL is connected to the gate electrode of the output control MOS QSye, QScyyQsw*Qsg of the output circuit OUT. The output control MOS QS connects one end of the output signal line H8 and the output line S for each color of the output circuit OUT.
It is configured to connect Ye, SCy, SW, and SG.

The output signal line HS is connected to the other semiconductor region (drain region) of the horizontal switch MOSQh of the plurality of solid-state image sensors arranged in the row direction. The other end of the output signal line HS is the reset MO of the horizontal retrace period reset section RES.
It is connected to the reset output line Vr with SQr interposed therebetween. The gate electrode of the reset MOS Qr is connected to and controlled by the reset signal line RP. The horizontal retrace period reset unit RES is configured to reset false signals accumulated during the horizontal scanning period.

Next, a specific device structure of the TSL type solid-state image sensor CHI will be explained using FIGS. 3 to 6. FIG. 3 is a plan view of the main part showing the solid-state image sensor of the light receiving section SA, and FIG. 4 is a plan view of the main part showing the solid-state image sensor of the optical black part OB. Figure 5 shows ■-■ in Figure 3.
The cross-sectional view taken along the cutting line, FIG. 6, is VI-VI in FIG. 3.
It is a sectional view taken along a cutting line.

As shown in FIGS. 3 to 6, the pixels of the light receiving section SA and the optical black section OB basically have the same structure.

Each of the solid-state image sensors of the light receiving section SA and the optical black section OB is located in a well region W provided in the semiconductor substrate SUB.
It is formed on the main surface of the ELL, and its periphery is defined by the element isolation insulating film LOG.

The semiconductor substrate SUB is made of N-type single crystal silicon. The well region WELL is of P type and mainly forms an N channel M O' 5FET. Note that if the well region WELL is not provided, P
A type semiconductor substrate SUB is used.

The element isolation insulating film LOG is made of a silicon oxide film formed by selectively thermally oxidizing the main surface of the well region WELL. The element isolation insulating film LOC is shown in Figures 3 and 4.
As shown in the figure, the pixel forming area is configured in a U-shape. More specifically, the inter-element isolation □ insulating film LOG is configured in a U-shape so that the area of the horizontal switch MOSQ region is small and the area of the vertical switch MOSQv region is large.

The horizontal switch MOSQh of the pixel is shown in FIGS. 3 to 6,
As shown in FIG. 7 (a plan view of main parts in a predetermined manufacturing process), mainly the well region WELL, the gate insulating film,
It is composed of a pair of N+ type semiconductor regions (N') which are gate electrodes, source regions, or drain regions.

The gate insulating film is, for example, a silicon oxide film formed by oxidizing the main surface of the well region WELL region.
It is formed with a film thickness of about 500 [people].

The gate electrode is formed of a gate electrode material such as polycrystalline silicon film (semiconductor film) P-8i. Polycrystalline silicon film P
-8i is 1, for example, formed with a film thickness of about 3000 to 4000 [people]. In addition, the gate electrode is made of high melting point gold@(M
It may also be formed of a film of Ti, Ta, W), a high melting point metal silicide (MOSi2.TiSi2.TaSi, 1WSi2) film, or a polycrystalline silicon film and a composite film thereof.

The semiconductor region N' is formed by introducing N-type impurities into the main surface of the well region WELL by ion implantation using the gate electrode as a mask, and by stretching and diffusing the impurities.

The semiconductor region N+, which is the drain region of the horizontal switch MOSQh, is formed on the main surface of a P' type semiconductor region (P') having a higher impurity concentration than the well region WELL. The semiconductor region P1 is diffused to the channel forming region of the horizontal switch MOSQh.

This semiconductor region P+ is configured to increase the threshold voltage of the horizontal switch MOSQh.

In other words, the semiconductor region P'' is configured to reduce the movement of electrons that cause blooming from the photoelectric conversion element FD side to the output signal line HS.

Vertical switch MOSQvl is horizontal switch MOSQh
Substantially the same as above, it is mainly composed of a pair of semiconductor regions N' which are a well region WELL, a gate insulating film, a gate electrode, and a source region or a drain region.

-7- Vertical switch M OS Q v 2 is horizontal switch M
Substantially similar to OSQh, mainly the well region WELL
, a gate insulator, a gate electrode, and a pair of semiconductor regions N' that are a source region or a drain region.

The gate electrodes of the vertical switches MOSQvl and Qv2 are formed in the same manufacturing process as the gate electrode of the horizontal switch MOSQh. vertical switch MOSQvl,
The respective gate electrodes of Q v 2 extend across the center of the photodiode formation region (or light receiving section) in the row direction, and are integrally (commonly) configured. Further, each gate electrode of the vertical switches M OS Q v 1 and Qv2 is configured integrally with a vertical scanning line VL extending in the row direction. That is, the vertical scanning line VL is configured to extend substantially in the upper center of the solid-state image sensor in the row direction. In reality, the vertical scanning line VL is located above the photoelectric conversion element PD, specifically between the photoelectric conversion element PDI and the photoelectric conversion element PD2 (near each of the photoelectric conversion elements PDI and PD2 in the solid-state image sensor). 1G-side).

One semiconductor region N′ of the vertical switch MOS Q v 1 is the same as one semiconductor region N of the horizontal switch MOS Qh.
It is integrally configured (shared) with ゛. Vertical switch M
The other semiconductor region N+ of the OS Q v 1 is integrally configured (shared) with the other semiconductor region N+ of the vertical switch MOS Q v 2. That is, vertical switch M
The OS Q v 1 and Q v 2 share a common gate electrode and are connected in series.

The photoelectric conversion element PDI is constituted by a PN junction between the other semiconductor region N+ of the switch MOSQvl or the other semiconductor region N' of the vertical switch MOSQv2 and the well region WELL. The photoelectric conversion element PD2 is a vertical switch M
One semiconductor region and well region W of OS Q v 2
It consists of a PN junction with ELL.

As shown in detail in FIG. 8 (a plan view of main parts in a predetermined manufacturing process), the horizontal scanning line HL is formed between the solid-state image sensor formation regions (element isolation insulating film LOG) arranged in the row direction. It is configured to extend in the column direction. The horizontal scanning line HL is composed of a conductive layer above the polycrystalline silicon film P-8i, for example, the first aluminum film ALL. For example, the aluminum film ALL is 5000
[It is formed with a film thickness comparable to that of a human. Aluminum film A
L1 is an interlayer insulating film (
For example, the PSG film is provided on the IA.

The horizontal scanning line HL is connected to the gate electrode (polycrystalline silicon film P-8i) of the horizontal switch MOSQh through the connection hole C2 formed in the interlayer insulating film IA.

The intermediate layer MLI or ML2 is connected to the semiconductor region N+, which is the drain region of the horizontal switch MOSQh, through the connection hole C1. Solid-state imaging device C of this embodiment
HI is composed of a color element (or may be a monochrome element), and the intermediate conductive layer MLI is made of yellow Ye.
, white W, and the intermediate conductive layer ML2 is provided with color filters of cyan Cy and green G.
A solid-state image sensor is provided with each color filter. Each of the intermediate conductive layers MLI and ML2 is formed of the same conductive layer as the horizontal scanning line HL.

The intermediate conductive layer MLI includes the semiconductor region N' of the horizontal switch MOSQh and the output signal line H8 extending substantially above the semiconductor region N'.
I, H83, . . . The intermediate conductive layer MLI is mainly configured to reduce the step shape during the connection and improve the reliability of the connection. The intermediate conductive layer ML2 is configured to connect the semiconductor region N1 of the horizontal switch MOSQh to the output signal lines H82, H84, . . . extending in an upper layer in a different region from the semiconductor region N1. The intermediate conductive layer ML2 is mainly configured to improve the reliability of the connection and to connect the semiconductor region N+ of different regions and the output signal line H8.

The intermediate conductive layer MLI is connected to output signal lines H8I, H83, . . . extending in the row direction between the solid-state image sensors (element isolation insulating film LOG) arranged in the column direction. The output signal line H8 is connected to a conductive layer above the aluminum ALL, for example, a second layer of aluminum film AL.
It consists of 2.

The aluminum film AL2 has a thickness of, for example, 8000 to 9000[
The thickness of the film is approximately the same as that of a human. The aluminum film AL2 is
An interlayer insulating film (for example, PS
G film) is provided on the IB. The output signal line H8 is connected to the intermediate conductive layer MLI through the connection hole C3 formed in the interlayer insulating film IB.

As shown in FIGS. 3 and 4, the intermediate conductive layer ML2 includes a layer extending in the row direction approximately at the center of the solid-state image sensors arranged in the column direction, overlapping the vertical scanning line VL, and extending in the row direction. Output signal lines H82, H84, . . . are connected thereto. The output signal line HS is.

For example, it is composed of a second layer of aluminum film AL2. The output signal line H8 is connected to the intermediate conductive layer ML2 through the connection hole C3. Output signal line H8 of light receiving section SA
2, 1 (84, . . . ) are vertical scanning lines VL and output signal lines H82, .
H84,... are superimposed.

In the optical black part OB region, as shown in FIG. 4, an interlayer insulating film (for example, P
SG film) A light shielding film SF is provided with an IC interposed therebetween. The light shielding film SF is, for example, a third layer aluminum film A.
Formed by L3. The aluminum film AL3 is formed, for example, by vapor deposition or sputtering, and has a thickness of about 10,000 [layers].

The TSL type solid-state imaging device CHI configured as described above
As shown in FIGS. 3 and 4, one electrode is connected to the semiconductor region N1 on the side to which the photoelectric conversion element PD of the vertical switch MOS Qv of the solid-state image sensor is connected, and this vertical A capacitive element PC is provided, the other electrode of which is connected to the gate electrode of the switch MOS. The capacitive element P
C has one electrode connected to the semiconductor region N' on the side to which the photoelectric conversion element PDI of the vertical switch MOS Q v 1 is connected, and the capacitive element PCI whose gate electrode is connected to the other electrode, and the vertical switch C. Switch M OS Q v 2
One electrode is connected to the semiconductor region N' on the side to which the photoelectric conversion element PD2 is connected, and the capacitive element PC2 has the other electrode connected to its gate electrode.

The capacitive element pc (each of the capacitive elements PCI and PC2) is composed of a parasitic capacitor (or a Miller capacitor or a coupling capacitor jt). In other words, the capacitive element PC consists of two vertical switches M that have a common gate electrode and are connected in series.
Vertical switch M OS with OS Qv 1 and Qv2
By configuring Q v, each capacitive element PCI,
It is configured to connect PC2 and actively increase the capacitance value.

Next, the information reading operation of the TSL type solid-state imaging device CHI configured as described above will be briefly explained using FIGS. 9 to 14. 9 to 13 are simplified equivalent circuit diagrams (one solid-state image sensor is shown) of the solid-state image sensor CHI shown for each information read operation step.

FIG. 14 is a time chart of the information read operation.

First, as shown in FIG. 9, a predetermined solid-state image sensor is selected by selecting the vertical scanning line VL and the horizontal scanning line HL (to high level: H), and information S of the selected solid-state image sensor is selected. Read out. That is, the selected solid-state image sensors are the vertical switch MOS Qv (Qvl and Qv2) and the horizontal switch MOSQh.

The output control MOSQS of the output circuit OUT can be operated (ON state), and the photoelectric conversion element PD (PDI,
The information (photoelectrons) S stored in each of the PDs (PD2) can be read out via the output signal line H8.

Next, as shown in FIG. 10, the vertical scanning line VL and horizontal scanning line HL are each unselected (low level: L) to bring the solid-state image sensor into a non-selected state. In other words, the solid-state image sensor is
Vertical switch MOSQv (Qvl and Qv2), horizontal switch MOSQh, and output control MOSQS do not operate (become OFF state). Further, at this time, the reset MOS Qr of the horizontal retrace period reset unit RES is not operating. From this non-selected state, the photoelectric conversion element PD (PDI, PD2, respectively) of the solid-state image sensor
The accumulation of information (photoelectrons) begins with the incidence of light.

Next, as shown in FIG. 11, when the solid-state image sensor is in a non-selected state, the reset signal line RP of the horizontal retrace period reset unit RES is selected (to H), and the reset MOSQr is activated (turned to ON state). let This reset MOS
During the operation period of Qr, the photoelectric conversion element P of the solid-state image sensor
When strong light ph is incident on D (PDI, PD2), the photoelectric conversion element FD becomes saturated and stops accumulating photoelectrons, and a part of the excess photoelectrons (false signal S') is transferred to the vertical switch MOSQV and the horizontal The signal leaks beyond the switch MOSQh to the output signal line H8. Some of these excess photoelectrons cause blooming, but since the reset MOSQr is operating, they are drawn out to the reset output line . □ Next, as shown in FIGS. 12 and 14 (timing a), the reset M of the horizontal retrace period reset section RES is
After the operation of the OS Qr stops (OF state), the vertical scanning line VL is turned on again to read out the information from the solid-state image sensor.
Select. The vertical scanning line VL is selected using the vertical switch M.
OSQv (Qvl and Qv2), MOSQS for output control
simultaneously operate (turn on) each of them. In selecting this vertical scanning line VL, the vertical switch MOSQv
(Qvl.

Qv2) and the photoelectric conversion element PD (PDI, PD2).

Due to the coupling effect of PC2), an increase in the potential of the vertical scanning line VL increases the potential of the photoelectric conversion element, so that the photoelectric conversion element PD can be brought into a non-saturated state at this moment. In the non-saturated state, the amount of photoelectrons accumulated in the photoelectric conversion element PD appears to be increased, and leakage of excessive photoelectrons to the output signal line H8 is eliminated.

In this non-saturated state, as shown in FIGS. 13 and 14 (timing b), by selecting the horizontal scanning line HL and operating the horizontal switch MOSQh, the information of the solid-state image sensor is stored without blooming. S can be read.

In this way, in the TSL type solid-state imaging device CHI, by providing the capacitive element PC between the vertical switch MOSQV of the solid-state imaging device and the photoelectric conversion element PD, the gate electrode of the vertical switch MOSQv can be selected. Sometimes, the photoelectric conversion element PD can be brought into a non-saturated state by the coupling effect of the capacitive element PC by this selection signal, so that blooming can be prevented by reading out the information S of the solid-state image sensor when it is in this unsaturated state. can be reduced.

(Example 2) Example 2 is another example of the present invention in which blooming is further reduced in a TSL type solid-state imaging device.

FIG. 15 shows a TSL type solid-state imaging device which is Embodiment 2 of the present invention (a plan view of the main part showing the solid-state imaging device of the light receiving section SA).
Indicated by

The solid-state imaging device CHI of this embodiment is configured to increase This increase in the number of capacitive elements PD is achieved by defining the solid-state image sensor forming region with an inter-element isolation insulating film LOG so that the gate width of the vertical switch M OS Q v 2 becomes longer. That is, in the embodiment I, the vertical scanning line VL between the photoelectric conversion elements PDI and PO2
In this embodiment (2), the capacitance value of the capacitive element PC is increased by recessing the element isolation insulating film LOG that was protruding downward.

The TSL type solid-state imaging device CHI configured as described above
Since the non-saturation state of the photoelectric conversion element PD can be improved to a high level, blooming can be further reduced.

(Example 2) Example 2 is another example of the present invention in which the present invention is applied to another solid-state image sensor having a different configuration (layout) in a TSL type solid-state imaging device.

FIG. 16 shows a TSL type solid-state imaging device which is Embodiment ① of the present invention (a plan view of the main part showing the solid-state imaging device of the light receiving section SA).
Indicated by

The solid-state imaging device CHI of this embodiment (■) has a horizontal switch MO
SQh, vertical switch MOS Qv, and photoelectric conversion element PD are connected in series to form a solid-state image sensor. Vertical switch MOS Qv and photoelectric conversion element PD
The capacitive element PC actively provided between the vertical scanning line V
A part of the vertical scanning line VL is extended above the photoelectric conversion element PD (semiconductor region N''), and a parasitic capacitance (substantially formed by the extended part of the vertical scanning line VL and the semiconductor region N1) is (a gate insulating film is provided below a portion of the vertical scanning line VL).

The TSL type solid-state imaging device CHI configured as described above
Similarly to Example I, blooming can be reduced.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

The present invention can be applied to a single line readout type solid-state imaging device in a TSL type solid-state imaging device.
- I can.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a TSL type solid-state imaging device, blooming can be reduced by providing a capacitive element between the vertical switch MOS of the solid-state imaging element and the photoelectric conversion element.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing a TSL type solid-state imaging device which is Embodiment I of the present invention, FIG. 2 is an equivalent circuit diagram of the solid-state imaging device shown in FIG. 1, and FIG. 3 is a light receiving device. FIG. FIG. 4 is a plan view of the main part showing the solid-state image sensor in the optical black section, FIG. 5 is a cross-sectional view taken along the line ■--■ in FIG. 3, and FIG. 7 is a plan view of the main part of the solid-state imaging device in a predetermined manufacturing process; FIG. 8 is a plan view of the main part of the solid-state imaging device in a predetermined manufacturing process; 9 to 13 are simplified equivalent circuit diagrams of the solid-state imaging device shown for each information read operation process. FIG. 14 is a time chart of the information read operation;
The figure is a plan view of a main part showing the solid-state image sensor of the light receiving part of a TSL type solid-state imaging device which is an embodiment (■) of the present invention, and FIG. FIG. 2 is a plan view of main parts showing a solid-state image sensor of a light receiving section of FIG. In the figure, CHI... solid-state imaging device (solid-state imaging chip),
ARR...Photodiode array, SA...Light receiving section, OB...Optical black section1. INT...Interlace scan control section, Vreg...Vertical scanning shift register section, Hreg...Horizontal scanning shift register section, OUT...Output circuit, VL・Vertical scanning line, H
L...Horizontal scanning line, H8...Output signal line, Qh...
Horizontal switch MOS, Qv...vertical switch MOS,
PD...Photoelectric conversion element, ML...Intermediate conductive layer, SF...
- Light shielding film, PC... Capacitive element. =31-5A... Light receiving section OB... Optical black section Vreq... Vertical scanning shift register section 1-1re
9...Horizontal short term shift raster section RES...Horizontal retrace period reset section INT...Interlace scan control section OUT...Output circuit CHI...Solid-state imaging chisso.

Claims (1)

[Claims] 1. In a horizontal readout type MOS type solid-state imaging device having a solid-state imaging device in which a horizontal switch MOS, a vertical switch MOS, and a photoelectric conversion element are each connected in series, the photoelectric conversion element of the vertical switch MOS 1. A solid-state imaging device comprising a capacitive element having one electrode connected to a semiconductor region to which the vertical switch MOS is connected and the other electrode connected to a gate electrode of the vertical switch MOS. 2. The solid-state imaging device according to claim 1, wherein the capacitive element is a parasitic capacitance formed between a semiconductor region of a vertical switch MOS and a gate electrode. 3. The solid-state imaging device according to claim 1 or 2, wherein the capacitive element is composed of a plurality of vertical switch MOSs having a common gate electrode and connected in series. . 4. The photoelectric conversion element is comprised of a PN junction formed by a semiconductor region of a vertical switch MOS and a substrate or well region provided with this semiconductor region. Each of the solid-state imaging devices described in Items 1 to 3. 5. The capacitive element is configured by extending a part of a vertical scanning line connected to the gate electrode of the vertical switch MOS above the photoelectric conversion element. Each of the solid-state imaging devices described in Items 1 to 4.