JP2569045B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a technology effective when applied to a MOS solid-state imaging device.

[Conventional technology]

A MOS solid-state imaging device used for an imaging device such as a video camera basically includes a series circuit of a switch MOS and a photoelectric conversion element (photodiode element) to constitute a solid-state imaging element. The photoelectric conversion element has a linear signal current amount generated with respect to the incident amount of photoelectrons, that is, a photoelectric conversion characteristic, and can accumulate photoelectrons based on the saturation capacitance value.

The human eye has high sensitivity when dark and low sensitivity when bright, and the detection sensitivity to noise changes depending on the brightness. Utilizing such human detection sensitivity, the standard light amount of the photoelectric conversion element is set at a place where the photoelectric conversion characteristic is low, which is the detection limit, to increase the sensitivity in darkness and to lower the sensitivity in bright light, such as a video camera. The imaging device of the above has improved the dynamic range. The improvement of the dynamic range of this imaging apparatus is performed in a circuit.

The solid-state imaging device is described in, for example, Nikkei Microdevice, June 1986, pp. 59-86.

[Problems to be solved by the invention]

However, as a result of the study by the present inventor, the MOS type solid-state imaging device sets the standard light amount at a place where the photoelectric conversion characteristic of the photoelectric conversion element is low as described above, so that the signal output at the standard light amount and the darkness are set. There is a problem that the ratio (S / N ratio) to the noise level at the time becomes worse.

An object of the present invention is to provide a technique capable of improving the dynamic range of a solid-state imaging device and improving the S / N ratio.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

In a solid-state imaging device in which a solid-state imaging device is arranged at an intersection of a horizontal scanning line and a vertical scanning line, a first solid-state imaging device including a first photoelectric conversion element having a first saturation light amount; And a second solid-state imaging device including a second photoelectric conversion element having a different second saturated light amount are alternately arranged in the direction in which the vertical scanning lines extend.

[Action]

According to the above-described means, the signal currents of the first photoelectric conversion element and the signal currents of the second photoelectric conversion element having different saturation light amounts are alternately read, and apparently, the two signal currents are combined, and the sensitivity in darkness is reduced. And the sensitivity can be reduced when the image is bright, so that the standard light amount can be increased to improve the S / N ratio and the dynamic range.

Hereinafter, the configuration of the present invention, horizontal read (TSL for use in an image pickup apparatus such as a video camera: T ransversal S ignal
L ine) will be described with an example in which the present invention is applied to monochrome MOS type solid-state imaging apparatus of a system.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

〔Example〕

FIGS. 1 (schematic diagram) and 2 (equivalent circuit diagram) of a TSL type monochrome solid-state imaging device according to an embodiment of the present invention.
Indicated by

As shown in FIG. 1, the TSL type solid-state imaging device (solid-state imaging chip) CHI has a photodiode array ARR in which a plurality of cells (pixels) are arranged in a matrix at a central portion.

The photodiode array ARR includes a light receiving section SA and an optical black section OB. The light receiving unit SA is configured to convert an optical signal incident through the optical lens into electric charges and accumulate the electric charges. Optical black part OB
Are configured to constitute a reference value (optical black level) for correcting noise due to dark current.

Around the right side of the photodiode array ARR, a horizontal flyback period reset unit RES, an interlace scanning control unit INT,
A vertical scan shift register section (vertical scan circuit) Vreg is provided. A horizontal scanning shift register section (horizontal scanning circuit) Hreg is provided around the lower side, and an output circuit (readout circuit) OUT is provided on the left side.

As shown in FIG. 2, the photodiode array AR
R light receiving section SA, vertical scanning lines VL1, VL2, ..., horizontal scanning lines HL1, H
, L2,... And output signal lines HS1, HS2,. The vertical scanning lines VL extend in the row direction, and a plurality of the vertical scanning lines VL are arranged in the column direction. The horizontal scanning lines HL extend in the column direction, and a plurality of the horizontal scanning lines HL are arranged in the row direction. The output signal line HS
A plurality of the scanning lines extend in the same row direction as the vertical scanning lines VL, and are arranged in the column direction.

The pixel has a horizontal switch MOSQh, a vertical switch MOSQv
(Qv1, Qv2), photoelectric conversion element (photodiode) PD (P
D1, PD2). One semiconductor region of the horizontal switch MOSQh and the other semiconductor region of the vertical switch MOSQv are connected, and both are connected in series. The photoelectric conversion element PD1 is connected to the other semiconductor region of the vertical switch MOSQv1, and the photoelectric conversion element PD2 is connected to the vertical switch MOSQv
2 is connected to one of the semiconductor regions.

The gate electrodes of the horizontal switches MOSQh of the plurality of solid-state imaging devices arranged in the column direction are connected to one horizontal scanning line HL. The horizontal scanning line HL is connected to the horizontal scanning shift register Hreg. Horizontal scan shift register
Hreg is configured to sequentially scan a plurality of horizontal scanning lines HL arranged in the row direction by an input signal Hin and clock signals φh ₁ and φh ₂ to select a pixel in the row direction.

Vertical switch MOSQv of multiple pixels arranged in the row direction
The gate electrode of each (Qv1 and Qv2) has one vertical scanning line V
Connected to L. One end of the vertical scanning line VL is connected to a vertical scanning shift register unit Vreg via an interlaced scanning control unit INT. The vertical scanning shift register unit Vreg outputs selection signals R ₁ , R ₂ ,... For sequentially scanning a plurality of vertical scanning lines VL arranged in the column direction according to the input signal Vin and the clock signals φv ₁ , φv ₂ . It is configured to output to the interlace scanning control unit INT.

The interlace scanning control unit INT outputs the field selection signal F
The switch MOSQFe or QFo is controlled by e or Fo, and the selection signal R
Is configured to select the driving MOSQd transmitting the signal. A boost capacitor is provided between the gate electrode of the driving MOS Qd and one semiconductor region (vertical scanning line VL). The other semiconductor region of the drive MOSQd, vertical scanning signals phi ₃ and phi ₄ is applied. That is, the vertical scanning signal phi ₃ or phi _4, based on the selection signal R, driving MOSQ
d is applied to the vertical scanning line VL. The driving MOSQd is
By the boosting capacitor, without causing a voltage drop corresponding to the threshold voltage, the vertical scanning signal phi ₃ or phi ₄
Can be applied to the vertical scanning line VL.

The interlace scanning control unit INT is configured to perform two-line simultaneous reading and interlace scanning. That is, first, the interlace scanning control unit INT selects two adjacent vertical scanning lines VL (for example, VL1 and VL2, VL3 and VL4) of the odd field A according to the field selection signal F. Next, the interlaced scanning control unit INT generates two vertical scanning lines VL (eg, VL2 and VL3,
VL4 and VL5).

The other end of the vertical scanning line VL is the output control M of the output circuit.
Are connected to the gate electrodes of OSQS1, QS2,. The output control MOSQS is connected to one end of the output signal line HS and the output line of the output circuit OUT.
It is configured to connect to S1 or S2.

The output signal line HS is connected to the other semiconductor region (drain region) of the horizontal switch MOSQh of the plurality of solid-state imaging devices arranged in the row direction. The other end of the output signal line HS is connected to the reset output line (video signal line) Vr via the reset MOS Qr of the horizontal blanking period reset section RES. The gate electrode of the reset MOSQr is connected to and controlled by the reset signal line RP. The horizontal blanking period reset unit RES is configured to reset the false signal stored during the horizontal scanning period.

Next, a specific device structure of the CHI of the TSL type solid-state imaging device will be described with reference to FIGS.
FIG. 3 is a main part plan view showing a solid-state imaging device of the light receiving unit SA,
FIG. 4 is a plan view of a main part showing a solid-state image sensor of the optical black section OB. 5 is a cross-sectional view taken along the line VV in FIG. 3, and FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG.

As shown in FIGS. 3 to 6, each pixel of the light receiving section and the optical black section OB has basically the same structure.

Each solid-state image sensor of the light receiving section SA and the optical black section OB is formed on the main surface of the well region WELL provided on the semiconductor substrate SUB, and the periphery thereof is defined by the element isolation insulating film LOC.

The semiconductor substrate SUB is formed of an N type made of single crystal silicon. The well region WELL is formed of a P-type and mainly forms an N-channel MOSFET. When the well region WELL is not provided, the P-type semiconductor substrate SUB is used.

The element isolation insulating film LOC is composed of a silicon oxide film formed by selectively thermally oxidizing the main surface of the well region WELL. As shown in FIGS. 3 and 4, the inter-element isolation insulating film LOC has a pixel forming region formed in a U-shape. More specifically, the element isolation insulating film LOC is a horizontal switch MOSQh
The area of the formation region is small, and in order to increase the opening area (opening ratio) of the photoelectric conversion element PD, the vertical switch MOSQv formation region is formed in a U-shape so as to have a large area.

As shown in FIG. 3 to FIG. 6 and FIG. 7 (main part plan view in a predetermined manufacturing process), the horizontal switch MOSQh of the pixel mainly includes a well region WELL, a gate insulating film, a gate electrode, and a source. It is composed of a pair of N ⁺ type semiconductor regions (N ⁺ ) which are regions or drain regions.

The gate insulating film is, for example, a silicon oxide film formed by oxidizing the main surface of the well region WELL region, 300 to 500
It is formed with a thickness of about [Å].

The gate electrode is formed of a gate electrode material, for example, a polycrystalline silicon film (semiconductor film) P-Si. Polycrystalline silicon film P
-Si is formed with a film thickness of, for example, about 3000 to 4000 [Å]. The gate electrode is made of a refractory metal (Mo, Ti, Ta, W) film or refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WS).
i ₂ ) It may be formed of a film or a polycrystalline silicon film and a composite film thereof.

In the semiconductor region N ⁺ , an N-type impurity is introduced into the main surface portion of the well region WELL by ion implantation using the gate electrode as a mask.
This is formed by stretching and diffusing.

The semiconductor region N ^+, which is the drain region of the horizontal switch MOSQh, is formed on the main surface of a P ⁺ type semiconductor region (P ⁺ ) having a higher impurity concentration than the well region WELL. Semiconductor area
P ⁺ is diffused to the channel formation region of the horizontal switch MOSQh. This semiconductor region P ⁺ is connected to the horizontal switch MOSQh
Is configured to increase the threshold voltage. In other words, the semiconductor region P ⁺ is configured to reduce the movement of electrons that cause blooming from the photoelectric conversion element PD to the output signal line HS.

Like the horizontal switch MOSQh, the vertical switch MOSQv1 mainly includes a well region WELL, a gate insulating film, a gate electrode, and a pair of semiconductor regions N ⁺ that are a source region or a drain region.

Like the horizontal switch MOSQh, the vertical switch MOSQv2 mainly includes a well region WELL, a gate insulating film, a gate electrode, and a pair of semiconductor regions N ⁺ that are a source region or a drain region.

The gate electrodes of the vertical switches MOSQv1 and Qv2 are formed in the same manufacturing process as the gate electrodes of the horizontal switch MOSQh. The respective gate electrodes of the vertical switches MOSQv1 and Qv2 extend in the row direction across the center of the photodiode forming region (or the light receiving unit), and are formed integrally (commonly). In addition, vertical switches MOSQv1, Qv
Each gate electrode 2 has a vertical scanning line V extending in the row direction.
It is configured integrally with L. That is, the vertical scanning line VL is
The solid-state imaging device is configured to extend substantially in the upper center in the row direction. Actually, the vertical scanning line VL is located above the photoelectric conversion element PD, specifically, between the photoelectric conversion element PD1 and the photoelectric conversion element PD2 (the photoelectric conversion element PD in the solid-state imaging element).
1, near each of PD2).

One semiconductor region N ⁺ is the vertical switch MOSQv1, is configured (shared) in one semiconductor region N ⁺ integral horizontal switches MOSQh. Other semiconductor region N ⁺ is the vertical switch MOSQv1, are other semiconductor region N ⁺ and constructed integrally of a vertical switch MOSQv2 (shared). That is, the vertical switch MO
Each of SQv1 and Qv2 has a common gate electrode and is connected in series.

The photoelectric conversion element PD1 is particularly, as shown in FIG. 5, PN of the other semiconductor region N ⁺ and the well region WELL in other semiconductor region N ⁺ or vertical switch MOSQv2 vertical switch MOSQv1
It consists of a joint. Note that one semiconductor region N ^{+ of the} switch MOSQv1 or one semiconductor region N of the horizontal switch MOSQh
^A photoelectric conversion element (photodiode element) is also formed at the PN junction between the ⁺ and the well region WELL, but since the MOS Qh is turned on for each horizontal scan (H), it is in the N ⁺ region common to Qv1 and Qh. The stored information is reset every H and only 1H contributes to the output and can be ignored. For example, even if the photodiode PD and the N ⁺ region common to Qv1 and Qh have the same area, the N ⁺ region common to Qv1 and Qh can store only 2/525 information compared to PD. The semiconductor region N ⁺ constituting the photoelectric conversion element PD1 is formed with an impurity concentration of, for example, about 10 ²⁰ [atoms / cm ³ ], and the well region WELL is formed of, for example, 10 ¹⁵
It is formed with an impurity concentration of about 10 ¹⁶ [atoms / cm ³ ].

The photoelectric conversion element PD2 includes a PN junction between one of the semiconductor regions N ⁺ and the well region WELL vertical switch MOSQv2, one semiconductor region N ⁺ and P ⁺ -type semiconductor region of a vertical switch MOSQv2 (P ⁺
_PD ) and a PN junction. Semiconductor area P ⁺ _PD
Is a PN formed by at least the semiconductor region N ⁺ and the well region WELL as shown by a dotted line in FIG. 3, FIG. 4 and FIG. 7 (representing the opening pattern of the P-type impurity introduction mask).
Extremely formed at the junction (along the semiconductor region N ⁺ ). The semiconductor region P ⁺ _PD has the same conductivity type as the well region WELL, and has a higher impurity concentration, for example, 10 ¹⁷ [atoms / cm ³ ].
It is formed with an impurity concentration of the order. The semiconductor region P ⁺ _PD can be formed by introducing (ion implantation or diffusion) a P-type impurity before or after introduction (ion implantation or diffusion) of an N-type impurity forming the semiconductor region N ⁺ . Further, the semiconductor region P ⁺ _PD may be formed in the same manufacturing process and at the same impurity concentration as the semiconductor region P ⁺ formed on the horizontal switch MOSQh side, or may be formed under different conditions.

As described above, each of the photoelectric conversion elements PD1 and PD2 is connected via the vertical switch MOSQv2, and during accumulation of photoelectrons, the vertical switch MOSQv2 is set to a non-operating state (OFF state) to accumulate photoelectrons independently. However, at the time of reading, since the vertical switch MOSQv2 is in the operating state (ON state), each can be read simultaneously, it can be regarded as one photoelectric conversion element PD of one solid-state imaging device.

The semiconductor region P ⁺ _PD provided extremely at the PN junction of the photoelectric conversion element PD2 is shown in FIGS. 3, 4, 7, and 8 (schematic layout diagram of the photodiode array). The area is different from that of the other adjacent photoelectric conversion element PD2. The photoelectric conversion element PD _A semiconductor regions P ⁺ _PD of large area photoelectric conversion element PD2 is provided, since the saturation signal current with increasing junction capacitance increases, the saturation amount of light with sensitivity is high is reduced. On the other hand, the photoelectric conversion element PD
Photoelectric conversion element P provided with semiconductor area P ⁺ _PD with small area 2
D _B is compared to the photoelectric conversion element PD _A, since the junction capacitance is small saturation signal current is small, the saturation amount of light with sensitivity is lowered increases. This photoelectric conversion element PD with a small amount of saturated light
A solid-state imaging device having _A, and the solid-state imaging device saturation amount has a large photoelectric conversion element PD _B, they are arranged alternately in the extending direction of the vertical scanning lines VL. Further, the solid-state imaging device having a photoelectric conversion element PD _A, a solid-state imaging device having a photoelectric conversion element PD _B is the layout, are arranged alternately in the extending direction of the horizontal scanning lines HL. That is, the solid-state imaging devices are arranged in a checkered pattern. The saturation light amount is
Simply, simply changing the area ratio of the photoelectric conversion element PD _A and the photoelectric conversion element PD _B has no effective change, as in the present invention,
Unless the semiconductor region P ⁺ _PD is provided to change the photoelectric conversion characteristics per unit area, no effective change occurs.

Saturated amount L _A is <1> type of the photoelectric conversion element PD _A, saturated amount L _B of the photoelectric conversion element PD _B can be obtained respectively in <2> equation.

_{L A = I A sat / S} A ...... <1> L B = I B sat / S B ...... <2> However, I _A sat: PD _A saturated signal current I _B sat: saturation signal current PD _B S _a: sensitivity of PD _a S _B: sensitivity said PD _B <1> expression from each of <2> _{formula, I a sat, S a,} I B s
at, by controlling the S _B by the area of the semiconductor region P ⁺ _PD, saturated amount of the photoelectric conversion element PD _A L _A and the photoelectric conversion element PD _B
It is possible to set the the saturation amount of light L _B properly.

When the predetermined vertical scanning line VL is selected, the monochrome solid-state imaging device CHI of the TSL system configured as described above sequentially selects the horizontal scanning line HL to select the photoelectric conversion of the solid-state imaging device connected to the vertical scanning line VL. since reads the signal current of the conversion element PD (information) sequentially and the signal current of the signal current and the photoelectric conversion element PD _B of the photoelectric conversion element PD _a are read alternately. The read signal current is apparently photoelectrically sensitive to the human eye as shown in FIG. 9 (a photoelectric conversion characteristic diagram showing the relationship between the amount of incident light and the amount of signal current generated based on it). You can see the signal current conversion element PD _a and the signal current of the photoelectric conversion element PD _B in synthesized form. The Figure 9 shows a case of setting the saturation amount of light L _B at twice the saturated amount L _A. That is, as shown in FIG. 9, the photoelectric conversion characteristics can be formed knee (knee) point K, by setting the standard quantity to the knee point K or the vicinity thereof, a small saturation amount of light L _A High sensitivity when dark (S _A +
S _B ), when the saturation light amount L _B is large and bright, the sensitivity can be lowered (S _B ). Therefore, the solid-state imaging device CH
For I, the standard light quantity can be set at a place where the signal current is high, so that the S / N ratio can be improved. .

As shown in detail in FIG. 10 (a plan view of a main part in a predetermined manufacturing process), the horizontal scanning line HL is formed between solid-state imaging element formation regions (element isolation insulating film LOC) arranged in the row direction.
It is configured to extend in the column direction. Horizontal scanning line HL
Is formed of a conductive layer above the polycrystalline silicon film P-Si, for example, a first aluminum film AL1. The aluminum film AL1 is formed to a thickness of, for example, about 5000 [Å]. The aluminum film AL1 is provided on an interlayer insulating film (for example, a PSG film) IA that covers the horizontal switch MOSQh and the like. The horizontal scanning line HL is connected to the interlayer insulating film IA.
Is connected to the gate electrode (polycrystalline silicon film P-Si) of the horizontal switch MOSQh through the connection hole C2 formed in the first switch.

Semiconductor region N which is the drain region of horizontal switch MOSQh
^The intermediate conductive layer ML1 or ML2 is connected to ⁺ through the connection hole C1.

The intermediate conductive layer ML1 is connected to the semiconductor region N ^{+ of the} horizontal switch MOSQh.
, And output signal lines HS1, HS3,... Extending substantially above it. The intermediate conductive layer ML1 is
It is mainly configured to reduce the step shape at the time of the connection and to improve the reliability of the connection. The intermediate conductive layer ML2 is
It is configured to connect the semiconductor region N ⁺ of the horizontal switch MOSQh and the output signal lines HS2, HS4,. The intermediate conductive layer ML2 is mainly configured to improve the reliability of the connection and connect the semiconductor region N ^{+ in} a different region to the output signal line HS.

The intermediate conductive layer ML1 is connected to output signal lines HS1, HS3,... Extending in the row direction between the solid-state imaging devices (element isolation insulating films LOC) arranged in the column direction. Output signal line
HS is formed of a conductive layer above the above-described aluminum AL1, for example, a second-layer aluminum film AL2.
The aluminum film AL2 is formed to a thickness of, for example, about 8000 to 9000 [Å]. The aluminum film AL2 is provided on an interlayer insulating film (for example, a PSG film) IB covering the aluminum film AL1. The output signal line HS is connected to the intermediate conductive layer ML1 through a connection hole C3 formed in the interlayer insulating film IB.

As shown in FIGS. 3 and 4, the intermediate conductive layer ML2 extends in the row direction over the vertical scanning line VL substantially at the center of the solid-state imaging device arranged in the column direction. Output signal lines HS2, HS4,. The output signal line HS is made of, for example, a second aluminum film AL2. The output signal line HS is connected to the intermediate conductive layer ML2 through the connection hole C3. Output signal line HS2, HS of light receiving section SA
As described above, the vertical scanning lines VL and the output signal lines HS2, HS4,... Are overlapped so that the opening area of the photoelectric conversion element (photoelectric conversion region) PD can be formed as large as possible. I have.

In the optical black part OB area, as shown in FIG. 4, an interlayer insulating film (for example, PSG
Film) A light shielding film SF is provided with an IC interposed. Light shielding film
SF is formed of, for example, a third aluminum layer AL3. The aluminum film AL3 is formed, for example, by vapor deposition or sputtering, and has a thickness of about 10,000 [Å].

The present invention, as in the solid-state imaging device of the aforementioned TSL system is smaller than other saturated amount of the photoelectric conversion elements PD _B adjacent the saturation amount of the photoelectric conversion elements PD _A solid-state imaging device, a semiconductor the junction between the region N ⁺ and the well region wELL, and a semiconductor region N ⁺ of the same conductivity type than that may be provided with semiconductor regions N ⁺⁺ of high impurity concentration.

The present invention, in a solid-state imaging device of the aforementioned TSL system, so as to reduce as compared with the saturated amount of another photoelectric conversion element PD _B adjacent the saturation amount of the photoelectric conversion elements PD _A solid-state imaging device, the photoelectric the semiconductor regions P ⁺ _PD provided in the conversion element PD _a, may not be provided a semiconductor region P ⁺ _PD in the photoelectric conversion element PD _B.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.

The present invention is not limited to the solid-state imaging device of the TSL system described above, and can be widely applied to a solid-state imaging device having a solid-state imaging device formed by a switch MOS and a photoelectric conversion element.

Further, the present invention is not limited to a monochrome MOS solid-state imaging device, but can be applied to a color MOS solid-state imaging device.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

In a solid-state imaging device having a solid-state imaging device formed by a switch MOS and a photoelectric conversion element, the S / N ratio can be improved and the dynamic range can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a TSL type solid-state imaging device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the solid-state imaging device shown in FIG. 1, and FIG. FIG. 4 is a main part plan view showing the solid-state imaging device of the optical black portion, FIG. 5 is a cross-sectional view taken along the line VV in FIG. 3, 6 is a cross-sectional view taken along the line VI-VI of FIG. 3, FIG. 7 is a plan view of a main part in a predetermined manufacturing process of the solid-state imaging device, and FIG. FIG. 9 is a schematic layout diagram of a photodiode array, FIG. 9 is a photoelectric conversion characteristic diagram of a solid-state imaging device of the solid-state imaging device, and FIG. 10 is a plan view of a main part in a predetermined manufacturing process of the solid-state imaging device. In the figure, CHI ... solid-state imaging device (solid-state imaging chip), ARR ...
... Photodiode array, SA ... Light receiving section, OB ... Optical black section, INT ... Interlaced scanning control section, V
reg: Shift register for vertical scanning, Hreg: Shift register for horizontal scanning, OUT: Output circuit, VL: Vertical scanning line, HL: Horizontal scanning line, HS: Output signal line, Qh:
Horizontal switch MOS, Qv: Vertical switch MOS, PD: Photoelectric conversion element, ML: Intermediate conductive layer, SF: Light-shielding film, P ⁺ _PD ...
It is a semiconductor region.

Claims (5)

(57) [Claims] 1. A solid-state imaging device in which a solid-state imaging device including a switch MOS and a photoelectric conversion element is arranged at an intersection of a horizontal scanning line and a vertical scanning line, the first photoelectric conversion having a first saturated light amount. A first solid-state imaging device comprising the first solid-state imaging device; a second solid-state imaging device comprising a second photoelectric conversion device having a second saturation light amount different from the first saturation light amount; and a first photoelectric conversion device of the first solid-state imaging device. A solid-state imaging device, wherein the elements and the second photoelectric conversion elements of the second solid-state imaging element are alternately arranged in a direction in which the vertical scanning line extends. 2. The solid-state imaging device according to claim 1, wherein said first photoelectric conversion element and said second photoelectric conversion element are arranged in a checkered pattern. 3. The device according to claim 1, wherein the first photoelectric conversion element of the first solid-state imaging device is formed of a PN junction having an impurity concentration different from that of the second photoelectric conversion element of the second solid-state imaging device. Item 3. The solid-state imaging device according to Item 1 or 2. 4. The high-impurity-concentration P-type or N-type photoelectric conversion element is formed at least partially at the PN junction.
4. The solid-state imaging device according to claim 3, wherein the solid-state imaging device is configured by introducing a type semiconductor region. 5. The semiconductor device according to claim 4, wherein said semiconductor region is configured to change a photoelectric conversion characteristic per unit area of said first or second photoelectric conversion element. Solid-state imaging device.