JPS63266875A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To enhance a dynamic range and to improve an SN ratio by a method wherein a device is constituted by a switch MOS, a first photoelectric converter and a second photoelectric converter and the first photoelectric converter or the second photoelectric converter is constituted by a P-N junction whose impurity concentration is high as compared with the second photoelectric converter or the first photoelectric converter. CONSTITUTION:Semiconductor regions N<+> constituting a photoelectric converter PD1 are formed at an impurity concentration of, e.g., about 10<20> [atoms/cm<2>]; semiconductor regions P<+>PD of a photoelectric converter PD2 are formed at a high impurity concentration, e.g., at an impurity concentration of about 10<17> atoms/cm<2>. That is to say, if the photoelectric converter PD2 constituted by a P-N junction whose impurity concentration is high as compared with that of the photoelectric converter PD1, it is possible to obtain a high saturation point pd2 in the PD2 as compared with a saturation point pd1 of the photoelectric converter PD1. When the information is read out, an added-up signal current Ipd of the photoelectric converters PD1 and PD2 is read out. That is to say, if a standard light quantity is set near a knee point K, it is made possible to improve an SN ratio by increasing the standard light quantity and to enhance a dynamic range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device, and particularly to a technique that is effective when applied to a MOS solid-state imaging device.

[Conventional technology]

MOS type solid-state imaging devices used in imaging devices such as video cameras basically consist of a series circuit of a switch MOS and a photoelectric conversion element (photodiode element). The photoelectric conversion element has a linear photoelectric conversion characteristic, and can accumulate photoelectrons based on a saturated capacitance value, based on a signal current h generated with respect to the amount of incident photoelectrons.

The human eye has high sensitivity when it is dark and low sensitivity when it is bright, and the detection sensitivity to noise changes depending on the brightness. Taking advantage of this human detection sensitivity, the standard light amount of the photoelectric conversion element is set at the detection limit, where the photoelectric conversion characteristics are low, increasing the sensitivity in dark conditions and lowering the sensitivity in bright conditions, such as in video cameras, etc. imaging devices have improved dynamic range. The dynamic range of this imaging device is improved through circuitry.

The solid-state imaging device is described in, for example, Nikkei Microdevice, June 1986 issue, pp. 59-86.

[Problem that the invention seeks to solve]

However, as a result of the inventor's study, as mentioned above, the standard light amount of the MOS solid-state imaging device is set at a location where the photoelectric conversion characteristics of the photoelectric conversion element are low. A problem arises in that the ratio (S/N ratio) between the noise level and the noise level (S/N ratio) deteriorates.

An object of the present invention is to provide a technique that can improve the dynamic range of a solid-state imaging device and improve the S/N ratio.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In a solid-state imaging device having a solid-state imaging device including a switch MOS and a first photoelectric conversion element and a second photoelectric conversion element that independently accumulate photoelectrons, the first or second photoelectric conversion element is connected to the second or second photoelectric conversion element. It is composed of a PN junction with a higher impurity concentration than that of a single photoelectric conversion element.

[Effect]

According to the above-mentioned means, the first or second
The saturation point of the photoelectric conversion element is made higher than that of the second or first photoelectric conversion element, and the total photoelectric conversion efficiency of the first and second photoelectric conversion elements when reading information is increased so that the sensitivity is high when it is dark and the sensitivity is high when it is bright. Since it is possible to lower the standard light amount, the S/N ratio can be improved by increasing the standard light amount, and the dynamic range can also be improved.

The configuration of the present invention will be explained below regarding horizontal transversal (TSL) used in imaging devices such as video cameras.
DESCRIPTION OF THE PREFERRED EMBODIMENTS An example in which the present invention is applied to a MOS type solid-state imaging device of the Al Signal Line method will be described.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔Example〕

The first embodiment of the TSL type solid-state imaging device of the present invention
(schematic configuration diagram) and FIG. 2 (equivalent circuit diagram).

As shown in FIG. 1, the TSL type solid-state imaging device (solid-state imaging chip) C:HI includes a photodiode array ARR in which a plurality of cells (pixels) are arranged in rows and columns in the center.

The photodiode array ARR is composed of a light receiving section SA and an optical black section OB.

The light receiving section SA is configured to convert an optical signal incident through an optical lens into an electric charge and store the electric charge. The optical black section OB is configured to form a reference value (optical black level) in order to correct noise due to dark current components.

Around the right side of the photodiode array ARR, there is a horizontal retrace period reset section RES and an interlace scan control section I.
NT, vertical scanning shift register section (vertical scanning circuit)
vreg is provided. A horizontal scanning shift register section (horizontal scanning circuit) Hreg is provided around the lower side, and an output circuit (continuation circuit) OUT is provided on the left side.

As shown in FIG. 2, the photodiode array AR
R light receiving section SA, vertical scanning lines VLI, VL2 . ...,
Horizontal scanning lines HLI, HL2. ..., output signal line H8I
, H82, . . . The vertical scanning lines VL extend in the row direction, and a plurality of vertical scanning lines VL are arranged in the column direction. The horizontal scanning lines I-IL extend in the column direction and are arranged in plural in the row direction. The output signal line HS is
They extend in the same row direction as the vertical scanning lines VL, and a plurality of them are arranged in the column direction.

The pixel includes a horizontal switch MOSQh and a vertical switch M
It is composed of an OSQv (Qvl, Qv2) and a photoelectric conversion element (photodiode) PD (PDI, PD2).

One semiconductor region of the horizontal switch MOS Q h and the other semiconductor region of the vertical switch MOS Q v are connected, and both are connected in series. The photoelectric conversion element PDI is connected to the other semiconductor region of the vertical switch M OS Q v 1, and the photoelectric conversion element PD2 is connected to one semiconductor region of the vertical switch M OS Q v 2.

The gate electrodes of the horizontal switches MOSQh of the plurality of solid-state image sensors arranged in the column direction are connected to one horizontal scanning line HL. The horizontal scanning line HL is connected to a horizontal scanning shift register section Hreg. The horizontal scanning shift register section Hreg is configured to sequentially scan a plurality of horizontal scanning lines HL arranged in the row direction and select pixels in the row direction using the input signal Hin and the clock signal φtLt+φh.

Vertical switch MOSQ of multiple pixels arranged in row direction
The gate electrodes of v (Qvl and Qv2, respectively) are connected to one vertical scanning line VL. One end of the vertical scanning line VL is connected to a vertical scanning shift register section VrB with an interlaced scanning control section INT interposed therebetween. The vertical scanning shift register section Vreg performs interlaced scanning control of selection signals R11R21, . Department INT
is configured to output to .

The interlace scan control unit INT switches the switch MOS Q Fe or QF using the field selection signal Fe or FO.
The driving MOS Qd that transmits the selection signal R is selected. A boosting capacitor is provided between the gate electrode of the driving MOSQd and one semiconductor region (vertical scanning line VL). Drive MOS
Vertical scanning signal φ3 or φ is applied to the other semiconductor region of Qd.
, is applied. In other words, the vertical scanning signal φ3 or φ
4 is applied to the vertical scanning line VL by the driving MOS Qd based on the selection signal R. The driving MO3Qd can apply the vertical scanning signal φ3 or φ4 to the vertical scanning line VL without causing a voltage drop corresponding to the threshold voltage due to the boosting capacitor.

This interlaced scanning control unit INT is configured to be able to perform two-line interval readout and interlaced scanning. That is, first, the interlaced scanning control unit INT selects two adjacent vertical scanning lines VL (for example, VLI, VL2, V
L3 and VL4). Next, the interlaced scan control unit INT selects 1 by using another field selection signal F.
Two vertical scanning lines VL of even field B shifted by a row
(For example, VL2 and VL3, VL4 and VL5).

The other end of the vertical scanning line VL is connected to the gate electrodes of output control MOS QSye, QScy, QSw, and QSg of the output circuit OUT. The output control MOSQS connects one end of the output signal line HS and the output line SY for each color of the output circuit OUT.
e, SCy, SW, and SG.

The output signal line HS is connected to the other semiconductor region (drain region) of the horizontal switch MOSQh of the plurality of solid-state image sensors arranged in the row direction. The other end of the output signal line H8 is the reset MO of the horizontal retrace period reset section RES.
It is connected to a reset output line (video signal line) Vr with SQr interposed therebetween. The gate electrode of the reset MOSQr is connected to and controlled by the reset signal line RP. The horizontal retrace period reset unit RES is configured to reset false signals accumulated during the horizontal scanning period.

Next, the basic device structure of the TSL type solid-state image sensor CI-II will be explained using FIGS. 3 to 6. FIG. 3 is a plan view of the main part showing the solid-state image sensor of the light receiving section SA, and FIG. 4 is a plan view of the main part showing the solid-state image sensor of the optical black part OB. Figure 5 is a sectional view taken along the section line ■-■ in Figure 3, and Figure 6 is the VI in Figure 3.
It is a sectional view taken along the -vf cutting line.

As shown in FIGS. 3 to 6, each pixel in the light receiving section and the optical black section OB basically has the same structure.

Each of the solid-state image sensors of the light receiving section SA and the optical black section OB is located in a well region W provided in the semiconductor substrate SUB.
It is formed on the main surface of the ELL, and its periphery is defined by the element isolation insulating film LOG.

The semiconductor substrate SUB is made of N-type single crystal silicon. The well region WELL is of P type and mainly forms an N channel MOSFET. Note that when the well region WELL is not provided, a P-type semiconductor substrate SUB is used.

The element isolation insulating film LOG is made of a silicon oxide film formed by selectively thermally oxidizing the main surface of the well region WELL. The element isolation insulating film LOG is shown in Figures 3 and 4.
As shown in the figure, the pixel forming area is configured in a U-shape. Specifically, in the element isolation insulating film LOG, the area of the horizontal switch MOSQh formation region is small, and the area of the vertical switch MOSQv formation region is small in order to increase the aperture area (aperture ratio) of the photoelectric conversion element PD. It is configured in a U-shape so that it is large.

The horizontal switch MOSQh of the pixel is shown in FIGS. 3 to 6,
As shown in FIG. 7 (a plan view of main parts in a predetermined manufacturing process), mainly the well region WELL, the gate insulating film,
It is composed of a pair of N° type semiconductor regions (N+) that are gate electrodes, source regions, or drain regions.

The gate insulating film is, for example, a silicon oxide film formed by oxidizing the main surface of the well region WELL region.
It is formed with a film thickness of about 500 [people].

The gate electrode is formed of a gate electrode material such as polycrystalline silicon film (semiconductor film) P-8i. Polycrystalline = 11- Silicon film P-8i is, for example, 3000-4000
[Form the film with a thickness similar to that of a human body.] In addition, the gate electrode is made of a high melting point metal (Mo, Ti, Ta, W) film or a high melting point metal silicide (MoSi, TiSi2.TaSi2.W).
It may be formed of a Si2) film or a polycrystalline silicon film and a composite film thereof.

The semiconductor region N' is formed by introducing N-type impurities into the main surface portions of the well regions WEI, L by ion implantation using the gate electrode as a mask, and by stretching and diffusing the impurities.

The semiconductor region N1, which is the drain region of the horizontal switch MOSQh, is formed on the main surface of a P'' type semiconductor region (P+) having a higher impurity concentration than the well region WELL. The semiconductor region P' is diffused to the channel forming region of the horizontal switch MOSQh.

This semiconductor region P+ is configured to increase the threshold voltage of the horizontal switch MOSQh.

In other words, the semiconductor region P''' is configured to reduce the movement of electrons that would cause blooming from the photoelectric conversion element PD side to the output signal line H8.

Vertical switch M OS Q v 1 is horizontal switch M
Substantially similar to OSQh, mainly the well region WELL
, a gate insulating film, a gate electrode, and a pair of semiconductor regions N+, which are a source region or a drain region.

Vertical switch M OS Q v 2 is horizontal switch M
Substantially similar to OSQh, mainly the well region WELL
, a gate insulating film, a gate electrode, and a pair of semiconductor regions N+, which are a source region or a drain region.

The gate electrodes of the vertical switches MOSQvl and Qv2 are formed in the same manufacturing process as the gate electrode of the horizontal switch MOSQh. Vertical switch M OS Q
Each of the gate electrodes v1 and Qv2 extends in the row direction across the center of the photodiode formation region (the photodiode is the light receiving section), and is integrally (commonly) configured.

Further, each gate electrode of the vertical switches M OS Qv1 and Qv2 is connected to a vertical scanning line VL extending in the row direction.
It is integrated with. In other words, the vertical scanning line ■L is
It is configured to extend substantially in the upper center of the solid-state image sensor in the row direction. In reality, the vertical scanning line VL is located above the photoelectric conversion element PD, specifically, the photoelectric conversion element PDI
and the photoelectric conversion element PD2 (in the vicinity of each of the photoelectric conversion elements PDI and PD2 in the solid-state image sensor).

One semiconductor region N′ of the vertical switch MOS Q v 1 is the same as one semiconductor region N of the horizontal switch MOS Qh.
It is integrally configured (shared) with ゛. vertical switch M,
The other semiconductor region N" of the OS Q v 1 is integrally configured (shared) with the other semiconductor region N" of the vertical switch M OS Q v 2. In other words, the vertical switch M
Each of OSQvl and Qv2 has a common gate electrode,
and connected in series.

In particular, the photoelectric conversion element PDI is connected to the other semiconductor region N of the vertical switch M OS Q v 1, as shown in FIG.
It is constituted by a PN junction between the other semiconductor region N' of the vertical switch MOS Qv2 and the well region WELL. Note that a photoelectric conversion element (photodiode element) is also formed at the PN junction between one semiconductor region N' of the switch MOSQvl or one semiconductor region N' of the horizontal switch MOSQh and the well region WELL.
Since Qh is in the ON state for every horizontal scan (H), Qv
The information stored in the N area common to I and Qh is reset every H, and only IH contributes to the output, so it can be ignored.

For example, if a photodiode PD and
Even if the common N4 region of Qh has the same area, Qvl・Q
h common area can only store 21525 pieces of information compared to PD. The semiconductor region N+ constituting the photoelectric conversion element PDI has, for example, 1020 [atoms/
an 3], and the well region is formed with an impurity concentration of about W an 3].
ELL e.g. 101″~10″ [atoms/an3
It is formed with an impurity concentration of approximately .

The photoelectric conversion element PD2 connects one semiconductor region N' of the vertical switch MOSQv2 and the well region WELL.
N junction, one semiconductor region N′ of vertical switch MOS Q v 2, and P′ type half-center region (p′, ,
) and a PN junction. Semiconductor region P"
p.

-15= is formed by at least the semiconductor region N' and the well region WELL, as shown by dotted lines in FIGS. 3 to 5 and FIG. (along the semiconductor region N'). The semiconductor region P"po is a well region W
It has the same conductivity type as the ELL, and is formed with a higher impurity concentration, for example, about 101' [atoms/cm3]. The semiconductor region P″FD is the semiconductor region N4
Introducing N-type impurities to form (ion implantation or diffusion)
It can be formed by introducing P-type impurities (ion implantation or diffusion) before or after. In addition, the semiconductor region P″P
D may be formed in the same manufacturing process and with the same impurity concentration as the semiconductor region P1 formed on the horizontal switch MOSQh side, or may be formed under different conditions.

As described above, each of the photoelectric conversion elements PDI and PD2 is
They are connected via a vertical switch M OS Q v 2. In other words, in one solid-state image sensor, when photoelectrons are accumulated, the vertical switch MOSQv2 can be put into a non-operating state (OFF state), so each of the photoelectric conversion elements PDI and PD2 independently accumulates photoelectrons. can do.

As described above, in the solid-state imaging device, the solid-state imaging device having the photoelectric conversion elements PD1 and PD2 that independently accumulate photoelectrons is connected between one semiconductor region N' of the vertical switch MOSQ v 2 and the well region WELL (PN a semiconductor region p' at the junction); 1. By providing ,
The photoelectric conversion element PD2 can be configured with a PN junction with a higher impurity concentration than the photoelectric conversion element PDI. As shown in FIG. 8 (a photoelectric conversion characteristic diagram showing the relationship between the amount of incident light and the amount of signal current generated based on it), this photoelectric conversion element PD2 has a saturated capacity that is lower than the saturation point pds of the photoelectric conversion element PDI. (junction capacitance) increases saturation point pd
2 can be obtained. The saturation capacitance of the photoelectric conversion element PD2 does not change effectively by simply changing the area ratio with the photoelectric conversion element PDI, and as in the present invention, the saturation capacity per unit area can be increased by providing the semiconductor region P''. It cannot be effectively increased unless the photoelectric conversion characteristics are changed.

Specifically, for example, the saturation capacity of the photoelectric conversion element PDI is Cpdl, the saturation signal current 1pd at this time is 1, the saturation capacity of the photoelectric conversion element PD2 is Cpd2, the saturation signal current at this time is Ipd2, and the saturation signal current is Ipd2 is the following formula <1>
The saturation capacitance Cpd2 of the photoelectric conversion element PD2 is set so as to satisfy
Suppose that P is increased in the semiconductor region P''FD.

Ipd2 = 2・Ipd1...
<1> Furthermore, the sensitivity S1 of the photoelectric conversion element PDI and the sensitivity S2 of the FD2 are set as shown in the following equation <2> for simplification.

s = Sl = s2 ...〈2
> From the above formulas <1> and formulas <2>, the photoelectric conversion element PDI
The saturated light amount L1 of the photoelectric conversion element PD2 and the saturated light amount L2 of the photoelectric conversion element PD2 can be expressed as shown in the following equations <3> and <4>, respectively.

LL=Ipdl/S...<
3>L2 =Ipd2/S =2・Ll...<4
〉 Therefore, as shown in FIG.
2 are in the operating state (ON state), and the total signal current of 1 pd of the photoelectric conversion elements PDI and FD2 is read out, so that a photoelectric conversion characteristic is obtained in which the sensitivity is high when it is dark and the sensitivity is low when it is bright. Can be done. In other words, a knee point K can be formed in the photoelectric conversion characteristics. The solid-state imaging device configured in this way has a standard light amount set at or near the knee point K.
The standard light amount can be increased to improve the S/N ratio, and the dynamic range (especially between light amounts L1 and L2) can be improved.
can be improved.

As shown in detail in FIG. 9 (a plan view of the main part in a predetermined manufacturing process), the horizontal scanning line HL is formed between the solid-state image sensor forming regions (element isolation insulating film LOG) arranged in the row direction. It is configured to extend in the column direction. The horizontal scanning line HL is composed of a conductive layer above the polycrystalline silicon film P-8i, for example, the first aluminum film ALL. For example, the aluminum film ALL is 5000
It is formed with a film thickness of about [a person]. aluminum mA
-l saw Ll is an interlayer insulating film (
For example, the PSG film is provided on the IA.

The horizontal scanning line HL is connected to the gate electrode (polycrystalline silicon film P-8i) of the horizontal switch MOSQh through the connection hole C2 formed in the interlayer insulating film IA.

The intermediate conductive layer MLI or ML2 is connected to the semiconductor region N+, which is the drain region of the horizontal switch MOSQb, through the connection hole C1. Solid-state imaging device C of this embodiment
HI is composed of a color element (or may be a monochrome element), and the intermediate conductive layer MLI is made of yellow Ye.
, white W, and the intermediate conductive layer ML2 is provided with color filters of cyan Cy and green G.
A solid-state image sensor is provided with each color filter. Each of the intermediate conductive layers ML1 and ML2 is formed of the same conductive layer as the horizontal scanning line HL.

The intermediate conductive layer MLI includes the semiconductor region N+ of the horizontal switch MOSQh and the output signal line H8 extending substantially over the semiconductor region N+.
I, l-l53. It is configured to connect... The intermediate conductive layer MLI is mainly configured to reduce the step shape during the connection and improve the reliability of the connection. The intermediate conductive layer ML2 is a horizontal switch MOSQh
The semiconductor region N1 is connected to output signal lines H82, H84, . . . extending in a layer above a region different from that region. The intermediate conductive layer ML2 is mainly configured to improve the reliability of the connection and to connect the semiconductor region N'' in a different region and the output signal line HS.

Output signal lines H8I, H83, . . . extending in the row direction are connected to the intermediate conductive layer MLI between the solid-state imaging devices arranged in the column direction (inter-element isolation insulating film LOG). . The output signal line H8 is connected to a conductive layer above the aluminum ALL, for example, a second layer of aluminum film A.
It consists of L2.

The aluminum film AL2 has a thickness of, for example, 8000 to 9000[
The thickness of the film is approximately the same as that of a human. The aluminum film AL2 is
An interlayer insulating film (for example, PS
G film) provided in IBI. The output signal line HS is connected to the intermediate conductive layer MLI through a connection hole C3 formed in the interlayer insulating film IB.

As shown in FIGS. 3 and 4, in the intermediate conductive layer ML2, there is formed a layer approximately at the center of the solid-state image sensors arranged in the column direction, and a layer overlapping the vertical scanning line VL in the row direction. Extending output signal lines H82, H84, . . . are connected. The output signal line HS is made of, for example, a second layer of aluminum film AL2. The output signal line HS is connected to the intermediate conductive layer ML2 through the connection hole C3. The output signal lines H82, H84, .
L and output signal lines H82, H84, . . . are overlapped.

In the optical black part OB region, as shown in FIG. 4, an interlayer insulating film (for example,
PSG film) A light shielding film SF is provided with an IC interposed therebetween. The light shielding film SF is formed of, for example, a third layer of aluminum film AL3. The aluminum film AL3 is, for example,
It is formed by vapor deposition or sputtering to a film thickness of about 10,000 mm.

Note that, in the above-mentioned TSL type solid-state imaging device, the present invention provides that one of the vertical switches M OS At the junction between the semiconductor region N' and the well region WELL, a semiconductor region N having the same conductivity type as the semiconductor region N+ and having a higher impurity concentration than the semiconductor region N+ is provided.
"" may be provided.

Note that, in the above-mentioned TSL type solid-state imaging device, the present invention provides that the other of the vertical switches M OS A semiconductor region P''po may be provided at the junction between the semiconductor region N'' and the well region WELL.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

The present invention is not limited to the above-mentioned TSL type solid-state imaging device, but can be applied to a solid-state imaging device having a solid-state imaging device formed of a switch MOS and a plurality of photoelectric conversion elements each capable of independently accumulating photoelectrons. can. For example, in the embodiment described above, the present invention provides a single horizontal switch MOS
and one vertical switch MOS, and includes two photoelectric conversion elements each formed by a source region, a drain region, and a well region of the vertical switch MOS. It can be applied to

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a solid-state imaging device having a solid-state imaging device formed of a switch MOS and two photoelectric conversion elements each capable of independently accumulating photoelectrons, it is possible to improve the S/N ratio and the dynamic range.

[Brief explanation of drawings]

Fig. 1 is a schematic configuration diagram showing a TSL type solid-state imaging device which is an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the solid-state imaging device shown in Fig. 1, and Fig. 3 is a light receiving device. Figure 4 is a plan view of the main part showing the solid-state imaging device in the optical black part, Figure 5 is a cross section taken along the section line ■-■ in Figure 3. 6 is a sectional view taken along the line VI-VI in FIG. 3, FIG. 7 is a plan view of the main part of the solid-state imaging device in a predetermined manufacturing process, and FIG. 8 is a cross-sectional view taken along the line VI-VI in FIG. Photoelectric conversion characteristic diagram of the solid-state imaging device of the device. FIG. 9 is a plan view of a main part of the solid-state imaging device in a predetermined manufacturing process. In the figure, CHI... solid-state imaging device (solid-state imaging chip),
ARR...Photodiode array, SA...Light receiving section, OB...Optical black section1. INT...
Interlace scan control section, Vreg...shift register section for vertical scanning, Hreg...shift register section for horizontal scanning, OUT...output circuit, VL...vertical scanning line, ML...horizontal scanning line , H8...output signal line, Qh
...Horizontal switch MOS, Qv...Vertical switch M
OS, PD...photoelectric conversion element, ML...intermediate conductive layer, SF...light shielding film, P+FD...semiconductor region. 5A... Light receiving part OB... Optical black part Vreg... Vertical scanning shift register part Hreq.
...Horizontal scanning shift register section RES...Horizontal retrace period reset section INT...Interlace scan control section OUT...Output circuit CHI...Solid-state imaging chip.

Claims (1)

[Scope of Claims] 1. A solid-state imaging device having a solid-state imaging device composed of a switch MOS, and a first photoelectric conversion element and a second photoelectric conversion element each capable of independently accumulating photoelectrons, wherein the first
A solid-state imaging device characterized in that a photoelectric conversion element is formed of a PN junction with a higher impurity concentration than a second photoelectric conversion element. 2. Claim 1, characterized in that the first photoelectric conversion element and the second photoelectric conversion element of the solid-state image sensor are connected through another switch MOS different from the switch MOS. The solid-state imaging device described in . 3. The first photoelectric conversion element is constructed by interposing a P-type or N-type semiconductor region with a high impurity concentration at least partially between the PN junctions. Or the solid-state imaging device according to item 2. 4. The solid-state imaging device according to claim 3, wherein the semiconductor region is configured to change photoelectric conversion characteristics per unit area of the first photoelectric conversion element. 5. The solid-state imaging device according to claim 3 or 4, wherein the semiconductor region has a higher impurity concentration than the substrate or well region.