JPS63266841A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS63266841A
JPS63266841A JP62099680A JP9968087A JPS63266841A JP S63266841 A JPS63266841 A JP S63266841A JP 62099680 A JP62099680 A JP 62099680A JP 9968087 A JP9968087 A JP 9968087A JP S63266841 A JPS63266841 A JP S63266841A
Authority
JP
Japan
Prior art keywords
wirings
phosphorus
copper
semiconductor device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62099680A
Other languages
Japanese (ja)
Other versions
JP2515324B2 (en
Inventor
Michitoshi Sera
世良　通利
Kazuhiro Yamamori
山森　和弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62099680A priority Critical patent/JP2515324B2/en
Publication of JPS63266841A publication Critical patent/JPS63266841A/en
Application granted granted Critical
Publication of JP2515324B2 publication Critical patent/JP2515324B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To improve temperature resistance cycle characteristic by applying phosphorus-deoxydized copper to fine metal wirings for connecting electrodes formed at a semiconductor chip to external leads in a bonding step to use the wirings to be hardly disconnected. CONSTITUTION:Metal frames disposed oppositely are divided at an equal interval to form units, lead terminals 1 which are started from the frames are provided, and a bed 2 is extended by posts 3 to be engaged with the frames at the center of each unit. In the bed 2 the electrodes and lead terminals 1 of a semiconductor element 4 are connected therebetween by fine metal wirings 5 after the element 4 is mounted by a mounter to be electrically conducted. Phosphorus-deoxydized copper which contains approx. 200ppm of phosphorus is applied to the wirings 5. After the wirings 5 made of the copper are bonded to the terminal 1 in a bonding step, the element 4 is buried by covering it with a sealing resin layer 6 by a transfer molding method. Thus, even if a ball bonding is executed, it can prevent crystal grains at a ball neck from roughly increasing and from breaking, thereby manufacturing an inexpensive semiconductor device having high reliability.

Description

【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は１５〜６０μｍの極細銅細線を使用し、かつエ
ポキシ樹脂により封止する半導体装置の改良に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to an improvement in a semiconductor device that uses an ultrafine copper wire of 15 to 60 μm and is sealed with an epoxy resin.

（従来の技術） いわゆるリードフレームを利用する半導体素子の組立方
式ではこの半導体素子に形成する電極と、リードフレー
ムに設けるアウターリード間を金属細線でポールボンデ
ィング技術によって電気的に接続後、トランスファーモ
ールド法によって樹脂封止する手法が採用されているの
は良く知られている通りである。(Prior art) In a semiconductor device assembly method that uses a so-called lead frame, the electrodes formed on the semiconductor device and the outer leads provided on the lead frame are electrically connected using pole bonding technology using thin metal wires, and then transfer molding is performed. It is well known that a method of resin sealing is used.

この金属細線としては一般的に金が適用されていたが、
経済的な観点からＡｌ１の使用が始まり、更に前記半導
体素子の電極として適用しているＡＱもしくは合金層に
対してＣｕ細線は十分なりｏｎｄａｂｊ　］　１−ｔｙ
が存在することを確認の上で、実用化の域に到達してい
るのが現状であり、この為当然ながらＣｕ細線の酸化防
止に留意している。Gold was generally used as this thin metal wire, but
The use of Al1 began from an economical point of view, and furthermore, Cu thin wires are sufficient for the AQ or alloy layer applied as the electrode of the semiconductor element.
At present, we have reached the stage of practical application after confirming the existence of Cu wires, and for this reason, we naturally pay attention to the prevention of oxidation of Cu thin wires.

このＣｕ１Ｂ線の採用は樹脂封止型半導体装置における
低コスト達成に貢献しているものの、最近の厳しいＣ，
Ｄ（Ｃｏｓｔ　Ｄｏｗｎ）に応じて、より安価なＣｕ細
線の採用が検討されている。しかし、このＣｕ細線は従
来適用していたＡｕ細線に比較してかなり硬いのでボン
ディング工程で必要とする荷重も当然大きくなる。従っ
て、このＣｕ細線をボンディングによって接続する電極
に隣接する絶縁物層もしくは半導体基板にクラックが発
生し、この対策としては純度を高めて硬さをＡｕ細線に
できるだけ近づける方法が採用されている。即ち、純度
が９９．９９９〜９９．９９９９％の無酸素銅細線が開
発されている。Although the adoption of this Cu1B wire has contributed to achieving low costs in resin-sealed semiconductor devices, the recent strict C,
Depending on D (Cost Down), adoption of cheaper Cu thin wire is being considered. However, since this Cu thin wire is considerably harder than the conventionally used Au thin wire, the load required in the bonding process is naturally increased. Therefore, cracks occur in the insulating layer or the semiconductor substrate adjacent to the electrode to which this thin Cu wire is connected by bonding, and as a countermeasure to this problem, a method has been adopted to increase the purity and make the hardness as close as possible to that of the thin Au wire. That is, oxygen-free copper thin wires with a purity of 99.999 to 99.9999% have been developed.

一方、封止樹脂としては高熱伝導性ならびに高熱膨張性
が必要となり、しかも機械的強度を保持するためにフィ
ラーとしてシリカを７０重量％含有させているが、この
伝導性と膨張性を両立させるのが難しい。そこで半導体
装置の特徴を生かすために熱放散性が求められるバイポ
ーラ型素子やパワー素子等では結晶性シリカをフィラー
として使用する封止樹脂を使用して熱膨張特性を多少犠
牲にしており、逆の場合には溶融性シリカをフィラーと
した封止樹脂を利用している。On the other hand, the sealing resin needs to have high thermal conductivity and high thermal expansion, and it contains 70% by weight of silica as a filler to maintain mechanical strength. is difficult. Therefore, in bipolar type devices, power devices, etc. that require heat dissipation properties to take advantage of the characteristics of semiconductor devices, sealing resins that use crystalline silica as a filler are used, sacrificing thermal expansion properties to some extent, and vice versa. In some cases, a sealing resin containing fusible silica as a filler is used.

（発明が解決しようとする問題点） このような高純度無酸素銅細線を使用したボンディング
工程及び樹脂封止工程を終えた樹脂封止型半導体装置は
、耐温度サイクル特性に劣る難点がある。この特性試験
とは樹脂封止型半導体装置を一５５℃に３０分像保持後
温に５分程度置き次に１５０℃に３０分間放置してから
再び常温に約５分間おく。(Problems to be Solved by the Invention) A resin-sealed semiconductor device that has undergone a bonding process and a resin-sealing process using such a high-purity oxygen-free thin copper wire has a disadvantage of poor temperature cycle resistance. In this characteristic test, a resin-sealed semiconductor device is kept at -55° C. for 30 minutes, then left at room temperature for about 5 minutes, then left at 150° C. for 30 minutes, and then returned to room temperature for about 5 minutes.

これを１サイクルとして１０００〜２０００回程度の繰
返しで異常が発生するのが通常であるが、前述の場合は
これに到達なかった。この封止樹脂として結晶性シリカ
をフィラーとして使用したものは熱伝導率λ＝３５×１
Ｏ−４ＣａＱ／■・ＳｅＣ・℃、熱膨張率α、＝２．８
　Ｘ　１０−’　１／℃、　　α２＝　７．ＯＸ　１０
−’　１／℃　　を示し、これを前記樹脂封止型半導体
装置に採用すると耐温度サイクル特性が顕著に表われて
高出力バイポーラＩＣやパワーＩＣへの銅細線適用に障
害となっていた。Normally, an abnormality occurs after about 1,000 to 2,000 repetitions of this cycle, but this did not occur in the case described above. The sealing resin that uses crystalline silica as a filler has a thermal conductivity of λ=35×1
O-4CaQ/■・SeC・℃, coefficient of thermal expansion α, = 2.8
X 10-' 1/℃, α2=7. OX10
-' 1/°C, and when it is used in the resin-sealed semiconductor device, its temperature cycle resistance becomes remarkable, which has been an obstacle to the application of thin copper wires to high-output bipolar ICs and power ICs.

本発明は上記難点を除去する新規な樹脂封止型半導体装
置に関し、特に断線不良を起し難い金属細線を使用し、
なお耐温度サイクル特性を改善するものである。The present invention relates to a novel resin-sealed semiconductor device that eliminates the above-mentioned drawbacks, and uses thin metal wires that are particularly resistant to disconnection defects.
Note that this improves temperature cycle resistance.

〔発明の構成〕[Structure of the invention]

（問題点を解決するための手段） この目的を達成するのに本発明は半導体チップに形成す
る電極と外部リード間をボンディング工程で接続する金
属細線にリン脱酸銅を適用する。(Means for Solving the Problems) To achieve this object, the present invention applies phosphorus-deoxidized copper to thin metal wires that connect electrodes formed on semiconductor chips and external leads in a bonding process.

（作用） 本発明を完成するに先立ち、前記高純度無酸素鋼細線を
使用して得られた樹脂封止型半導体装置のうち耐温度サ
イクル特性試験によって不良となったものを詳細に調査
した結果、■不良品はすべてＣｕ細線の断線不良であり
、■破断箇所は主として半導体チップに設けた電極に熱
圧着で固着したボールのすぐ上のいわゆるボールネック
部であり、■この部分はボンディング工程に必要なボー
ルを形成する際にＣｕｘｅ細線への附加する熱負荷によ
って結晶粒が阻大化して強度が低下するためと判断した
。(Function) Prior to completing the present invention, we conducted a detailed investigation of resin-encapsulated semiconductor devices obtained using the above-mentioned high-purity oxygen-free steel wire that were found to be defective in a temperature cycle characteristic test. ,■ All of the defective products are due to disconnection defects in the Cu thin wire, and ■The breakage point is mainly at the so-called ball neck area just above the ball that is fixed by thermocompression to the electrode provided on the semiconductor chip. It was determined that this was due to the thermal load applied to the Cuxe thin wire when forming the necessary balls, which enlarged the crystal grains and reduced the strength.

この分析結果を基にして実験を重ねた結果、■無酸素銅
細線を高純度にすればする程（例えば９９．９％→９９
．９９９％→９９．９９９９％）、ボンディング用ボー
ル形成時における熱の影響によって結晶粒の粗大化が激
しくなって再結晶領域も大きくなる。As a result of repeated experiments based on this analysis result, it was found that ■ The higher the purity of the oxygen-free copper thin wire (for example, 99.9% → 99%
．． (999% → 99.9999%), the crystal grains become coarser due to the influence of heat during the formation of the bonding ball, and the recrystallized region also becomes larger.

■一方高純度無酸素銅に代えて２００ｐｐｍ程度のリン
を含むリン脱酸銅細線を採用したところ、前記熱負荷に
伴う結晶粒の粗大化がかなり抑えられ、従って再結晶領
域が小さくなることが確認された。■On the other hand, when a phosphorus-deoxidized thin copper wire containing about 200 ppm of phosphorus was used instead of high-purity oxygen-free copper, the coarsening of crystal grains caused by the heat load was considerably suppressed, and the recrystallization area became smaller. confirmed.

前記不良品分析を実施するうちに、前記ポールネック部
の破断以外に、リードフレームのアウタ一リードとの熱
圧着部に近い細線にも破断現象がみられ、これについて
も■無酸素銅細線を高純度化するにつれてこの熱圧着部
に近い位置の破断現象が増大し、■リン脱酸銅細線は高
温時の引張強度が無酸素鋼細線より遥かに高くて、前記
破断現象は全く発生しない事実が判明した。While conducting the above defective product analysis, in addition to the breakage at the pole neck part, a breakage phenomenon was also observed in the thin wire near the thermocompression bonded part with the outer lead of the lead frame. As the purity increases, the occurrence of breakage near the thermocompression bond increases, and the fact that the tensile strength of phosphorus-deoxidized copper wire at high temperatures is much higher than that of oxygen-free steel wire, and the above-mentioned breakage phenomenon does not occur at all. There was found.

以上の知見からリン脱酸銅細線はもともと結晶組織が小
さく、ボール形成時の熱の影響による結晶粒組織の粗大
化をリンが抑え、かつ粒界強化元素の役割りを果して、
温度サイクルによるポールネック部等の破断を防止して
いると推定できる。From the above findings, the phosphorus-deoxidized copper fine wire originally has a small crystal structure, and phosphorus suppresses the coarsening of the crystal grain structure due to the influence of heat during ball formation, and also plays the role of a grain boundary strengthening element.
It can be assumed that this prevents the pole neck from breaking due to temperature cycles.

尚この考案に当っては結晶化シリカをフィラーとして採
用したエポキシ樹脂を封止樹脂として使用し、その含有
量は前述のように７０重量％である。In this invention, an epoxy resin containing crystallized silica as a filler is used as a sealing resin, and its content is 70% by weight as described above.

本発明は、上記考察に基づいてリン脱酸銅細線を樹脂封
止型半導体装置に採用する。Based on the above considerations, the present invention employs a phosphorus-deoxidized thin copper wire in a resin-sealed semiconductor device.

（実施例） 図にはリン脱酸銅細線を適用した樹脂封止型半導体装置
の一部切欠斜視図を示した。この図から詳細は不明であ
るが、リードフレームとしてはＤＩＰタイプ用もしくは
いわゆる合掌型フレームを使用する。(Example) The figure shows a partially cutaway perspective view of a resin-sealed semiconductor device to which a phosphorus-deoxidized thin copper wire is applied. Although the details are unclear from this figure, a DIP type or so-called gassho type frame is used as the lead frame.

即ち相対向して配置する金属製枠体（図示せず）を等間
隔で区分して、単位体を構成し、この単位体の中心に向
けてこの金属枠体を起点とするリード端子１．・・・を
設け、更にこの各単位体の中心にはベッド部２を金属製
枠体に係止する支柱３によって張架するのが通常である
。このベッド部２には半導体素子４をマウンター等によ
ってマウント後この半導体素子４に形成する電極（図示
せず）とリード端子］・・・間を金属細線５によって接
続して電気的な導通を図る。That is, metal frames (not shown) arranged facing each other are divided at equal intervals to form a unit, and lead terminals 1. . . . and furthermore, the bed section 2 is usually suspended at the center of each unit by a support 3 that locks it to a metal frame. A semiconductor element 4 is mounted on this bed part 2 using a mounter or the like, and then electrodes (not shown) and lead terminals formed on the semiconductor element 4 are connected by thin metal wires 5 to establish electrical continuity. .

この金属細線５としては前述のように約２００ｐｐｍの
リンを含有するリン脱酸銅製のものを適用するのは前述
の通りであり、又リード端子１・・・の一部は図のよう
に外部リードとして使用する。この外部リードは通常の
ようにモールド工程等を終えてからいわゆるＣｕｔ　ａ
ｎｄ　Ｂｅｎｄ工程によって折曲げ成形を施して使用機
器への着脱を可能とする。この金属細線５・・を固着す
る電極は図で半導体素子４の外周附近に画かれているが
、これはパッド部を想定したものであり、実際には図示
しない不純物領域に隣接して設ける電極に連続しかつこ
の半導体基板表面を被覆する絶縁物層に延長する配線に
金属細線５をボンディングする場合もある。このボンデ
ィング工程はいわゆるポールボンディングであり、その
加熱手段としては電気１〜−チを利用する場合と、酸水
素焔を利用する場合があり、又超音波ボンディングも適
用可能である。As described above, this fine metal wire 5 is made of phosphorus-deoxidized copper containing about 200 ppm of phosphorus, and a part of the lead terminal 1 is externally connected as shown in the figure. Use as a lead. This external lead is so-called "Cut a" after finishing the molding process etc. as usual.
By performing bending and forming in the nd bend process, it is possible to attach and detach it to the equipment in use. The electrodes for fixing these thin metal wires 5 are drawn near the outer periphery of the semiconductor element 4 in the figure, but this is assumed to be a pad part, and in reality it is an electrode provided adjacent to an impurity region (not shown). In some cases, the thin metal wire 5 is bonded to a wiring that is continuous with the semiconductor substrate and extends to an insulating layer covering the surface of the semiconductor substrate. This bonding process is so-called pole bonding, and the heating means may be electric or oxyhydrogen flame, and ultrasonic bonding is also applicable.

ボンディング工程によって図のようにリン脱酸銅からな
る金属細線５・・・をリード端子１・・に固着後トラン
スファーモールド法によって封止樹脂層６を常法に従っ
て被覆して、半導体素子４を埋設する。As shown in the figure, thin metal wires 5 made of phosphorus-deoxidized copper are fixed to lead terminals 1 through a bonding process, and then a sealing resin layer 6 is coated in a conventional manner by transfer molding, and semiconductor elements 4 are buried. do.

この封止樹脂としては熱伝導率λ＝３７Ｘ］０−４ｃａ
Ｑ／ｃｓｎ−ｓｅｃ・’Ｃ５熱膨張率係数ａ　ｔ　＝　
２．８　Ｘ　１．０”　］　／℃、α２＝　７．Ｏｘ　
１０−’　１／℃を示す結晶性シリカをフィラーとして
７０重量％含有するエポキシ樹脂を使用する。Thermal conductivity λ=37X]0-4ca for this sealing resin
Q/csn-sec・'C5 coefficient of thermal expansion a t =
2.8 x 1.0” /℃, α2= 7.Ox
An epoxy resin containing 70% by weight of crystalline silica as a filler having a temperature of 10-' 1/°C is used.

この熱膨張係数α１α、は横軸に温度、縦軸に伸びを採
った場合ガラス転移点Ｔｇまでの値をα、それ以後をα
２とし、半導体用としての上限はα１で３．５　Ｘ　１
０−５］／℃、α２＝　９．ＯＸ　１０−５１．／℃で
ある。このようにして樹脂封止型半導体装置を完成する
。This coefficient of thermal expansion α1α, when temperature is plotted on the horizontal axis and elongation is plotted on the vertical axis, is α for the value up to the glass transition point Tg, and α for the value after that.
2, and the upper limit for semiconductor use is α1 of 3.5 x 1
0-5]/℃, α2=9. OX 10-51. /℃. In this way, a resin-sealed semiconductor device is completed.

〔発明の効果〕〔Effect of the invention〕

（以下余白） −８・ 第１表に示すようにリン脱酸銅細線を使用してポールボ
ンディングを実施しても、ポールネック部等の結晶粒阻
大化を防止でき、かつ高温時の細線強度も高いので温度
サイクル試験においても外部リード側及びポールネック
部での破断が発生せず信頼性の高い安価な半導体装置が
製造できる。(Left below) -8. As shown in Table 1, even if pole bonding is performed using phosphorus-deoxidized thin copper wire, it is possible to prevent crystal grain enlargement at the pole neck, etc., and the thin wire at high temperatures Since the strength is high, no breakage occurs on the external lead side or the pole neck part even in a temperature cycle test, making it possible to manufacture a highly reliable and inexpensive semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明に係る樹脂封止型半導体装置の一部切欠斜視
図である。The figure is a partially cutaway perspective view of a resin-sealed semiconductor device according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 外部リードならびに素子電極間を金属細線で接続する半
導体素子を封止樹脂層に埋設する半導体装置において、
この金属細線にリン脱酸銅を適用することを特徴とする
樹脂封止型半導体装置。In a semiconductor device in which a semiconductor element is embedded in a sealing resin layer with external leads and element electrodes connected by thin metal wires,
A resin-sealed semiconductor device characterized by applying phosphorus-deoxidized copper to the thin metal wire.
JP62099680A 1987-04-24 1987-04-24 Resin-sealed semiconductor device Expired - Lifetime JP2515324B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62099680A JP2515324B2 (en) 1987-04-24 1987-04-24 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62099680A JP2515324B2 (en) 1987-04-24 1987-04-24 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS63266841A true JPS63266841A (en) 1988-11-02
JP2515324B2 JP2515324B2 (en) 1996-07-10

Family

ID=14253746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62099680A Expired - Lifetime JP2515324B2 (en) 1987-04-24 1987-04-24 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP2515324B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4482605B1 (en) * 2009-01-23 2010-06-16 田中電子工業株式会社 High purity Cu bonding wire

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4482605B1 (en) * 2009-01-23 2010-06-16 田中電子工業株式会社 High purity Cu bonding wire
JP2010171235A (en) * 2009-01-23 2010-08-05 Tanaka Electronics Ind Co Ltd HIGH-PURITY Cu BONDING WIRE

Also Published As

Publication number Publication date
JP2515324B2 (en) 1996-07-10

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