JPS63265459A - Semiconductor device - Google Patents

Abstract

PURPOSE:To allow a power source noise Vn which is mixed in through a substrate to be shielded by a region with opposite conductivity type grounded region and prevent its noise from reaching a signal line by earthing one region of one electrode out of two electrodes as well as a region with reverse conductivity type and by using the other electrode as the signal conductor. CONSTITUTION:The title device has a semiconductor substrate 1 of one conductivity, a region 19 with opposite conductivity type which is formed on the substrate 1 and grounded, a thick oxide film 2 which is formed on the region 19, a first electrode 3 formed on the film 2, a thin oxide film 4 which is formed on the electrode 3, a second electrode 5 which is formed on the film 4, and the electrode 5 is grounded and the other one 3 is used as a signal conductor. A power source noise Vn is attenuated by the capacity value C3 of junction capacitor 20 and the resistance value R of resistance 21 by mounting P well 18 between the thick oxide film 2 and the substrate and they by earthing its well in this way. Then, mixing to the signal conductor of the power source noise is drastically limited.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device incorporating a capacitance.

2. Description of the Related Art In recent years, MO8 integrated circuits have increasingly incorporated capacitors in combination with analog switches, as seen in switched capacitor filters and the like.

An example of a conventional semiconductor device with a built-in capacitor will be described below with reference to the drawings.

3 and 4 are equivalent circuits of an output buffer including a conventional capacitor structure and an analog switch using the capacitor. In Figure 3, 1 is an N-type silicon substrate connected to a power supply, 2 is a thick oxide film, 3 is a first electrode formed on the thick oxide film, and 4 is a thin layer formed on the first electrode. An oxide film, 5 is a second electrode formed on the thin oxide film, and 6 is an equivalent capacitor formed between the first electrode 3 and the second electrode 5, which is assumed to be C+. 7
is an equivalent parasitic capacitor formed between the first electrode 3 and the N-type silicon substrate 1, and is denoted by C2. 8 is a signal line terminal, 9 is a power supply terminal, and 10 is a ground terminal. In FIG. 4, 11 is a signal input terminal, 12 is an analog switch control terminal, 13 is an inverter, 14 is an N-channel transistor, 15 is a P-channel transistor, and inverter 1
3°N channel transistor 14. The P-channel transistor 15 constitutes an analog switch. 16 is an output buffer composed of an operational amplifier, 17 is an output terminal,
These are integrated within a semiconductor chip.

The operation of the semiconductor device configured as described above will be described below.

First, in FIG. 4, while a signal V is input to the signal input terminal 11 and a high-level DC voltage is applied to the analog switch control terminal 12, the N-channel transistor 1
4 and P-channel transistor 15 are both turned on, and the signal v
1 is charged into the capacitor C1 and the parasitic capacitor C2. The voltage charged in the capacitor C+ and the parasitic capacitor C2 is transmitted to the output terminal 17 through the output buffer 16. When the DC voltage applied to the analog switch control terminal 12 becomes low level, both the P-channel transistor 15 and the N-channel transistor 14 are turned off, but the voltage stored in the capacitor CI and the parasitic capacitor C2 is output.

In the cross-sectional view of FIG. 3, the thickness of the thin oxide film 4 is tl, and the dielectric constant is εsio! , where S is the opposing area of the first electrode 3 and the second electrode 5, it is the dielectric constant in the capacitance value of the capacitor CI. On the other hand, when the thickness of the thick oxide film 2 is t2, and the capacitance value of the parasitic capacitor C2 is t2=9000 A, the capacitance ratio of C and C2 is 9:1.゛Problems to be Solved by the Invention However, in the above configuration, when noise Vn enters the power supply, the noise divided by the capacitance C and the parasitic capacitance C2 mixes into the signal line terminal 8. become. In other words, there was a problem that C,:C2 was mixed. Generally, the signal from the output terminal 17 is multiplied by eight and used, which has the problem of increasing the signal size.

Means for Solving the Problems In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor substrate of one conductivity type connected to a power supply, a region of an opposite conductivity type formed on the same substrate and grounded, and a region of the opposite conductivity type formed on the same substrate and grounded. A thick oxide film formed on the region, a first electrode formed on the thick oxide film, a thin oxide film formed on the first electrode, and a first electrode formed on the thin oxide film. It has a configuration in which one electrode is grounded and the other electrode is used as a signal line.

Operation According to the above-described structure of the present invention, the power supply noise Vn mixed through the substrate is shielded by the grounded region of the opposite conductivity type, and does not reach the signal line.

Embodiment Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a capacitor structure of a semiconductor device according to a first embodiment of the present invention.

In FIG. 1, 18 is a P well, and 19 is a P/diffusion region for making an ohmic connection. 20 is the board 1
An equivalent junction capacitor (capacitance value C
3), 21 is the resistance (resistance value R) of the P well.

Regarding the semiconductor device configured as above, the following will be described in the first section.
The operation will be explained using FIG. First, FIG. 2 is an applied circuit that includes an equivalent circuit of the capacitor structure shown in FIG. 1, and is used for the same functional purpose as the applied circuit shown in FIG. 3. In both FIG. 1 and FIG. 2, explanations of the same numbers as in FIG. 3 and FIG. 4 showing the conventional example will be omitted. The power supply noise Vn is attenuated by the capacitance value C3 of the junction capacitor 20 and the resistance value R of the resistor 21, and the attenuated power supply noise becomes C
It is divided by I and 02 and mixed into the signal line. Now, C5=
Assuming 75pF, R=10, and Ω, the cutoff frequency f component is about IKHz, and the amount of attenuation due to C3,H is 20
eog j / IK Hz = 46 dB, and the power supply noise is significantly improved.

As described above, according to this embodiment, by providing the P-well between the thick oxide film and the substrate and grounding it, it is possible to significantly limit the ingress of power supply noise into the signal line. Also, the above is N
Although the configuration has been described using a substrate and a P-well, a P-substrate and N-well configuration may also be used.

Effects of the Invention As described above, the present invention provides a power source by forming a grounded region of the opposite conductivity type between a capacitor provided on a semiconductor substrate of one conductivity type and separated by a thick insulating film, and the same substrate. It is possible to significantly improve the ingress of noise into the signal line. By sandwiching the signal line between the grounded P-well and the grounded second electrode, it has the effect of shielding from external noise.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of an applied circuit including the same semiconductor device, FIG. 3 is a sectional view of a conventional semiconductor device, and FIG. 4 is an equivalent circuit diagram of an application circuit including the conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... Thick oxide film, 3... First electrode, 4... Thin electrode, 5... ...Second electrode, 18...
P well, 19. Old...P+ diffusion region. Name of agent: Patent attorney Toshio Nakao (1 person)

Claims (1)

[Claims] A semiconductor substrate of one conductivity type connected to a power supply, a region of an opposite conductivity type formed on the same substrate and grounded, a thick oxide film formed on the same region, and a first semiconductor substrate formed on the same oxide film. an electrode, a thin oxide film formed on the first electrode, and a second electrode formed on the thin oxide film;
A semiconductor device, wherein one of the electrodes and the region of the opposite conductivity type are grounded, and the other electrode is used as a signal line.