JPS63265452A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63265452A
JPS63265452A JP62330433A JP33043387A JPS63265452A JP S63265452 A JPS63265452 A JP S63265452A JP 62330433 A JP62330433 A JP 62330433A JP 33043387 A JP33043387 A JP 33043387A JP S63265452 A JPS63265452 A JP S63265452A
Authority
JP
Japan
Prior art keywords
die pad
resin
tie
semiconductor
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62330433A
Other languages
Japanese (ja)
Other versions
JP2607576B2 (en
Inventor
Yasuhiro Yamaji
泰弘 山地
Kenji Takahashi
健司 高橋
Seiichi Hirata
誠一 平田
Hisaharu Sakurai
桜井 寿春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62330433A priority Critical patent/JP2607576B2/en
Publication of JPS63265452A publication Critical patent/JPS63265452A/en
Application granted granted Critical
Publication of JP2607576B2 publication Critical patent/JP2607576B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To maintain favorably the reliability of moisture resistance even through mounting with solder is carried out by heating wholly after taking moisture absorption, thereby eliminating the crack development of inner resin during its mounting by providing more than one piece of bores or notches reaching tie-bars at the surface or the rear of mold resin. CONSTITUTION:Four corners of a plate-like die pad 2 are held by tie-bars 3 and a semiconductor element 3 is mounted on an upper plane of the die pad 2. The element 3 and lead 4 are bound by bonding wires 5. The element 3 and its surroundings sealed with rectangular mold resin 6 make up a semiconductor package P. Bores 6a reaching a tie-bar 2 are respectively arranged at four positions facing to the tie-bar 2 located on the diagonal in the rear of this resin 6. When a semiconductor device is mounted at a substrate and the like by exposing the entire package P to a high temperature of 200 deg.C or more, a moisture which exists in the interface between the element 3 and the die pad 2 and evaporates is discharged outside from the bores 6a through the tie- bars 1 connecting to the die pad 2.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は半導体装置、特に樹脂封止型で多数個のものを
同時に基板等に実装する表面実装用、更には半導体パッ
ケージの外形が大きく、かつ多ビンで薄型のものに適応
して最適な半導体装置に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to semiconductor devices, particularly resin-sealed type devices for surface mounting in which a large number of devices are simultaneously mounted on a substrate, etc., and furthermore, semiconductor packages. The present invention relates to a semiconductor device that is suitable for use in large external dimensions, multiple bins, and thinness.

(従来の技術) 従来、上記表面実装用樹脂封止型半導体装置は、第12
図乃至第14図に示すように、タイバー1により四隅(
場合によっては四辺又は二隅又は二辺)を支持した平板
状のダイパッド2の上面に半導体素子3を搭載し、この
半導体素子3とリード線4とをボンディングワイヤ5(
第14図)でボンディングした後、モールド樹脂6で樹
脂封止して半導体パッケージPを構成することが一般に
行われていた。
(Prior Art) Conventionally, the above-mentioned resin-sealed semiconductor device for surface mounting has a twelfth
As shown in Figs.
A semiconductor element 3 is mounted on the upper surface of a flat die pad 2 that supports four sides, two corners, or two sides depending on the case, and a bonding wire 5 (
After bonding as shown in FIG. 14), the semiconductor package P is generally configured by resin sealing with a molding resin 6.

この時のダイパッド2の隅部とタイバー1の先端とのタ
イバー長さLは半導体パッケージPの外形寸法により決
まる値を有していた。
At this time, the tie bar length L between the corner of the die pad 2 and the tip of the tie bar 1 had a value determined by the external dimensions of the semiconductor package P.

しかしながら、最近の高密度実装化に伴い、FP(フラ
ット・パッケージ) 、PLCC(プラスチック・リー
ド付チップφキャリヤ)、5OJ(スモール・アウトラ
イン・J−ベンド・パッケージ)等の表面実装用薄型樹
脂封止パッケージの適用が進み、こうした半導体パッケ
ージの基板への表面実装を行う際に、個々のリード部の
みの半田付加熱とは異なり、半導体パッケージの全体が
200℃以上の高温にさらされる方式が採用されるに至
ってきている。
However, with the recent trend toward high-density packaging, thin resin sealing for surface mounting such as FP (flat package), PLCC (plastic leaded chip carrier), 5OJ (small outline J-bend package), etc. As the application of semiconductor packages progresses, when surface mounting these semiconductor packages on substrates, a method is being adopted in which the entire semiconductor package is exposed to high temperatures of 200°C or more, unlike soldering heat applied to only individual leads. It has come to the point where

このため、モールド樹脂6の内部に吸湿された水分が、
半導体素子3とモールド樹脂6との界面やダイパッド2
とモールド樹脂6との界面で爆発的に蒸気化しようとし
、更に両界面に高圧が加わって、第14図に示すように
、ダイパッド2の周囲の下面のモールド樹脂6内や半導
体素子3の周囲の上面のモールド樹脂6内等(図示せず
)にクラック7が発生してしまうことがあるという問題
点があった。
Therefore, the moisture absorbed inside the mold resin 6 is
The interface between the semiconductor element 3 and the mold resin 6 and the die pad 2
At the interface between the die pad 2 and the mold resin 6, explosive vaporization occurs, and high pressure is applied to both interfaces, causing the inside of the mold resin 6 on the lower surface around the die pad 2 and around the semiconductor element 3 to evaporate, as shown in FIG. There is a problem in that cracks 7 may occur inside the mold resin 6 (not shown) on the upper surface of the holder.

このクラック7は単に外観を損なうだけでなく、半導体
素子3の耐湿信頼性を著しく低下させることに繋がるも
のである。
This crack 7 not only impairs the appearance but also leads to a significant decrease in the moisture resistance reliability of the semiconductor element 3.

更に、上記半導体パッケージの多ピン化に伴い、半導体
パッケージの大型化及び半導体素子サイズの大型化が進
む一方で、半導体パッケージの厚さとは逆に、薄型化の
方向にある。
Further, as the number of pins in the semiconductor package increases, the size of the semiconductor package and the size of the semiconductor element are increasing, while the thickness of the semiconductor package is becoming thinner.

このため、第15図及び第16図に示すように、グイパ
ッド2を支えるタイバー1がますます長くなり、その一
方でグイパッド2のサイズが大型化し、この影響により
、樹脂モールド時に充填される溶融した熱硬化性樹脂の
流動圧力Pによって、ダイパッド2及び半導体素子3が
通常の位置より押し上げられたり(第15図)、若しく
は押し下げられたり(第16図)する現象が生じてしま
う。
For this reason, as shown in Figures 15 and 16, the tie bar 1 that supports the Gui pad 2 has become increasingly long, and the size of the Gui pad 2 has also increased. The flow pressure P of the thermosetting resin causes a phenomenon in which the die pad 2 and the semiconductor element 3 are pushed up from their normal positions (FIG. 15) or pushed down (FIG. 16).

この現象は、ダイパッド2の上下運動により、単にワイ
ヤボンディング部にダメージを与えるばかりでなく、半
導体素子3の上側又は下側の樹脂層が極端に薄くなるこ
とにより、特に半田リフロー後の著しい耐湿性の劣化を
きたすことにもつながるものである。
This phenomenon not only damages the wire bonding part due to the vertical movement of the die pad 2, but also causes the upper or lower resin layer of the semiconductor element 3 to become extremely thin, resulting in significant moisture resistance, especially after solder reflow. It also leads to deterioration of the

上記クラックの発生を防止するため、例えば特開昭60
−208847号として、半導体素子の裏面のモールド
樹脂部に円柱又は多角形状の穴をあけ、極度に肉厚の薄
い部分又はモールド樹脂がない部分を形成して、半導体
パッケージ全体の加熱に際して、この内部の水分の蒸発
によるガスを逃す手段としたものが提案されている。
In order to prevent the above-mentioned cracks from occurring, for example,
-208847, a cylindrical or polygonal hole is made in the molding resin part on the back side of the semiconductor element to form an extremely thin part or a part without molding resin, and when the entire semiconductor package is heated, this internal part is heated. A method has been proposed that allows gas to escape due to the evaporation of moisture.

(発明が解決しようとする問題点) しかしながら、上記特開昭60−208847号公報に
記載されたものは、半導体素子の裏面のモールド樹脂に
穴があけられているため、半導体素子を搭載したダイパ
ッドの下面が外部に露出してしまうばかりでなく、半導
体パッケージ全体が高温にさらされることによって、モ
ールド樹脂とダイパッドとの密着性が低下して放射状に
剥がれてしまい、ここから腐蝕が始まって半導体素子に
悪影響を与えるおそれがあると考えられる。
(Problems to be Solved by the Invention) However, in the method described in JP-A-60-208847, a hole is made in the mold resin on the back side of the semiconductor element, so the die pad on which the semiconductor element is mounted is Not only is the bottom surface exposed to the outside, but the entire semiconductor package is exposed to high temperatures, which reduces the adhesion between the molding resin and the die pad and causes it to peel off in a radial pattern, which is where corrosion begins and damages the semiconductor element. It is considered that there is a risk of having a negative impact on

また実装時に用いられるフラックスや、実装後の洗浄工
程において使用される処理液等が穴から侵入した場合に
は、これらが容易にグイパッド裏面全面を汚染してしま
うため、ダイパッドの腐食や、耐湿信頼性の劣化を引き
起こすといった問題点があると考えられる。
Additionally, if the flux used during mounting or the processing liquid used in the post-mounting cleaning process enters through the holes, they can easily contaminate the entire back surface of the die pad, resulting in corrosion of the die pad and moisture resistance. It is thought that there are problems such as causing sexual deterioration.

更に、上記樹脂モールドによるダイパッド及び半導体素
子の上方向又は下方向へのずれ(以下、ダイパッドの浮
き又は沈みという)に対する対策は、何等施されていな
かった。
Furthermore, no countermeasures have been taken against upward or downward displacement of the die pad and semiconductor element by the resin mold (hereinafter referred to as floating or sinking of the die pad).

本発明は上記に鑑み、実装時に内部の樹脂クラックの発
生をなくして、吸湿後に全体加熱による半田付実装を行
っても耐湿信頼性に問題がなく、しかも半導体素子に悪
影響を与えてしまうことがないばかりでなく、パッケー
ジ自体の大型化にも対処することができ、更にはダイパ
ッドの浮き又は沈みの発生をなくして、この点でも耐湿
信頼性上の問題をなくすようにすることもできるものを
提供することを目的とする。
In view of the above, the present invention eliminates the occurrence of internal resin cracks during mounting, so that there is no problem in moisture resistance reliability even when soldering is performed by heating the entire body after moisture absorption, and there is no adverse effect on semiconductor elements. In addition, it is possible to cope with the increase in the size of the package itself, and furthermore, it can eliminate the occurrence of floating or sinking of the die pad, and in this respect, it can also eliminate problems with moisture resistance reliability. The purpose is to provide.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) 本発明は上記目的を達成するため、タイバーにより支持
したダイパッドの上面に搭載した半導体素子をモールド
樹脂で樹脂封止した半導体装置において、上記モールド
樹脂の表面又は裏面の少なくとも一方、例えばモールド
樹脂の裏面のみ、又はモールド樹脂の夫々対応する表面
及び裏面の双方等に、上記タイバーに達する穿孔又は切
欠きを1個以上設けたものである。
(Means for Solving the Problems) In order to achieve the above object, the present invention provides a semiconductor device in which a semiconductor element mounted on the upper surface of a die pad supported by tie bars is sealed with a mold resin. One or more perforations or notches reaching the tie bar are provided on at least one of the back surfaces, for example, only on the back surface of the mold resin, or on both the corresponding front and back surfaces of the mold resin.

(作 用) 而して、モールド樹脂の内部、特にモールド樹脂とダイ
パッドの界面の近傍に存在する水分を、実装時の高温下
において蒸気として穿孔又は切欠きから効果的に外部に
排出することにより、この出口を予め形成してこの蒸気
によるクラックの発生を防止するとともに、この穿孔又
は切欠きをタイバーに達するよう設けることにより、こ
の穿孔又は切欠きによって、半導体素子に悪影響を与え
てしまうことを防止するとともに、パッケージの形状の
大型化に対処し、更にモールド樹脂の表面及び裏面の夫
々対向する位置に上記穿孔又は切欠きを設けることによ
り、樹脂モールド時に穿孔又は切欠を介してタイバーを
上下方向から押圧してこれを固定することにより、ダイ
パッドの浮き又は沈みの発生を確実に防止するようする
こともできるものである。
(Function) By effectively discharging moisture existing inside the mold resin, especially near the interface between the mold resin and the die pad, to the outside as steam through the perforations or notches under high temperatures during mounting. By forming this outlet in advance to prevent the occurrence of cracks due to this vapor, and by providing this perforation or notch so as to reach the tie bar, it is possible to prevent the perforation or notch from having an adverse effect on the semiconductor element. By providing the above-mentioned perforations or notches at opposite positions on the front and back surfaces of the molded resin, it is possible to prevent the tie bars from moving in the vertical direction through the perforations or notches during resin molding. By pressing and fixing the die pad, it is possible to reliably prevent the die pad from floating or sinking.

(実施例) 第1図及び第2図は、本発明の第1の実施例を示すもの
で、隅部から四方に延びるタイバー1により平板状のグ
イパッド2の四隅が支持され、このダイパッド2の上面
には半導体素子3が搭載されている。この半導体素子3
とリード線4とは、第14図に示すようにボンディング
ワイヤ5でボンディングされている。
(Embodiment) FIGS. 1 and 2 show a first embodiment of the present invention, in which the four corners of a flat die pad 2 are supported by tie bars 1 extending in all directions from the corners. A semiconductor element 3 is mounted on the upper surface. This semiconductor element 3
and lead wire 4 are bonded with bonding wire 5 as shown in FIG.

この半導体素子3及びこの周囲は矩形状のモールド樹脂
6で樹脂封止されて半導体パッケージPが構成されてい
る。
This semiconductor element 3 and its surroundings are resin-sealed with a rectangular molding resin 6 to constitute a semiconductor package P.

このモールド樹脂6の裏面の対角線上の上記タイバー2
に対向する4ケ所の位置には、このタイバー2に達する
穿孔6aが夫々設けられている。
The tie bar 2 on the diagonal line on the back side of this molded resin 6
Perforations 6a reaching this tie bar 2 are provided at four positions facing each other.

このように、穿孔6aを設けることにより、半導体パッ
ケージP全体を200℃以上の高温にさらして半導体装
置を基板等に実装する時、特に半導体素子3とダイパッ
ド2との界面に存在して蒸発する水分を、このダイパッ
ド2に連続したタイバー1を伝わってこの穿孔6aから
外部に排出させることにより、この蒸発の圧力によって
モールド樹脂6の内部にクラックが発生してしまうこと
を防止するのである。
As described above, by providing the perforations 6a, when the entire semiconductor package P is exposed to high temperatures of 200° C. or higher and the semiconductor device is mounted on a substrate, etc., the holes 6a are present and evaporated, especially at the interface between the semiconductor element 3 and the die pad 2. By discharging moisture to the outside through the tie bars 1 continuous to the die pad 2 through the perforations 6a, cracks are prevented from forming inside the mold resin 6 due to the pressure of this evaporation.

しかも、通常クラックの発生は、ダイパッド2の四辺の
中央に対応する位置から隅部の方向に向かって円弧状に
進み、隅部には発生しにくいため、このように穿孔6a
を設けても、ここからクラックが発生してしまうおそれ
は少ない。
In addition, cracks normally occur in an arc shape from the center of the four sides of the die pad 2 toward the corners, and are less likely to occur in the corners.
Even if this is provided, there is little risk of cracks occurring from this point.

更に、このように穿孔6aを設けることにより、ダイパ
ッド2の隅部とこの穿孔6aとの距離pを半導体パッケ
ージPの外形により決まるタイバー長さしより短くなし
て、クラックの発生に関し、この穿孔6aを結ぶ線で囲
まれた範囲の大きさの半導体パッケージと実質的に同等
な大きさの半導体パッケージのようにし、これにより通
常半導体パッケージの大きさが小さけれは小さい程りラ
ブクの発生が少ないので、クラックの発生を極力防止し
ているのである。
Furthermore, by providing the perforation 6a in this manner, the distance p between the corner of the die pad 2 and the perforation 6a can be made shorter than the tie bar length determined by the external shape of the semiconductor package P, thereby preventing the occurrence of cracks. The size of the semiconductor package is set to be substantially the same as the size of the semiconductor package surrounded by the line connecting the This is to prevent the occurrence of cracks as much as possible.

このようにして構成した半導体装置を、85℃で85%
RHの加速雰囲気で半導体パッケージ内の水分量が飽和
状態になるまで放置し、215℃で2分間半田浸漬した
後に、クラックの発生を調べた結果、10個中にクラッ
クの発生したものは全くなかった。これに対して、従来
のものを上記と同様にして実験した結果では、10個中
の全てにクラックが発生した。
The semiconductor device constructed in this way was heated to 85% at 85°C.
After leaving the semiconductor package in an accelerated atmosphere of RH until the moisture content reached a saturated state and immersing it in solder for 2 minutes at 215°C, we examined the occurrence of cracks and found that none of the 10 had any cracks. Ta. On the other hand, according to the results of experiments conducted on conventional products in the same manner as above, cracks occurred in all 10 of them.

第3図及び第4図は、第2の実施例を示すもので、上記
実施例と異なる点は、モールド樹脂6の対角線上のタイ
バー1に対向する位置の裏面の一ケ所に、このタイバー
1に達する切欠き6bを設けた点にある。
3 and 4 show a second embodiment, and the difference from the above embodiment is that this tie bar 1 is placed at one place on the back surface of the molded resin 6 at a position opposite to the tie bar 1 on the diagonal line. The point is that a notch 6b reaching .

このようにして、半導体パッケージPの全体を200℃
以上の雰囲気にさらした時に、この切欠き6bからモー
ルド樹脂6の内部の蒸発した水分を排出させるのである
In this way, the entire semiconductor package P is heated to 200°C.
When exposed to the above atmosphere, the evaporated moisture inside the mold resin 6 is discharged from the notch 6b.

なお、上記のようにモールド樹脂6の裏面から穿孔68
等を設けたのは、主に美感を損なうことがないようにす
るためであり、モールド樹脂6の表面から穿孔6a等を
設けるようにすることもできる。
In addition, as mentioned above, the perforations 68 are made from the back side of the molded resin 6.
The reason why holes 6a etc. are provided is mainly to avoid spoiling the aesthetic appearance, and it is also possible to provide perforations 6a etc. from the surface of the molded resin 6.

また、半導体素子3の上面にジャンクションコーティン
グレジン(JCR)又はポリイミド等を塗布して、耐湿
信頼性のより一層の向上を図るようにすることもできる
Furthermore, it is also possible to coat the upper surface of the semiconductor element 3 with junction coating resin (JCR), polyimide, or the like to further improve the moisture resistance reliability.

第5図及び第6図は、第3の実施例を示すもので、モー
ルド樹脂6の表面及び裏面の双方の上下から、上記タイ
バー1に対向する対角線上の4ケ所で、且つお互いに対
向する位置に、上記タイバー1に達する穿孔6g、6a
’を夫々設けたものである。
FIGS. 5 and 6 show a third embodiment, in which the molded resin 6 is placed at four locations on a diagonal line facing the tie bar 1 from above and below on both the front and back surfaces, and facing each other. Holes 6g and 6a reaching the tie bar 1 are located at the positions.
'.

このように、夫々対向する上下から夫々穿孔6a、6a
’を設けることにより、上記表面又は裏面の一方のみか
ら設けた効果の他に以下のような効果がある。
In this way, the perforations 6a, 6a are formed from the opposing upper and lower sides, respectively.
By providing ', the following effects are obtained in addition to the effects provided from only one of the front and back surfaces.

即ち、第7図に示すように、樹脂モールドする際、本来
パッケージの端(タイバー長さL)でモールド金具8.
8によって固定されているタイバー2が、その途中の位
置(距離II (<L))でモールド金具8.8の突出
部8a、8aで上下から押圧して固定するようにするこ
とができるため、このタイバー1によって支持されるダ
イパッド2及び半導体素子3が、溶融した熱硬化性樹脂
の流動圧力により通常あるべき位置よりも押し上げられ
たり、又は押し下げられたりすることを確実に防止する
ようにすることができる。
That is, as shown in FIG. 7, when resin molding is performed, the mold fitting 8.
The tie bar 2 fixed by the mold fitting 8.8 can be pressed and fixed from above and below by the protrusions 8a, 8a of the molded metal fitting 8.8 at an intermediate position (distance II (<L)). To surely prevent a die pad 2 and a semiconductor element 3 supported by this tie bar 1 from being pushed up or down from their normal positions due to the flow pressure of the molten thermosetting resin. Can be done.

しかも、このようにダイパッド2及び半導体素子3の浮
き又は沈みを確実に防止することにより、半導体素子3
の上側又は下側の樹脂厚を適正値に保つことができ、こ
れによって、特に大型で薄型の半導体パッケージにおい
て、特に半田リフロー後の良好な耐湿信頼性を得るよう
にすることができる。
Moreover, by reliably preventing the die pad 2 and the semiconductor element 3 from floating or sinking, the semiconductor element 3
The resin thickness on the upper or lower side of the semiconductor package can be maintained at an appropriate value, thereby making it possible to obtain good moisture resistance reliability especially after solder reflow, especially in a large and thin semiconductor package.

なお、この実施例において、上記モールド樹脂6の表裏
両面に設けた穿孔6a、6a’は、タイバー1に近付く
程、小さくなるテーバ状に形成されているが、このよう
に形成することにより、モールド成型時の成型し品さを
図るようにすることができる。
In this embodiment, the perforations 6a and 6a' provided on both the front and back surfaces of the mold resin 6 are formed in a tapered shape that becomes smaller as they approach the tie bar 1. It is possible to improve the quality of the molding during molding.

第8図は、第4の実施例を示すもので、ダイパッド2の
左右の二辺に中央から延びるタイバー1により、上記ダ
イパッド2を支持するとともに、このタイバー1に対向
する左右の2カ所の表面及び裏面の双方から、且つお互
いに対向する位置に、夫々上記タイバー1に達する穿孔
6a、 6a’を夫々設けたものである。
FIG. 8 shows a fourth embodiment, in which the die pad 2 is supported by tie bars 1 extending from the center on the left and right sides of the die pad 2, and two surfaces on the left and right opposite to the tie bars 1 are supported. Perforations 6a and 6a' reaching the tie bar 1 are provided from both the back side and at positions facing each other, respectively.

なお、上記実施例において、第9図に示すように、上記
穿孔6aに対応する位置にあるタイバー1の一部に面積
の大きな大形部1aを形成することにより、タイバー1
は一般に細幅であるため、この穿孔6aが確実にタイバ
ー1に達するようにするとともに、美観の向上を図るよ
うにすることができる。
In the above embodiment, as shown in FIG. 9, by forming a large portion 1a with a large area in a part of the tie bar 1 located at a position corresponding to the perforation 6a, the tie bar 1
Since the width of the perforation 6a is generally narrow, it is possible to ensure that the perforation 6a reaches the tie bar 1 and to improve the appearance.

第10図及び第11図は、第5の実施例を示すもので、
モールド樹脂6の表面及び裏面の双方の上下から、上記
タイバー′1に対向する対角線上の2ケ所で、且つお互
いに対向する位置に、夫々上記タイバー1に達する切欠
き6b、6b’を設けたものである、 上記のように、穿孔6a、5a’又は切欠き6b、6b
’は、1力所以上で、且つモールド樹脂6の表面及び裏
面の夫々対向する位置から設ければ、ダイパッド2及び
半導体素子3の浮き又は沈みを防止する効果を発揮する
ことができる。
10 and 11 show the fifth embodiment,
Notches 6b and 6b' reaching the tie bar 1 are provided at two diagonal locations facing the tie bar '1 from above and below on both the front and back surfaces of the molded resin 6, and at positions facing each other. As mentioned above, the perforations 6a, 5a' or the notches 6b, 6b
If ' is provided at one or more places of force and from opposite positions on the front and back surfaces of the mold resin 6, the effect of preventing the die pad 2 and the semiconductor element 3 from floating or sinking can be exhibited.

また、半導体素子3の上面に、ポリイミド等を塗布して
、耐湿信頼性のより一層の向上を図るようにすることも
できる。
Further, the upper surface of the semiconductor element 3 may be coated with polyimide or the like to further improve moisture resistance reliability.

〔発明の効果〕〔Effect of the invention〕

本発明は上記のような構成であるので、半田付実装時に
半導体パッケージ全体が200℃以上の高温にさらされ
た時に、モールド樹脂の内部に存在する水分は蒸気とな
って、容品に外部に排出され、この蒸気によってクラッ
クが発生することを防止することができる。
Since the present invention has the above-described configuration, when the entire semiconductor package is exposed to a high temperature of 200°C or higher during soldering and mounting, the moisture existing inside the molding resin turns into steam and is released into the package outside. It is possible to prevent cracks from occurring due to this vapor.

しかも、大型の半導体パッケージにおいても、穿孔等の
位置によって、クラックの発生に関しては小型の半導体
パッケージと実質的に同等となして、この発生を防止し
、この信頼性を向上させることができる。
Moreover, even in a large semiconductor package, the occurrence of cracks can be made substantially the same as in a small semiconductor package, depending on the position of the perforations, etc., thereby preventing the occurrence of cracks and improving reliability.

更に、半導体素子を搭載したダイパッドの下面が外部に
露出することがないので、ここが腐蝕してしまうおそれ
はない。また穿孔からダイパッドまでは細いタイバーで
繁っているので外部からの汚染物質の侵入を抑制するこ
とができる。従って穿孔等によって半導体素子に悪影響
を与えてしまうことはない。
Furthermore, since the bottom surface of the die pad on which the semiconductor element is mounted is not exposed to the outside, there is no risk of corrosion. Furthermore, since there are thin tie bars extending from the perforation to the die pad, it is possible to suppress the intrusion of contaminants from the outside. Therefore, the semiconductor element will not be adversely affected by the perforation or the like.

加えて、モールド樹脂の表面及び裏面の夫々対向する位
置にタイバーに達する穿孔又は切欠きを設けることによ
り、樹脂モールドによるダイパッド及び半導体素子の上
下方向へのずれ(浮き又は沈み)を確実に防ぐようにす
ることができ、これによって、特に大型で薄型の半導体
パッケージでの、この浮き又は沈みによる耐湿信頼性上
の問題をなくすようにすることができるといった効果が
ある。
In addition, by providing perforations or notches that reach the tie bars at opposing positions on the front and back surfaces of the mold resin, it is possible to reliably prevent vertical displacement (lifting or sinking) of the die pad and semiconductor element due to the resin mold. This has the effect of eliminating moisture-resistance reliability problems caused by this floating or sinking, especially in large and thin semiconductor packages.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本発明の第1の実施例を示し、第1
図は第2図のI−X線断面図、第2図は裏面図、第3図
及び第4図は第2の実施例を示し、第3図は第4図の■
−■線断面図、第4図は裏面図、第5図乃至第7図は第
3の実施例を示し、第5図は第6図のV−V線断面図、
第6図は裏面図(表面図)、第7図はその製造工程にお
ける断面図、第8図は第4の実施例を示す裏面図(表面
図)、第9図はタイバーの変形例を示す裏面図、第10
図及び第11図は第5の実施例を示し、第10図は第1
1図のX−X線断面図、第11図は裏面図(表面図)、
第12図乃至第14図は従来例を示し、第12図は裏面
図、第13図は第12図+7)X111−Xlll線断
面図、第14図は同じ< XIV−X+V線断面図、第
15図及び第16図は夫々異なる他の従来例を示す断面
図である。 1・・・タイバー、2・・・ダイパッド、3・・・半導
体素子、6・・・モールド樹脂、6a、 6a’・・・
同穿孔、6b、6b’・・・同切欠き。 第1図 第2図 第3図 第4図 第5図 ρ 第6図 第8図 第9図 第10図 第11図 第12図 第13図 第14図 第15図 第16図 手続補正書 昭和63年2り′介日
FIG. 1 and FIG. 2 show a first embodiment of the present invention.
The figure is a sectional view taken along the line I-X in Figure 2, Figure 2 is a back view, Figures 3 and 4 show the second embodiment, and Figure 3 is a cross-sectional view of Figure 4.
-■ line sectional view, Figure 4 is a back view, Figures 5 to 7 show the third embodiment, Figure 5 is a V-V line sectional view of Figure 6,
Figure 6 is a back view (front view), Figure 7 is a sectional view of the manufacturing process, Figure 8 is a back view (front view) showing the fourth embodiment, and Figure 9 is a modification of the tie bar. Back view, No. 10
11 shows the fifth embodiment, and FIG. 10 shows the first embodiment.
Figure 1 is a cross-sectional view taken along the line X-X, Figure 11 is a back view (front view),
12 to 14 show the conventional example, FIG. 12 is a back view, FIG. 13 is a sectional view taken along the line 12+7) FIG. 15 and FIG. 16 are sectional views showing other different conventional examples. DESCRIPTION OF SYMBOLS 1... Tie bar, 2... Die pad, 3... Semiconductor element, 6... Mold resin, 6a, 6a'...
Same perforation, 6b, 6b'...same notch. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 ρ Figure 6 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Procedure Amendment Book Showa February 1963

Claims (1)

【特許請求の範囲】 1、タイバーにより支持したダイパッドの上面に搭載し
た半導体素子をモールド樹脂で樹脂封止した半導体装置
において、上記モールド樹脂の表面又は裏面の少なくと
も一方に上記タイバーに達する穿孔又は切欠きを1個以
上設けたことを特徴とする半導体装置。 2、上記モールド樹脂の表面及び裏面の夫々対向する位
置に、上記タイバーに達する穿孔又は切欠きを夫々設け
たことを特徴とする特許請求の範囲第1項記載の半導体
装置。
[Scope of Claims] 1. In a semiconductor device in which a semiconductor element mounted on the upper surface of a die pad supported by tie bars is sealed with mold resin, a perforation or cut that reaches the tie bars is provided on at least one of the front or back surface of the mold resin. A semiconductor device characterized by having one or more notches. 2. The semiconductor device according to claim 1, wherein perforations or notches reaching the tie bars are provided at opposing positions on the front and back surfaces of the molding resin, respectively.
JP62330433A 1986-12-26 1987-12-26 Semiconductor device Expired - Lifetime JP2607576B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62330433A JP2607576B2 (en) 1986-12-26 1987-12-26 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP61-313754 1986-12-26
JP31375486 1986-12-26
JP62330433A JP2607576B2 (en) 1986-12-26 1987-12-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS63265452A true JPS63265452A (en) 1988-11-01
JP2607576B2 JP2607576B2 (en) 1997-05-07

Family

ID=26567693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62330433A Expired - Lifetime JP2607576B2 (en) 1986-12-26 1987-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2607576B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5879739A (en) * 1981-11-05 1983-05-13 Toshiba Corp Sheath for semiconductor
JPS59121959A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Semiconductor device and its manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5879739A (en) * 1981-11-05 1983-05-13 Toshiba Corp Sheath for semiconductor
JPS59121959A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Semiconductor device and its manufacture

Also Published As

Publication number Publication date
JP2607576B2 (en) 1997-05-07

Similar Documents

Publication Publication Date Title
KR100552353B1 (en) Leadframe Semiconductor Integrated Circuit Device Using the Same and Method of and Process for Fabricating the Two
US6510976B2 (en) Method for forming a flip chip semiconductor package
US20030205797A1 (en) Method of manufacturing a semiconductor device and a semiconductor device
US4855807A (en) Semiconductor device
JP3686287B2 (en) Manufacturing method of semiconductor device
US6255742B1 (en) Semiconductor package incorporating heat dispersion plate inside resin molding
US10707154B2 (en) Semiconductor device and method for manufacturing the same
TWI624014B (en) Semiconductor device and manufacturing method thereof
JPH0294653A (en) Resin-sealed semiconductor device
JPS63265452A (en) Semiconductor device
US6232651B1 (en) Lead frame for semiconductor device
EP0711104B1 (en) Semiconductor device and method for making same
JPH0870087A (en) Lead frame
KR100419981B1 (en) layer structure of semiconductor installed board
JPH0526761Y2 (en)
JPH0794674A (en) Semiconductor device and fabrication thereof
KR101026116B1 (en) Bonding structure and method for bonding substrates using the same
JPH04142042A (en) Manufacture of semiconductor device
JPH06283629A (en) Semiconductor device and method and mold for manufacturing same
JPH02117162A (en) Semiconductor device
JPH01110754A (en) Resin-sealed semiconductor integrated circuit device
JPH07106493A (en) Lead frame and manufacture of semiconductor package using the lead frame
JPH01187954A (en) Resin seal type semiconductor device
JPS6248386B2 (en)
JPH0766352A (en) Lead frame

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term