JPS63262742A - Common bus monitor - Google Patents

Abstract

PURPOSE:To leave behind bus information to a bus cycle in which busy has been generated, by storing busy information and stopping the subsequent recording, when bus busy has been detected, and restarting the recording of the bus information after the busy has been recovered. CONSTITUTION:When a bus request is generated, a timer 7 is started. When a prescribed time T elapses after the start of the timer 7, a bus busy detecting circuit 8 decides that a bus to a bus cycle (n) is busy. By this decision, a stop of updating of an address is instructed to an address control circuit 9, and a stop of an input of bus information is instructed to a memory register 2. Also, simultaneously, by setting a flag to the bus cycle (n) of a busy information memory 4, it is stored to be busy. After the bus busy has been recovered, recording of the bus information is restarted continuously without sweeping away the bus information to the bus cycle (n).

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a data processing system in which a central processing unit, a memory, and an input/output device communicate information via a common bus. Regarding the common bus monitor that records.

(Problems to be solved by conventional technology and invention) Conventionally,
This type of bus monitor can detect a busy state of the bus and stop recording bus information, but when the busy state returns and resumes recording bus information,
The bus information for the bus cycle that triggered the busy state was flushed from the bus information memory.

Therefore, there is a drawback that the bus information for the bus cycle in which the bus is busy does not remain in the bus information memory.

(Means for Solving the Problems) The common bus monitor of the present invention is a data processing system in which a central processing unit, memory, and input/output devices communicate information via a common bus, and a history of communication information on the common bus. a memory register that temporarily stores communication information on the bus as bus information; a bus information memory that continuously stores the contents of the memory register for each bus cycle; and a cycle in which a bus busy occurs. a busy information memory for storing the contents of the memory register, an address control circuit for instructing the address of the bus information memory for storing the contents of the memory register, an address register for temporarily storing the address instructed by the address control circuit, and a bus request. a request flip-flop that resets the request flip-flop after a certain period of time; a timer that measures from the time the request flip-flop is set until a predetermined time; a bus busy detection circuit that determines that there is a bus busy detection circuit;
When bus busy is detected, the method instructs the address control circuit to stop updating the address, instructs the memory register to stop inputting the bus information, and holds the previous bus information in the bus information memory. shall be.

(Example) Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the positioning of a common bus monitor according to an embodiment of the present invention in a data processing system. The common bus monitor is connected to the common bus as an independent device like the central processing unit, memory, and input/output devices.

FIG. 2 is a block diagram showing the configuration of the common bus monitor of this embodiment. This embodiment uses bus interface 1. Memory register 2. Bus information memory 3, busy information memory 4. Control port #r5. Request flip-flop 6, timer 7, bus busy detection circuit 8. It consists of an address control circuit 9 and an address register 10.

Information on the common bus is temporarily stored in a memory register 2 via a bus interface 1, and then sequentially stored in a bus information memory 3 starting from address 0. When the bus information memory 3 reaches the final address, the bus information memory 3 returns to 0.
It is a memory that stores bus information endlessly, starting from the address. This storage address is updated by the address control circuit 9 and temporarily stored in the address register 1o.

FIG. 3 is a time chart when there is a bus request from the central processing unit or the like in this embodiment. The dotted line in FIG. 3 represents the operation when the bus request is not reset within the predetermined time T for some reason in bus cycle n.

Normally, when a bus request occurs, the request flip-flop 6 is set and the timer 7 is activated, and when the bus request ends, the request flip-flop 6 and timer 7 are reset. However, in the above case, as shown by the dotted line in FIG. 3, the request flip-flop 6 remains set after the predetermined time T has elapsed since the start of the timer 7, so the bus busy detection circuit 8 It determines that the bus for bus cycle n is busy, and instructs the address system SO path 9 to stop updating the address, and instructs the memory register 2 to stop inputting bus information. At the same time, a flag for bus cycle n is set in the busy information memory 4 to store that it is busy.

After bus busy recovery, recording of the bus information is resumed without flushing out the bus information for bus cycle n.

(Effects of the Invention) As explained above, the present invention stores busy information when a bus is busy and stops recording of the bus information thereafter.
By continuing to resume recording of bus information after bus busy recovery, the bus information for the bus cycle in which the busy occurred can be retained, which is effective in failure analysis.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the positioning of a common bus monitor according to an embodiment of the present invention in a data processing system, FIG. 2 is a block diagram showing the configuration of the common bus monitor according to this embodiment, and FIG. It is a time chart when there is a bus request from a central processing unit or the like. DESCRIPTION OF SYMBOLS 1... Bus interface, 2... Memory register, 3... Bus information memory, 4... Busy information memory, 5... Control circuit, 6... Request flip-flop, 7... Timer , 8... bus busy detection circuit,
9...Address control circuit, 10...Address register.

Claims (1)

[Scope of Claims] A data processing system in which a central processing unit, a memory, and an input/output device communicate information via a common bus, and an apparatus for recording the history of communication information on the common bus, comprising: a memory register that temporarily stores the contents of the memory register as bus information; a bus information memory that continuously stores the contents of the memory register for each bus cycle; a busy information memory that stores the cycle in which the bus busy occurs; an address control circuit that instructs the address of the bus information memory to be stored; an address register that temporarily stores the address instructed by the address control circuit; a request flip-flop that resets the bus request after a certain period of time; and a bus busy detection circuit that determines that the bus is busy if the request flip-flop remains set when the predetermined time is reached. When the circuit detects bus busy, it instructs the address control circuit to stop updating the address, instructs the memory register to stop inputting the bus information, and retains the previous bus information in the bus information memory. A common bus monitor characterized by: