JPH07319816A - Method for collecting logging information in cpu system - Google Patents

Abstract

PURPOSE:To provide a method for automatically collecting logging information obtained in the past without requiring manual processing when a CPU generates an alarm and a method for shortening time required up to restart after the reset of the CPU in respect to a method for collecting logging information for a past processing process when a CPU system detects abnormality and generates an alarm. CONSTITUTION:A common RAM 8 for simultaneously executing the writing and reading of lagging information in/from a main storage part 4 by a main CPU 1, a logging information storing part 10 to be a non-volatile memory to which the data of the RAM 8 are to be transferred and a sub-CPU 9 for transferring the data of the RAM 8 to the storing part 10 by a program stored in its own ROM are connected to a system bus 100 in the CPU system, and when the CPU system is turned to an abnormal state, the logging information of a processing process executed by the main CPU 1 up to this time is stored in the storing part 10 without being cleared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU system which performs a certain operation under the control of the CPU, and when the CPU detects an abnormality of the system and generates an alarm, a process used for analyzing the cause of the alarm occurrence. The present invention relates to a method of collecting logging information that is progress information.

[0002]

2. Description of the Related Art In a conventional CPU system, referring to the system configuration diagram of FIG. 11 and the operation flow diagram of FIG.
The progress of processing performed by is always written in the work area work area provided in the main memory, and when the error detection unit (11) detects a system error and an alarm occurs, it is used as logging information used for cause analysis. . But in this case,
When the reset circuit resets the CPU, FIG.
As shown in the operation flow chart of the above, since the CPU operates in the initialization sequence starting with the start-up program written in advance in the ROM, the information written up to that point in the main memory is erased and cleared. Therefore, the logging information acquired earlier is lost.

[0003]

Therefore, after collecting the logging information by human work such as an operator,
It is necessary to reset the CPU. Therefore, CPU
There is a problem that it takes time to reset the system and restore the system to the normal operation. The purpose of the present invention is to
When the CPU detects an abnormality of the system and generates an alarm, there is a method of automatically collecting logging information up to that time without any manual work and a method of shortening the time until the CPU is reset. To provide. In the present invention, not only the reset signal is sent to the CPU and other circuits, but also so-called power-on reset by turning off / on the power source is considered. Since a volatile memory such as DRAM or SRAM is used in the conventional main memory unit in order to improve the writing speed, the contents of the memory may not be retained when the power is turned off. , Even if you tried to use the data in the memory contents as it was, there was a possibility that the data was already destroyed.
Therefore, the CPU clears the memory when the system starts up.

[0004]

The basic configuration of claim 1 of the present invention for achieving the above object is as follows. Referring to the principle diagram of FIG. 1, a main CPU is installed on a system bus (100) of a conventional CPU system. A common RAM capable of simultaneously writing and reading the logging information from the main memory, and the common RA
The logging information storage unit (10) of the non-volatile memory to which the data of M is transferred and the data of the common RAM are stored in the own RO.
If a CPU system has an abnormality, the logging information of the processing progress by the main CPU up to that time is not cleared, provided with the sub CPU that is transferred to the logging information storage unit (10) by the program in M. The logging information storage unit
Configured to be stored in (10).

The constitution of claim 2 which aims to eliminate the use of software by the sub CPU in claim 1 and to constitute only the hardware, refers to the principle diagram of FIG. 2, and the sub CPU in the constitution of claim 1 When the main CPU detects a system error in the error detection unit (11), the data transfer timing control signals c1 and c2 are generated, and the logging information written in the common RAM up to that time. Read out, logging information storage section of non-volatile memory
It is configured to include a data transfer control unit for transferring data to (10).

According to a second aspect of the present invention, which is directed to a circuit configuration which does not use a common RAM in which writing and reading timing control by the CPU is difficult,
Refer to the principle diagram of the above, the main CPU is equipped with a FIFO memory that receives writing from the CPU in sequence under normal conditions and sends the updated output to the logging information storage unit (10) by hardware, and the main CPU has an abnormality detection unit. When the system abnormality is detected in (11), the timing control signals c1 and c2 from the data transfer control unit disable writing to the FIFO memory, and the output logging information is not updated and retained. To configure.

Next, even if the contents of the main memory are cleared by resetting the CPU again, the logging information can be held without being cleared.
Referring to the principle diagram of FIG. 4, the system bus (100) is set to an enable state in which the CPU can write during normal operation of the system, and when the system is abnormal, data can be immediately written even when the system is next restored. It has a bus control unit that disables it and a logging information storage unit (10) of non-volatile memory that stores the processing information of the CPU until the occurrence of an abnormality.The CPU is reset again and the main storage unit is cleared. Even if it is done, the logging information in the logging information storage unit (10) is configured to be retained without being cleared.

Next, in the above claims 1 to 4, the method is to collect all the logging information of the processing until the CPU detects the system abnormality.
It aims at the method of logging detailed information of the interrupt factor (Non Maskable Interruption etc.) to PU. According to the configuration of claim 5, referring to the principle diagram of FIG. 5, a power source backup unit of a standby power source, an SRAM backed up by the power source backup unit, and a register for reading out detailed information of an interrupt.
(11), a reset register (12) for the CPU, a timer section (13) that outputs a pulse p only for a fixed time by the output from the register (11), and interrupt information is logged in the SRAM. With a register (14) indicating that
When the CPU reads the information in the SRAM and recognizes that it is the interrupt information, the CPU writes a reset signal to the reset register (12) to reset itself and restart. To configure.

[0009]

In the structure of claim 1 of FIG. 1, the CPU is a ROM.
While starting the main program inside, write the logging information in the main memory to the common RAM.
It continues from the occurrence of the CPU alarm to the reset. The logging data written in the common RAM is
The sub CPU for logging information transfer reads out and transfers to the logging information storage unit (10). In this case, if the logging information storage unit (10) is an electrical write / erase type ROM (EEPRO
If it is composed of M), the write cycle must be taken into consideration, and the sub CPU performs the processing.
However, the start / stop of the logging information transfer is started by the main CPU.
It is controlled by an alarm signal detected by the side abnormality detection circuit (11). That is, the data transfer from the common RAM to the logging information storage unit (10) is performed only during the period when the main CPU is operating normally, and the data during the CPU alarm is not transferred. This prevents the logging data from being overwritten. According to the configuration of claim 1 of the present invention, since the logging data is saved even when the CPU is reset, the system can be reset immediately when the system goes down.

In the structure of claim 2 of FIG. 2, the data transfer of the logging data transferred to the logging information storage section (10) by using the software of the ROM of the sub CPU in the structure of claim 1 is carried out. This is done by hardware called the control unit. The data transfer control unit sends address information and read control signals to the common RAM, and the logging information storage unit (1
Address information and a write control signal are sent to 0). As a result, data is transferred from the common RAM to the logging information storage unit (10). After that, the data is sequentially transferred by sequentially changing the address value.

In the configuration of claim 3 of FIG. 3, by replacing the common RAM of the configuration of claim 2 with a FIFO memory, it is possible to delete the address information that was transferred by the common RAM in the configuration of claim 2. It is possible and the circuit is simplified.

In the configuration of claim 4 of FIG. 4, the CPU directly writes the logging information to the logging information storage unit (10), but after the CPU alarm occurs, the CPU
The bus control unit disconnects the bus after the alarm occurs so that the data will not be destroyed by accessing the logging information storage unit (10).

The configuration of claim 5 in FIG. 5 is carried out for logging of an abnormal factor, while claims 1 to 4 are carried out for collecting logging information of the history of processing of the CPU. When an interrupt occurs, the CPU writes to an SRAM having a backup power supply provided separately from the main memory to improve the reliability of the write cycle,
After that, the CPU resets itself. In this case, if the configuration is made up of only registers, the reset will continue to take place. Therefore, the timer circuit is made to reset only for a certain period of time. Also, after reset, the CPU
When writing a factor to M, in order to prevent overwriting to the previously written area, the factor presence / absence register (14)
And the CPU writes the factor to the SRAM,
Set the display bit in the factor presence / absence register (14). After the reset, if the display bit is set, writing is not performed to prevent overwriting.

[0014]

[Embodiment] FIG. 6 shows a structure of an embodiment corresponding to claim 1. The common RAM is composed of Dual Port RAM, and the logging information storage section (10) is composed of EEPROM of nonvolatile memory. The CPU includes a power-on reset circuit and a ROM containing software.

FIG. 7 shows the configuration of an embodiment corresponding to claim 2, wherein the common RAM is composed of Dual Port RAM, the logging information storage unit (10) is composed of EEPROM of a non-volatile memory, and data transfer is performed. The control unit includes a timing control circuit for inputting an alarm signal and a clock counter circuit.

FIG. 8 shows the configuration of an embodiment corresponding to claim 3, and a FIFO memory is used instead of the Dual Port RAM of FIG. FIG. 9 shows the configuration of an embodiment corresponding to claim 4, wherein the bus control unit is provided with a latch circuit which receives an alarm signal input and outputs of a data register and an address register from the main memory unit and the auxiliary memory unit. , A buffer which controls the bus by using the output as an enable signal.

FIG. 10 shows a configuration of an embodiment corresponding to claim 5, and when an interrupt occurs, the CPU writes to an SRAM having a backup power source different from the main memory unit, and then writes to itself. Apply a reset. In this case, in the one-shot pulse generator of the timer circuit (13),
Make sure that the reset is applied only for a certain period of time. After the reset, when the CPU writes the interrupt factor to the SRAM, in order to prevent the previously written area from being overwritten, the factor is written to the SRAM and displayed in the factor presence / absence register (14). Set a bit After resetting, if the display bit is set, writing is not performed to prevent overwriting.

[0018]

As described above, according to the present invention, C
When the CPU system is installed in an unmanned station, it is possible to obtain logging information when the PU system is abnormal, and to restart the system immediately without any human work. The effect of speeding up the cause analysis of the abnormal occurrence of is obtained.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a logging information collecting method in a CPU system according to claim 1 of the present invention.

FIG. 2 is a principle diagram showing a configuration of a logging information collecting method according to claim 2 of the present invention.

FIG. 3 is a principle diagram showing a configuration of a logging information collecting method according to claim 3 of the present invention.

FIG. 4 is a principle diagram showing a configuration of a logging information collecting method according to claim 4 of the present invention.

FIG. 5 is a principle diagram showing a basic configuration of a method of collecting logging information of an interrupt factor to a CPU according to claim 5 of the present invention.

FIG. 6 is a configuration diagram of an embodiment corresponding to claim 1 of the present invention.

FIG. 7 is a configuration diagram of an embodiment corresponding to claim 2 of the present invention.

FIG. 8 is a configuration diagram of an embodiment corresponding to claim 3 of the present invention.

FIG. 9 is a configuration diagram of an embodiment corresponding to claim 4 of the present invention.

FIG. 10 is a configuration diagram of an embodiment corresponding to claim 5 of the present invention.

FIG. 11 is a configuration diagram of a logging information collecting method in a conventional CPU system.

FIG. 12 is an operation flow diagram of a conventional logging information collection method.

[Explanation of reference symbols] is a main CPU, is a reset circuit, is a ROM, is a main memory unit, is an auxiliary memory unit, is an I / O port, is an external terminal, is a common RAM or FIFO memory or a bus control unit, and is a sub CPU Or data transfer control unit, (10)
Is a logging information storage unit, and (11) is an abnormality detection unit.

Claims (5)

[Claims] 1. A common RAM (8) for simultaneously writing and reading logging information from a main memory (4) by a main CPU (1) on a system bus (100) of a CPU system, and a common RAM (8) The logging information storage unit (10) of the non-volatile memory to which the data is transferred, and the logging information storage unit (10) of the data of the common RAM by the program in its own ROM.
When the CPU system becomes abnormal, the logging information of the processing progress by the main CPU (1) up to that time is not cleared, and the logging information storage section ( A method for collecting logging information in a CPU system, characterized by being stored in 10). 2. The main CPU instead of the sub CPU (9)
When (1) detects a system error in the error detection unit (11), it generates the data transfer timing control signals (c1, c2),
By that time, the logging information written in the common RAM (8) is read and the logging information storage unit (10) of the non-volatile memory is read.
2. The method for collecting logging information in a CPU system according to claim 1, further comprising a data transfer control unit (9) for transferring data to the. 3. Instead of the common RAM (8), normally, writing from the CPU (1) is sequentially accepted, and the updated output is sent to the logging information storage unit (10) by hardware. Main CPU (1) with FIFO memory (8)
Is detected by the abnormality detection unit (11),
Timing control signal (c
2. The collecting of logging information in the CPU system according to claim 1, wherein the writing input to the FIFO memory (8) is disabled by 1, c2) and the logging information of the output is held without being updated. Method. 4. The system bus (100) is set to an enable state in which writing from the CPU (1) can be normally performed, and in the event of an abnormality, data cannot be immediately written even if the system is next restored. Bus control part (8) to be in a state, and CPU (1) until an error occurs
And a logging information storage unit (10) of a non-volatile memory for storing the processing information of the logging information storage unit (10) even if the CPU (1) is reset again and the main storage unit (4) is cleared. 2. The method for collecting logging information in a CPU system according to claim 1, wherein the logging information is held without being cleared. 5. In the CPU system, a power backup unit (9) prepared in advance for power interruption, an SRAM (8) backed up by the power backup unit, and a CPU
Interrupt factor detector that notifies (1) that an interrupt factor has occurred.
(2), an interrupt factor register (11) that sends detailed information of interrupt factors to the CPU (1), a reset register (12) to which the CPU can write, and data to the reset register (12). The CPU (1) is provided with a timer section (13) that operates for a fixed time when is written, and a factor presence / absence register (14) that indicates whether or not interrupt information is logged in the SRAM (8). ) Reads out the contents of SRAM (8) and recognizes that it is the interrupt information, CPU (1) writes a reset signal to the reset register (12) to notify itself (1). A method of collecting logging information in a CPU system, characterized by resetting and restarting.