JPH096651A - Scsi tracer device - Google Patents

Abstract

PURPOSE: To extremely facilitate the analysis of an error without erasing the trace data on the immediately preceding error when a system reset signal is supplied by preparing two memories to store exclusively and alternately the trace data in response to the system reset signal. CONSTITUTION: An SCSI tracer control circuit 10 collects the trace data through an SCSI bus and exclusuvely and alternately generates the signals CS1 and CS2 in response to the supply of a system reset signal. Furthermore, a RAMa 20 is added to successively store the trace data supplied in response to the supply of the signal CS1 at and after the head of a storage area and then to start again this data storing operation when the storage area is filled with the data, together with a RAMb 30 which successively store the trace data in response to the supply of the signal CS2 at and after the head of the storage area and then starts again this data storing operation when the storage area is filled with the data.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to SCSI tracer devices.

[0002]

2. Description of the Related Art In a peripheral control device for controlling a peripheral device by SCSI (Small Computer System Interface), all control signals and data values on the SCSI are stored, and when the storage area is exhausted, the head storage area is restarted. By having a so-called SCSI tracer device that stores endlessly, a so-called SCSI tracer device facilitates the analysis of the movement of the phase on the SCSI until and at the time of the failure and the data, that is, the instruction to the peripheral device, Particularly, a technique capable of solving a problem such as intermittent failure in a short time is disclosed in Japanese Patent Laid-Open No. 5-67026.

Therefore, this SCS is used as a countermeasure against a failure.
It is becoming possible to find a device in which the I-tracer device is built in the same housing together with the computer main body and operated by the same power supply.

In a general device, when an error occurs at system startup due to power-on, a system reset signal is automatically or manually supplied to each part to restore the initial state in order to avoid troubles due to accidental failure or the like. Let's start again.

FIG. 3 shows a conventional SCSI tracer device 33.
A block diagram showing the configuration of is shown.

A conventional SCSI tracer device 3 shown in FIG.
3 is a RAM 200 for storing trace data, and S
SCSI tracer control circuit 100 for receiving trace data from CSI and writing it in RAM 200
It is connected to the CSI control circuit 400.

The SCSI controller 32 having the SCSI tracer device 33 and the SCSI control circuit 400 is connected to the host device 31 via the host bus and to the SC device via the SCSI bus.
It is connected to the SI device 34.

In the conventional SCSI tracer device 33, when a power-on system starts up, a SCSI error occurs and a system reset signal for retry is supplied from the host device 31.
The tracer device 33 resets the memory holding the trace information, that is, initializes the write address in order to return to the initial state.

[0009]

The above-described conventional SCS
The I tracer device is SC when the power is turned on.
When an error occurs in SI and the system reset signal is supplied, the memory that holds the trace information is reset. Therefore, when restarting, the storage location of the trace data when the error occurs is reset. There is a problem that the SCSI trace information at the time of error cannot be saved and collected because it becomes unclear and overwrite occurs due to the trace data upon restart.

An object of the present invention is to prepare two memories for storing trace data, and switch the memories for storing trace data to each other when a system reset signal is supplied. An object of the present invention is to provide a SCSI tracer device capable of easily analyzing error contents by making it possible to save and collect trace data of SCSI in which an error has occurred.

[0011]

According to a first aspect of the present invention, a SCSI tracer device collects trace data from a SCSI bus and excludes a first signal and a second signal in response to supply of a system reset signal. Generated by alternately switching
In response to the supply of the first signal, the CSI tracer control means stores the trace data supplied from the SCSI tracer control means in order from the beginning of its own storage area, and when the storage area becomes full, a new one is stored. First storage means for storing the trace data supplied from the SCSI tracer control means in response to the supply of the second signal, in order from the beginning of the self storage area, and the storage area When it is full, it has a second storage means for newly storing from the beginning.

The SCSI tracer device of the second invention is the SCSI tracer device of the first invention, wherein the SCSI tracer control means is responsive to the decoder for decoding the sampled system reset signal and the supply of the output of the decoder. It is configured to include a flip-flop that exclusively and alternately switches and outputs the first signal and the second signal.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the SCSI tracer device of the present invention.

As shown in FIG. 1, the SCSI tracer device 3 of this embodiment collects the trace data from the SCSI bus and outputs the signal C in response to the supply of the system reset signal.
SCSI for exclusively and alternately generating S1 and signal CS2
The tracer control circuit 10, the RAMa 20 which stores the trace data supplied in response to the supply of the signal CS1 in order from the beginning of the storage area, and newly stores it from the beginning when the storage area is full, and the signal CS2. Of the trace data supplied in response to the supply of data from the beginning of the storage area, and newly storing from the beginning when the storage area is full. Is connected to a SCSI control circuit 40 which is a peripheral control device or the like.

The SCSI control unit 2 having the SCSI control circuit 40 and the SCSI tracer device 3 is composed of a host device 1 such as a computer via a host bus and a magnetic disk device, tape device, printer or the like via the SCSI bus. It is connected to a certain SCSI device 4.

An example of the structure of the SCSI tracer control circuit 10 is shown in FIG.

The SCSI tracer control circuit 10 of FIG.
Buffer 13, decoder 11, flip-flop 1
2 is included.

The signal flowing from the SCSI bus to the RAMa 20 and the RAMb 30 is fetched via the buffer 13 and supplied as trace data to the RAMa 20 and the RAMb 30.
The system reset signal supplied is decoded by the decoder 11 to generate a decode signal 16.

When one specific interface line different from the others is assigned for the system reset signal, this decoder 11 becomes unnecessary and the signal of the specific interface line is transferred through the buffer 13 to It is supplied as a drive signal for the next flip-flop 12 in place of the decode signal 16 of.

The flip-flop 12 is a flip-flop (for example, a T-type flip-flop) that changes its internal state by using the supplied decode signal 16 as a trigger, and the signal line 17 receives the decode signal of the first system reset signal to output 2 If one value of the value signal, for example "1", is output, "0", which is the other value of the binary signal, is generated by the decoding signal of the next system reset signal.
After that, one value and the other value of the binary signal are exclusively and alternately output to the signal line 17 every time the decode signal of the system reset signal is supplied.

Then, one value of the binary signal is set to the signal CS1.
As the signal CS2 and the other value of the binary signal as the signal CS2.

Next, the operation of the SCSI tracer device 3 of this embodiment will be described.

In the system connected as shown in FIG. 1, when power is turned on and system startup is started, the SCSI tracer control circuit 10 monitors the signal of the SCSI control circuit 40 and is first supplied. system·
It is assumed that the reset signal is introduced and the signal CS1 is generated, for example.

In response to the supply of the signal CS1, the RAMa 20 stores trace data such as control signals and data (instructions to peripheral devices) on the SCSI bus, which are subsequently supplied via the SCSI tracer control circuit 10, in the storage area. The data is stored in order from the beginning. When the storage area is filled with the supplied trace data, the supplied trace data is newly stored from the beginning of the storage area, and the storage operation is continued endlessly. In this way, by holding the trace data from the time of failure occurrence to a certain period before, it is useful for failure analysis.

When operating in the above state, the signal CS
Since 2 has not been generated, the RAMb 30 to which the signal CS2 is not supplied cannot store the trace data even if the trace data is supplied.

In the above case, the system startup is successful and enters the normal operation state. The case where the SCSI error occurs during system startup and the system startup fails will be described.

In such a case, as described above, the system reset signal is manually or automatically supplied from the host device 1 to restore the initial state and restart.

When the system reset signal for this restart is supplied from the host device 1, the SCSI tracer control circuit 10 takes in this signal, and this time stops the generation of the signal CS1 and outputs a signal different from the signal CS1. Generate CS2.

In response to the supply of the signal CS2, the RAMb 30 stores in the storage area trace data such as control signals and data (instructions to peripheral devices) on the SCSI bus which are subsequently supplied via the SCSI tracer control circuit 10. The data is stored in order from the beginning. When the storage area is filled with the supplied trace data, the supplied trace data is newly stored from the beginning of the storage area, and the storage operation is continued endlessly.

On the other hand, since the supply of the signal CS1 to the RAMa 20 is stopped, the trace data storing operation is stopped at this point. In this state, the RAMa20 sends the signal CS
The trace data supplied from the supply of 1 to the stop of the supply, that is, the trace data from the system startup to the system startup failure is stored and saved. When the system is started up normally, the trace data stored and saved can be analyzed to analyze the error when the system is started up.

As described above, the SCSI of this embodiment
In the tracer device, two memories for storing the trace data are prepared, and in response to the supply of the system reset signal, the memory is alternately switched to the trace data to store the trace data. When supplying the
This has an effect that data can be retained without being lost and error analysis can be facilitated.

[0033]

As described above, the SCSI of the present invention
The tracer device prepares two memories for storing the trace data, and in response to the supply of the system reset signal, switches the memory exclusively and alternately to store the trace data. Even when supplied, the trace data relating to the immediately preceding error can be retained without being lost, and there is an effect that the error analysis can be significantly facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a SCSI tracer device of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a SCSI tracer control circuit.

FIG. 3 is a block diagram showing a configuration of a conventional SCSI tracer device.

[Explanation of symbols]

 1, 31 Upper device 2, 32 SCSI control unit 3, 33 SCSI tracer device 4, 34 SCSI device 10, 100 SCSI tracer control circuit 11 Decoder 12 Flip-flop 13 Buffer 20 RAMa 30 RAMb 40, 400 SCSI control circuit 200 RAM

Claims (2)

[Claims] 1. A trace data is sampled from a SCSI bus and is responsive to the supply of a system reset signal to exclusively and alternately generate a first signal and a second signal.
In response to the supply of the first signal, the CSI tracer control means stores the trace data supplied from the SCSI tracer control means in order from the beginning of its own storage area, and when the storage area becomes full, a new one is stored. First storage means for storing the trace data supplied from the SCSI tracer control means in response to the supply of the second signal, in order from the beginning of the self storage area, and the storage area And a second storage means for newly storing the data from the beginning when the SCSI tracer device is full. 2. The SCSI tracer control means is a system
A decoder for decoding a reset signal, and a flip-flop that exclusively and alternately outputs the first signal and the second signal in response to the supply of the output of the decoder. 1. The SCSI tracer device according to 1.