JPS63259720A - Floating point multiplication circuit - Google Patents

Abstract

PURPOSE:To rapidly process overflow of digits by providing an overflow detecting part in a mantissa or an exponent part, and driving an overflow correcting circuit for the operated output according to the detection signal of it. CONSTITUTION:In an operation circuit I, the signals l1, l2, corresponding to the mantissa, are added to a multiplying circuit 1, and a multiplication result l5 is outputted, and the signals l3, l4, corresponding to the exponent are added to an adding circuit 2, and an addition result l6 is outputted. An exponent overflow detecting circuit 4 outputs the signal CMO showing an exponent high- order overflow, and the signal CMU showing an exponent low-order overflow. The operation circuit I executes an exponent correction, due to a floating point multiplication and the exponent high-order overflow, and the correction of the mantissa, and the operation circuit II executes the correction of the exponent and the mantissa due to the exponent low-order overflow. Thus, the overflow can be processed rapidly without being processed by a program processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating-point multiplication circuit, and more particularly to a floating-point multiplication circuit used in a high-speed digital signal processor for real-time processing of data with a wide dynamic range (maximum possible amplitude of data). It is something.

The floating-point multiplication circuit is composed of a fixed-point multiplier dedicated to mantissa operations and an adder dedicated to exponent operations. In other words, the two numbers to be multiplied are A +-= M□・2°1 and A2
=M2・2°2, the multiplication result is A=A,・A2
=M1·M2·2°1+02, and multiplication of M,·M2 and addition of el+e2 are performed. Here, Ml and M2 are mantissas and ei+82 is an exponent. In floating-point multiplication, the two-manual mantissa is normalized to maintain the maximum number of significant digits. When these multiplication circuits are constructed from binary digital circuits, the number of bits in the mantissa and exponent parts is specified for convenience in circuit configuration.
Since the multiplication result, that is, the product, must also be expressed by a fixed number of digits, the problem of overflow and underflow occurs.

Also, when normalizing the multiplication result, moving the mantissa and adding or subtracting the exponent by that amount, overflow may occur even when the exponent does not fall within the range represented by the normal number of bits. A problem arises.

Conventionally, when overflow (overflow, underflow) occurs in the mantissa and exponent parts, a flag has been used to detect the occurrence, and a program has been used to process the correction. Therefore, it takes a considerable amount of time to execute a program for processing overflow, and there is a drawback that high-speed calculation cannot be performed. In particular, in devices such as communication devices that require real-time processing, that is, input and output must be performed in the same time relationship, even higher-speed signal processing devices are required, and in particular, multipliers that require time are required to be faster. .

Therefore, an object of the present invention is to realize a floating point multiplication circuit that can process overflow in floating point multiplication at high speed without performing program processing.

Another object of the present invention is to realize a circuit that quickly handles overflow that occurs in floating point multiplication.

In order to achieve the above object, the present invention provides a multiplication circuit for two floating point numbers consisting of a mantissa and an exponent of a fixed number of bits, and provides an overflow detection section for the input or output mantissa or exponent. The present invention is characterized in that the signal is configured to drive an overflow correction circuit for arithmetic output.

The present invention will now be described in detail with reference to the two drawings. First, before explaining embodiments, the principle of the present invention will be explained. Figure 1 shows two numbers A1゜A2 to be multiplied and their product A
It shows the composition of =A□・A2, where the mantissa of the number of customers is M and the exponent is e, which is A, =M1・2°' HA
2 = M 2・2°2. It is expressed as A=M·2° (true value). The suffix of each symbol distinguishes the number of customers. In floating point multiplication, two numbers A1. Mantissa M1 of A2.
M2 is normalized to maximize the effective number, and when a binary number is expressed in two's complement representation, -2°≦M1, or M2<2-1, or 2″1≦M1.or M2×2. °
Also, due to the configuration of the multiplication device, the number 1 representing the mantissa M and the exponent e is
〜numbers have constant bit numbers m and n (A in Fig. 1)
1. In the case of A2, m=11 n=4). Therefore, 2 numbers A1. It will look like the one shown in A2. These two numbers A1. The product of A2 is expressed by a 23-bit mantissa and a 4- or 5-bit exponent if no restrictions are placed on the bit configuration. However, due to the configuration of the circuit and device, A in FIG.

In an actual device, the number A is 1.2Mo.2°0. A
Same bit configuration as 2 (mantissa m bits, exponent n bits)
It is said that Therefore, overflow occurs as described below.

(1) Product A of two normalized numbers A, , A2 overflowing the upper digits of the exponent. The mantissa M. is (a
) non-normalized state, i.e. -2-1≦Mo≦-
2-2 (b) There are two normalized states, namely -2°≦Mo(-2''1).

Therefore, when the index e becomes 2n-1, the following problem occurs. Generally, in state (a) where the mantissa is not normalized, the mantissa is M. Shift left by 1 bit and specify e. It is normalized by subtracting 1 from , and the exponent e. When is greater than or equal to 2°-1, the mantissa M. Regardless of the state of , the product A. It is conceivable to perform a correction that maximizes the absolute value of the mantissa M. is not normalized (a), and the index e. is 2n
In the case of -1, if the above correction is performed, a large error will occur due to the correction. For example, the exponent is e if n=4 bits. =24
-1=8, mantissa M. -2-2 (non-normalized example)
, then the true product A. is A. = (-2-2) X21+
= -26, and the product A when the above correction is performed. ′
is A. '=(-2°)X27=-27, which is the true value Ao
The incorrect value is twice that of .

(2) When the true value of the exponent of the product is less than 12n-1, it is assumed that the lower digits are overflowed, and the correction can be made by approximating the exponent to 21-1 without performing a shift. Dynamic range cannot be used effectively.

(3) Mantissa overflow 2 number A1. Even though the true value of the product is 1 when both A2 are -1, if the calculation is performed using two's complement representation, the product will be a binary number of 1.0000... and the MSB will be 1.
11'', the value is incorrectly interpreted as -1.

The floating-point multiplier of the present invention solves the above-mentioned overflow problem.
2) A circuit that detects each digit misalignment, and when a digit misalignment is detected, it is corrected without program processing using a correction circuit that has the following functions.

If the mantissa part M is not normalized and the exponent part becomes 2 TI -1, shift the board number part M to the left (raise the digits), set the exponent part to the maximum value that can be displayed, 2n-1,1, and display the exponent. co=21
-1 and the mantissa is normalized, or the exponent e.

〉2″-1, the sign of the mantissa is not changed and the absolute value is set to be the maximum.

When the exponent part is less than 12n-1 (the index overflows the lower digits), the true exponent value e is calculated from the minimum displayable value of the exponent part -2n-1.
The mantissa is shifted to the right (downward) by (eo-e) bits. By this correction, the dynamics range is expanded by the effective bit 1 to length m bits of the mantissa.

When the mantissa part causes overflow, that is, 2 numbers A1. A
When both 2 are -1, the first method shifts the mantissa to the right by 1 bit and adds 1 to the exponent.

In addition, the second method sets the mantissa to 2° 2-(m-11,
No correction is made to the exponent part. Although the second method includes an error of 2-15, it is more advantageous than the first method in terms of circuit configuration because it can be shared with the exponent overflow correction circuit used as another arithmetic circuit.

FIG. 2 is a block diagram showing the configuration of an embodiment of a floating point multiplication circuit of the present invention constructed based on the above principle.

This embodiment is composed of first and second arithmetic circuits I and (2). The first arithmetic circuit I is a circuit that detects floating point multiplication and overflow, and performs exponent correction and mantissa correction due to overflow of the upper digits of the exponent. The second arithmetic circuit (2) is a circuit that corrects the exponent and mantissa due to overflow of lower digits of the exponent. In this embodiment, the circuit for correcting the overflow of the lower digits of the exponent, that is, the second arithmetic circuit (2) performs an arithmetic operation between the output of the first arithmetic circuit I and another input A3 (consisting of the mantissa Q9 and the exponent Q10). It also serves as an arithmetic circuit.
It is also designed to be able to perform floating point multiplication and fixed point operations. The operation of each circuit configuration will be explained below.

In the arithmetic circuit (2), the 12-bit mantissas corresponding to mantissas M1 and A2 in FIG. 1 are input signals Q, respectively.

and is added to the multiplication circuit 1 as Q2, and the multiplication result Q5
Output. On the other hand, 4-bit exponents corresponding to exponents e1 and Q2 are respectively applied to the adder circuit 2 as input signals Q3rA4, and the addition result Q6 is output. Since these input and output signals are expressed in 4-bit two's complement representation, there are restrictions such as -8≦Q3+Q4+Q and 6≦7.

4 is a circuit for detecting overflow of exponent digits and correcting the exponent when the upper digits of the index are overflowed, which includes a detection signal C8 for detecting when the exponent is 8, a signal CMo representing overflow of the upper digits of the index, and a signal cMu representing overflow of the lower digits of the index. Output.

Reference numeral 14 switches between floating-point multiplication and fixed-point multiplication in response to control signal B, and is provided so that the circuit of this embodiment can also be used as a fixed-point arithmetic circuit.

FIG. 3 shows the circuit configuration of the adder circuit 2, the exponent overflow detection circuit 4, and the switching circuit 14. In the same figure, Q3 2
3. Q322. Q32” and Q9-2° are input A
4-bit signal with index e of 1, ρ4-23. Ω, -2
2, Q14-2' and A4-2° are the exponents e of input A2
Q6-23, Q6-22 .
Q6-21 and Q6-20 represent the output of adder 2, and Q3 represents a carry signal from Q6-22 to Q6-23. The OR circuit 1.6 and the AND circuit 17 are circuits that detect that the exponent e of the product is 8 or more.
MO= (Q, 323) + (A4-23) ・Q3)
The output CMo becomes II i TT.

AND circuit 18 and AND circuit 19 are circuits that detect when the exponent e is less than 18, and when Q3-23 and A4-23 are "1" and Q3 is LL O, the output C□ is "1". The AND circuit 20 is a circuit that detects that the index e is 8, and when CMo is 1'', Q6-22. Q6-21.
When all Q6-2° are 1101+ (i.e. CM.・
(Q6-22), (Q6-21), Q6-2° is “1”
) Outputs “1”. AND circuit 21, OR circuits 22, 23, and 24 set the exponent to e when the exponent e is 8 or more.

=110111''.The floating-point arithmetic and fixed-point arithmetic switching circuit 14 is used when changing the arithmetic format, and the control signal B is corrected when the floating-point arithmetic is performed.
111'', turns on the AND circuits 25, 26, and 27, and passes the signals of CMu, C, o, and C8.

FIG. 4 is a circuit diagram of the mantissa correction circuit 3 of FIG. 2. As inputs, the signals C, . . . , C8 shown in FIG. , the 16-bit signal Ω5-2 which is the output of the mantissa multiplication circuit 1
°, C5-2-'...C5-2-15 is added. Logic circuit 29 includes inverters 30, 33, 35 . Exclusive OR 31, 39. NAND circuits 32, 37. Noah circuit 3
4.3B, consists of an OR circuit 36, which determines various states of multiplication results, and AND gates 41, 42 . ...Turn 44 on and off. The ona circuits 51...54 take out the output of the AND gate and corrected mantissa Q7-2"',
ρ7-2-2. ．． ．． Q, 2-15. The output Q7-2° of the inverter 40 becomes the MSB signal of the mantissa.

With the above circuit, a multiplication output other than the overflow of the lower digits of the exponent can be obtained. Each case will be explained separately below. exponent e is 8
In the above case, the output CMo of the OR circuit 17 in FIG.
2', Qa 2') becomes "0111" (+7).

As for the mantissa part, since CMo is LL I ++ in FIG. 4, the NAND circuit 37 becomes "1", and the AND gate 41
-1.42-1゜44-1, MSBQ, 5-
0.1 when 2' is 170 ++ or 1", respectively.
The value has the maximum absolute value, such as 1111...1 or 1.000...0.

However, if the exponent e is 8 and the mantissa is not normalized, that is, CMo, CB, is tr 1 ++ and Q, 5-20
When the signs of C5-2-'' and C5-2-'' are the same, the logic circuit 29 turns on the ant games 1-41-3, 42-3, . . . and shifts the mantissa part to the left by one bit.

When the exponent e is 18≦e<7, no overflow occurs and the output α6 of the adder 2 in the exponent part becomes the output Q8 (C8-2
3, C8-22...C8-2°), and the mantissa part is normalized (if not, normalization processing is performed).

Overflow occurs, but this detection is performed by the NAND circuit 32 in FIG. 4, and (Q, -2°)・C02-2
When it is detected that (C5-2°) becomes II I ++, the mantissa correction output Q7-2°.

C72-2+...Ω 2-15 is “0.1.1
11...1''' (=2° 2/15).Next, we will explain the case of overflowing the lower digits of the exponent.The overflowing of the lower digits of the exponent is corrected by using the second arithmetic circuit ■ in Figure 2. Input A3
This is done in the middle of the calculation. In Fig. 3, when the lower exponent digit overflow occurs, CMu becomes '1'', and the exponent lower digit overflow exponent correction circuit 6 in Fig. 2. The index comparison correction circuit 12 when the index lower digit overflow occurs, the index lower digit overflow occurs. It is added to the pre-calculation cloth shift correction circuit 8 and the exponent part calculation input bus switching circuit 13.

The mantissa Q9 of the other input A3 is sent to the mantissa calculation input bus switching circuit 5, and the exponent QiO is sent to the switching circuit 13. Index comparison circuit 11. Furthermore, the exponent output Qe (=eo) of the arithmetic circuit (2) is applied to the exponent correction circuit 6. The switching circuit 13 supplies the larger of the two indices to another arithmetic circuit or an output terminal (not shown). The comparator 11 compares the two indexes. The index comparator circuit 12 corrects the output Q17 of the comparator circuit 11 when the lower digits of the index overflow, generates a control signal nta when the lower digits of the index overflow occur, and outputs the input signal (mantissa) C7 of the input bus switching circuit 5. is the output signal ρ1. In addition to the pre-calculation cloth shift circuit 9, the input bus switching circuit 13 outputs the input signal ρ1o as an output, thereby controlling the subtraction circuit 7. Index correction circuit 6. Subtraction circuit 7. Right shift correction circuit 8
determines the right shift amount of the mantissa, as explained in detail in FIG.

15 is a switching circuit between floating point arithmetic and fixed point arithmetic;
This is a 10 fixed point subtraction circuit.

Now, the exponent of the output of the arithmetic circuit I is β=(β3β2β1β.

) and the true value of the exponent part is e. Note that β is the output in the case of overflow of lower digits. Also, let the exponents of other inputs be α=(
C3, C2, C1, α. ) (This signal is Ql.

).

Overflow of lower digits of the exponent occurs when T3·CMu="l'". At this time, in 4-bit two's complement representation, e
Since <−8 and β≧O, e<β. Therefore, CM
When u is 1, β is smaller than e, so correction is performed by the exponential comparison correction circuit. In order to align the exponents of two-manpower (α−
e), and α−e can be expressed as α−e−α−(−16+β) =(α+8)−(−8+β) (3). Here, α and β are -8≦α≦7− (4), o≦β≦7... (5) 0≦
α+8≦15 (6).

-8≦-8+β≦-1... (7) Since there is a condition, the following inequality holds α+7〉-8+
β...(8)1≦α-e≦23...
・(9) On the other hand, input data 1 to the mantissa right shift circuit 9
3 must be limited by O≦Q13≦15, so the following correction is necessary.

When a −e < 16 Q13= a −e −(
10) When a −e < 16, nx3=15 −(
11) When the above formula is expressed in logical symbols for the circuit configuration, (3
) formula (α+8), (-s + β) is (α+8)=((α
3■1)α2α1α. )=((C3:Mu)α2α
, α. )...(12) (-8+β)=((1+0)β2β1β.)=((β
3+CMu) β2β1β. )...(13) Also, finding the condition C for equations (10) and (11), x=(C3 of CMu) -C3-(14)y=(CMu
+β3) =O=・(15), then C= (x−y+(x■y)・C2) −C, u−(
16)=χ・C2・CMu−(17).

FIG. 5 shows an example of an exponent overflow circuit in floating point multiplication constructed based on the above principle, and each block 6
．． 7, 8, 12, and 15 correspond to the second portions with the same numbers. In the figure, signal QB 23. Qa-2
2, Qg 2'HQB 2° is the above β3. β2.
β3. To β0, 110 23t 21022+ Q□
o 2'+ (A1o2° is the above α3.C2°C1,
α. corresponds to Exclusive OR 55 is C3■ of formula (12)
After executing question C, the OR circuit 56 is β3+CM of equation (14).
Execute u. The comparison correction circuit 12 turns on the switch S1 when =16-CMu is "1", and turns on the switch S2.
is turned off and the signal Q18 is set to "O". When C□ is "O", this is reversed and 018 becomes fli7.

The subtraction circuit 7 outputs α−〇, but the right shift correction circuit 8
, the AND circuit 57 judges the condition C of the above equation (17), and if the shift is larger than 16, then 111''
Output. Therefore, when α-e is ≧16, 15 is set as the shift signal Q13, and when α-e is less than 16, α-e is set as C3.

The above explanation has been about the case where the correction of the overflow of lower digits of the exponent is performed during addition and subtraction with other input data A3, but 2 input data A1. If it is desired to directly take out the multiplication result of A2 as the output of the second arithmetic circuit (2), the data of the mantissa part Q9 of the other input signal A3 should be O11, and the data Q1o of the matching number should be set to -8. In other words, (00...0) Product A of A2
. is found.

[Brief explanation of drawings]

FIG. 1 is a bit configuration diagram of input data in floating point multiplication, FIG. 2 is a block diagram showing the configuration of an embodiment of a floating point multiplication circuit according to the present invention, and FIG. 3 is an adder circuit 2 and an exponent in the above embodiment. Overflow detection circuit 4, switching circuit 1
4 is a circuit diagram of the mantissa correction circuit 3 of FIG. 1, and FIG. 5 is a circuit diagram of blocks 6.7 and 8.15 of FIG. 1. DESCRIPTION OF SYMBOLS 1... Multiplication circuit, 2... Addition circuit, 3... Mantissa correction circuit, 4... Exponent overflow detection circuit, 5... Mantissa calculation input bus switching circuit, 6... Exponent correction circuit, 7.
... Subtraction circuit, 8... Right shift correction circuit, 9... Right shift circuit, 10... Fixed-point addition/subtraction circuit, 11...
- Index comparison circuit, 12... Comparison correction circuit, 13... Index calculation input bus switching circuit, 14. ．． 15...Floating point arithmetic and fixed point arithmetic switching circuit.

Claims (1)

[Claims] A detection circuit that detects overflow from a mantissa multiplication circuit or an exponent addition circuit in a digital multiplication circuit that multiplies two-input data in a two's complement floating point representation, and a circuit that corrects overflow using the output of the detection circuit. A floating point multiplication circuit comprising: