JPH0644048A - Floating point arithmetic unit and method - Google Patents

Abstract

PURPOSE:To attain the high speed of the addition/subtraction of a floating point number by executing normalization processing and rounding processing in parallel. CONSTITUTION:A rounding correction determination circuit 8 provided with plural rounding correction judgement circuits 81 corresponding to each of plural rounding position candidates and a selection circuit 82 to select the output of the rounding correction judgement circuits 81 in conformity with the output of a rounding position determination circuit 6 is provided. In this configuration, the output of an adder/subtracter circuit 4 is used as the inputs of the rounding position determination circuit 6, the rounding correction determination circuit 8, and a rounding correction addition circuit 10. Thus, since the adder/subtracter circuit 4 and the rounding correction judgement circuit 81, and the rounding correction addition circuit 10 and a normalized shift number calculation circuit 12 come to be capable of executing the processing simultaneously, the processing time of a whole arithmetic unit is shortened, and the high speed of a arithmetic processing is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic device and method for increasing the operation speed of floating point numbers.

[0002]

2. Description of the Related Art As a method of expressing a floating point number on a computer, for example, IEEE-754 as shown in FIG. 7 is used.
There are standard formats defined in. As a conventional device for adding and subtracting two floating point numbers expressed in this type of format, there is one described in Japanese Patent Laid-Open No. 2-232723.

The device disclosed in the above publication is constructed as shown in FIG. The digit matching circuit 2 inputs two floating point numbers to be added and subtracted, that is, operands 1 and 2, and shifts the mantissa part of one operand to the lower side so that both exponent parts are equal. The data output from the digit alignment circuit 2 is input to the addition / subtraction circuit 24. Adder / subtractor circuit 24
Performs addition or subtraction of the mantissa part after digit alignment according to the distinction between the addition type instruction and the subtraction type instruction, the sign of the operand, the magnitude relation, and the like. The output of the adder / subtractor circuit 24 is input to the normalization circuit 26.

The normalization circuit 26 searches for the most significant digit of the mantissa after addition and subtraction, that is, the digit in which 1 appears first from the upper bit, and shifts the mantissa so that the decimal point is immediately to the right of that digit. At the same time, the exponent part is corrected according to the number of shifts. The output of the normalization circuit 26 is input to the rounding circuit 28.

The rounding circuit 28 shortens the number of bits of the mantissa part of the normalized data to the number of bits that can be expressed when the number of bits of the mantissa exceeds the range that can be expressed in a predetermined format. Specifically, rounding up (+1 addition is required) or rounding down (+1 addition is not required) is performed on the bits that cannot be expressed on the lower side according to the value of those bits and a predetermined rounding mode.

[0006]

However, in the above-mentioned conventional technique, since the rounding process is performed by using the data after the normalization process, the whole processing time becomes long, and the addition and subtraction of the floating point number is performed. Is a hindrance to doing at high speed.

It is an object of the present invention to provide a floating point arithmetic unit and method for speeding up addition and subtraction of floating point numbers by performing normalization processing and rounding processing in parallel.

[0008]

In order to achieve the above-mentioned object, the present invention adopts a digit aligning means for taking in two floating point operands and digit aligning the mantissa parts of both operands, and the digit aligning means after digit aligning processing. Addition / subtraction means for adding or subtracting the mantissa part of both operands, and shifting the mantissa part so that the newly added or subtracted most significant digit is at a predetermined position, and the exponent part according to the number of shifts. And a normalization means for performing a normalization process for correcting, and a rounding process for reducing the number of digits of the mantissa according to a predesignated rounding mode when the mantissa after addition or subtraction has more than a predetermined number of digits. In the floating-point arithmetic unit including means, a mantissa part before normalization processing is fetched from the addition / subtraction means, a part of the rounding processing is executed using the mantissa part, and then the normalization processing is performed. It is provided with a means for performing parallel processing and rounding processing.

Further, according to the present invention, two floating-point operands are taken in, the absolute value of the difference between the exponent parts of both operands is calculated, and the mantissa part of the operand having a small exponent part is lower by the calculated absolute value. A digit aligning means for shifting the mantissa parts of both the operands to the side, an adder / subtractor means for adding or subtracting the mantissa parts of the both operands after the digit aligning process, and a new uppermost position added or subtracted. The normalizing means that shifts the mantissa part so that the digit becomes a predetermined position and corrects the exponent part according to the number of shifts, and the mantissa part after addition or subtraction are predetermined. When the number of digits is greater than the number of digits, a rounding unit that performs a rounding process that reduces the number of digits of the mantissa according to a predesignated rounding mode is used. Assuming that the shift of the number part is 1 bit to the lower side, 0 bit to the higher side, or 1 bit to the higher side, +1 is added to the mantissa part in the rounding process in each case. Whether rounding correction determining means for determining whether correction is necessary using the mantissa part before the normalization process and shift of the mantissa part in the normalization process are one of the three types Alternatively, based on the rounding position determining unit that determines whether there is any other than the above three types using the mantissa part before the normalization process, and the rounding correction determining unit based on the determination result of the rounding position determining unit,
The normalizing process and the rounding process are performed in parallel by providing a selecting means that makes one of the streets valid or makes all three streets invalid.

The present invention also incorporates any one of the above floating point arithmetic units into a semiconductor device.

Further, according to the present invention, digit alignment processing for taking in two floating-point operands and digit-matching the mantissa parts of both operands, and addition / subtraction processing for adding or subtracting the mantissa parts of both operands after digit alignment processing. And normalization processing that shifts the mantissa so that the new highest digit after addition or subtraction is at a predetermined position, and corrects the exponent according to the number of shifts, and after addition or subtraction If the mantissa part of is greater than the predetermined number of digits, rounding processing to reduce the number of digits of the mantissa part according to a predesignated rounding mode,
In the floating point arithmetic method including, the mantissa part before the normalization process is taken in, a part of the rounding process is executed using the mantissa part, and then the normalization process and the rounding process are performed in parallel. That is.

Further, according to the present invention, two floating-point operands are taken in, the absolute value of the difference between the exponent parts of both operands is calculated, and the mantissa part of the operand having a small exponent part is lower by the calculated absolute value. Shift to the side to perform digit alignment processing for aligning the mantissa parts of both operands, addition / subtraction processing for adding or subtracting the mantissa parts of both operands after digit alignment processing, and addition or subtraction to newly add the highest rank. The mantissa part is shifted so that the digit becomes a predetermined position, and the exponent part is corrected according to the number of shifts, and the mantissa part after addition or subtraction is larger than the predetermined digit number. In this case, in the floating-point arithmetic method that includes rounding processing that reduces the number of digits of the mantissa according to a predesignated rounding mode, the shift of the mantissa during the normalization processing is , 0 bits to the upper side, or 1 bit to the upper side are assumed, and in each case, it is determined whether or not the correction of adding +1 to the mantissa part in the rounding process is necessary. The rounding correction determination process for determining using the mantissa part before the normalization process and whether the shift of the mantissa part in the normalization process is one of the three types or other than the three types are described above. Rounding position determination processing for determining using the mantissa part before normalization processing,
Whether to enable one of the three types in the rounding correction determination process based on the determination result of the rounding position determination process,
Alternatively, the normalization process and the rounding process are performed in parallel by executing a selection process that invalidates all three types.

[0013]

According to the present invention, the rounding correction determination can be performed by using the mantissa before the normalization process by assuming three shift numbers of the mantissa during the normalization process. , It is possible to perform the normalization process and the rounding process in parallel. Further, in the rounding correction determination process, since only the lower-order few bits of the mantissa part are used, the process of the higher-order bits in the addition / subtraction process and the rounding correction determination process can be performed in parallel. In addition, since the rounding correction determination processing circuit can be originally configured with a small number of gates, the increase in the number of gates by increasing the number of circuits to three is negligible. This makes it possible to reduce the overall processing time without complicating the circuit.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the following description, an IEEE-754 double precision format floating point arithmetic unit is shown as an example, but the present invention is not limited thereto.
It is also effective when used in an arithmetic unit that supports other formats (in particular, those that require a relatively complicated rounding process), or an arithmetic unit that simultaneously supports a plurality of these formats.

FIG. 1 is a block diagram showing a schematic configuration of a floating point arithmetic unit according to the present invention. As shown in the figure, the floating point arithmetic unit of the present invention includes a digit alignment circuit 2, an addition / subtraction circuit 4, a rounding position determination circuit 6, a rounding correction determination circuit 8, a rounding correction addition circuit 10, a normalized shift number calculation circuit 12, Normalization shift circuit 14, rounding correction shift circuit 16, exponent correction circuit 18 associated with normalization shift, and 11-bit 2
→ It is composed of one selection circuit 20.

Next, the operation of the floating point arithmetic unit having the above configuration will be described. 2 and Table 1 show details of the digit alignment circuit 2. The digit alignment circuit 2 uses two floating point numbers to be operated, that is, the operand 1 (10
2) and operand 2 (104) are input and the larger of the exponents of both is output (106), and at the same time, the mantissa of the operand with the smaller exponent is placed lower by the absolute value of the difference between the exponents. It is shifted to the side and output as the mantissa part b (110). At that time, the 55th bit after the decimal point is ORed of all the bits shifted out to the lower order than the 54th bit when shifted, and the value is output. On the other hand, the mantissa part of the operand with the larger exponent part is output as it is as the mantissa part a (108).

In the IEEE-754, when a floating point number is calculated, it is assumed that the number of digits of the mantissa is infinite, and then the rounding is performed to obtain the result. However, if the type of operation is addition / subtraction,
Even if the operation is limited to the decimal point and up to the 55th bit as in this embodiment, the result after rounding is as follows.
The same result is obtained assuming that the number of digits of the mantissa is infinite.

[0018]

[Table 1]

FIG. 3 is a detailed block diagram of the adder / subtractor circuit 4. The adder / subtractor circuit 4 inputs the two mantissa parts which are the outputs of the digit alignment circuit 2 and, depending on the type of the instruction to be executed (additional instruction or subtraction instruction) and the sign of both operands, the two Add or subtract. In order to prevent the result from becoming a negative number, in the case of subtraction, the operand with the larger absolute value is subtracted from the operand with the smaller absolute value, and the sign of the result is inverted if necessary.

The two mantissa parts after digit alignment are first input to the inversion / selection circuits 411 and 412. When the subtraction is performed, the mantissa part (the mantissa part of the operand having a smaller absolute value) corresponding to the subtraction is inverted, and the carry input for the least significant bit is set to 1 at the time of addition, and the addition is performed. By adopting such a method, it is possible to perform the +1 addition when taking the 2's complement and the operation between the two operands in one addition. On the other hand, when performing addition, the inversion / selection circuits 411 and 412 do not invert the two mantissa parts and output them as they are.

The outputs of the inversion / selection circuits 411 and 412 are each divided into n + 1 blocks. The carry input adder circuit 43 inputs the lowest block of the n + 1 blocks, regards the signal indicating whether or not to perform subtraction as the carry input from the lower order, performs the addition, and outputs the operation result and the upper block. Output a carry. Each of the n carry-free adder circuits 421 to 42n inputs one of the remaining n blocks, performs an addition assuming that there is no carry from the lower block, and carries out the operation result and the carry ( Carry generation signal) is output. n
Similarly, one of the carry addition circuits 441 to 44n inputs one of the upper n blocks, performs addition assuming that there is a carry from the lower block, and carries out the operation result and the carry (carry to the upper block. Propagation signal) is output.

The carry propagation circuit 45 inputs a carry generation signal and a carry propagation signal from n blocks excluding the uppermost block, and outputs a final carry to the upper n blocks. The selection circuits 461 to 46n are based on the input from the carry propagation circuit 45, and carry-free addition circuit 42.
1 to 42n outputs and carry addition circuits 441 to 44n
Select one of the outputs of. By adopting such a configuration, the time required for carry propagation can be suppressed to be short, so that high-speed addition can be performed.

Select circuits 461 to 46n of upper n blocks
Output and carry input adder circuit 43 of the lowest block
Are added together to obtain the operation result of the adder / subtractor circuit 4 (11
2). At the same time, the lower 5 bits of the output of the carry input adder circuit 43 of the lowest block are rounding correction determining circuit 81.
(114), and the upper 3 bits of the outputs of the carry-free adder circuit 421 and the carry-adder circuit 441 of the highest block are output to the rounding position determination circuit 61 (11
6) Further, of the outputs of the carry propagation circuit 45, the carry signal to the highest-order block is the rounding position determination output selection circuit 62.
Is output to (118).

FIG. 4 is a detailed diagram of the rounding position determination circuit 6. Rounding position candidates include A, B, and
There are four possibilities, C and D. Rounding position determination circuit 61
Reference numerals 1 and 612 determine the rounding positions for the case in which it is assumed that there is a carry to the top block and the case in which it is assumed that there is no carry. The selection circuits 621 to 624 select one of the outputs of the two rounding position determination circuits 611 and 612 depending on whether or not there is a carry to the highest block. With the above-described configuration, it is possible to determine the rounding position at the same time that the calculation result of the uppermost block of the adder / subtractor circuit 4 is output.

[0025]

[Table 2]

Although the present embodiment is an arithmetic unit that performs addition or subtraction of floating point numbers, another example is an arithmetic unit that simultaneously supports type conversion instructions between floating point numbers and integers. Conceivable. In such an example, it may be necessary to perform rounding at a fixed position regardless of the output of the adder / subtractor circuit, only when executing a specific instruction. However, even in such a case, if the circuit of FIG. 4 is slightly modified, it is possible to fix the output of the rounding position determination circuit only when the instruction is executed.

FIG. 5 is a detailed diagram of the rounding correction determining circuit 8. The relationship between the rounding position determined by the rounding position determination circuit 6 and the bits used for rounding correction determination is as shown in Table 2. Rounding bit (L, G, S) depending on each rounding position
Therefore, a plurality of rounding correction determination circuits 811 to 813 are required for each rounding position. The rounding correction determination circuits 811 to 813 all have the same configuration, and as shown in Table 3, rounding up is generated by inputting a rounding bit of 3 bits, a sign of the result, and a predetermined rounding mode. Determine whether to do. The selection circuit 82 selects and outputs the output of the rounding correction determination circuits 811 to 813 or the logical value 0 according to the output of the rounding position determination circuit 6.

[0028]

[Table 3]

The rounding correction addition circuit 10 inputs the calculation result of the addition / subtraction circuit 4 and the output of the rounding correction determination circuit 8.
When rounding up is necessary due to rounding, 1 is added to the bit of L shown in Table 2, and when rounding down, it is output as it is without addition.

The shift number calculation circuit 12 inputs the calculation result of the adder / subtractor circuit, searches for a position of 1 (preceding 1) that appears first from the upper side, and calculates the shift number necessary for normalization. The normalization shift circuit 14 shifts the mantissa part output from the rounding correction addition circuit 10 according to the shift number calculated by the shift number calculation circuit 12. The output of the normalization shift circuit 14 normally has a decimal point immediately to the right (lower side) of the leading 1, but when the position of the leading 1 moves when the rounding correction addition circuit 10 performs +1 addition, There is a decimal point to the right of the bit one bit lower than the leading one. The rounding correction shift circuit 16 sets the output of the normalization shift circuit 14 to 1 so that the decimal point is located immediately to the right of the leading 1 when the position of the leading 1 is moved by the +1 addition of the rounding correction adding circuit 10. Shift to the lower bit side. However, when the position of the leading 1 is moved by the +1 addition of the rounding correction addition circuit 10, all the bits other than the leading 1 become 0, so that the rounding correction shift circuit 16 needs to actually shift: Only the leading 1 bit. In particular, when it is not necessary to output the leading 1 bit as in the IEEE-754 format, the rounding correction shift circuit 16 does not have to perform the shift.

The exponent part correction circuit 18 adds necessary correction to the exponent part output from the digit alignment circuit 2 by normalization shift. If the rounding correction shift circuit 16 needs to shift 1 bit to the lower side, the exponent part needs to be corrected by +1. Therefore, the exponent part corrected by +1 is also calculated at the same time. deep. The selection circuit 20 selects and outputs one of the two exponent parts calculated by the exponent part correction circuit 18, depending on whether or not the lower shift in the rounding correction shift circuit 16 is necessary. With such a configuration, the time required to correct the exponent part by the shift in the rounding correction shift circuit 16 can be substantially the processing time of the selection circuit 20, and thus high-speed processing is possible. Become.

Mantissa part output from the rounding correction shift circuit 16
(132) and the exponent part (134) output from the selection circuit 20 are combined to obtain the calculation result.

Processing time of the conventional arithmetic unit (FIG. 6 (a))
6 is compared with the processing time (FIG. 6B) of the arithmetic unit of this embodiment, the processing time of shift number calculation and rounding correction determination can be shortened, and floating point numbers can be calculated at high speed as a whole. It turns out that it is extremely effective to do.

[0034]

As described in detail above, according to the present invention,
Since the normalization process and the rounding process are performed in parallel, the processing time can be shortened as compared with the conventional arithmetic device.
It is possible to perform floating point arithmetic at higher speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a floating point arithmetic unit of the present invention.

FIG. 2 is a diagram showing a format of input / output data of a digit alignment circuit.

FIG. 3 is a detailed block diagram of an adder / subtractor circuit.

FIG. 4 is a detailed diagram of a rounding position determination circuit.

FIG. 5 is a detailed diagram of a rounding correction determination circuit.

FIG. 6 is a diagram comparing the processing time of the arithmetic device between the related art and the present invention.

FIG. 7 is a diagram showing an example of a method of expressing a floating point number.

FIG. 8 is a block diagram showing a schematic configuration of a conventional floating point arithmetic unit.

[Explanation of symbols]

 2 Digit alignment circuit 4 Addition / subtraction circuit 6 Rounding position determination circuit 61 Rounding position determination circuit 62 Selection circuit 8 Rounding correction determination circuit 81 Rounding correction determination circuit 82 Selection circuit 10 Rounding correction addition circuit 12 Normalized shift number calculation circuit 14 Normalized shift circuit 16 Rounding correction shift circuit 18 Exponential part correction circuit 20 Selection circuit

Claims (5)

[Claims] 1. A digit aligning unit that takes in two floating point operands and digit-matches the mantissa parts of both operands; an adder-subtractor unit that adds or subtracts the mantissa parts of both operands after digit aligning processing; Normalization means that shifts the mantissa so that the new highest digit after subtraction is at a predetermined position and corrects the exponent according to the number of shifts; and addition or subtraction In a floating-point arithmetic unit comprising rounding means for rounding down the number of digits of the mantissa according to a predesignated rounding mode when the subsequent mantissa has more than a predetermined number of digits, Take in the mantissa before normalization, and execute part of the rounding process using the mantissa,
After that, a unit for performing the normalizing process and the rounding process in parallel is provided, which is a floating point arithmetic unit. 2. Taking two floating-point operands, obtaining the absolute value of the difference between the exponent parts of both operands, and shifting the mantissa part of the operand with a small exponent part to the lower side by the obtained absolute value. A digit aligning means for aligning the mantissa parts of both operands, an adder / subtractor means for adding or subtracting the mantissa parts of the operands after digit aligning processing, and an addition or subtraction to obtain a new highest digit. A normalization unit that shifts the mantissa part so that the digit is at a predetermined position and corrects the exponent part according to the number of shifts, and the mantissa part after addition or subtraction have more than the predetermined digit number. In a floating-point arithmetic device having rounding means for reducing the number of digits of the mantissa according to a predesignated rounding mode, the shift of the mantissa at the time of performing the normalization processing. , 1 bit to the lower side, 0 bit to the upper side, or 1 bit to the upper side, and in each case, correction is required to add +1 to the mantissa part in the rounding process. Rounding correction determining means for determining whether or not the mantissa before the normalization processing is used, and the shift of the mantissa in the normalization processing is one of the three ways or other than the three ways. Based on the result of the rounding position determining unit and the rounding position determining unit, and one of three types of the rounding correction determining unit based on the determination result of the rounding position determining unit. Or
Alternatively, the floating point arithmetic unit is characterized in that the normalizing process and the rounding process are performed in parallel by providing selection means for invalidating all three ways. 3. A semiconductor device incorporating the floating point arithmetic unit according to claim 1. 4. A digit alignment process that takes in two floating-point operands and digit-matches the mantissa parts of both operands; an add-subtract process that adds or subtracts the mantissa parts of the two operands after digit alignment process; The normalization process is performed to shift the mantissa so that the new highest digit after subtraction comes to a predetermined position, and to correct the exponent according to the number of shifts, and the mantissa after addition or subtraction. In a floating-point arithmetic method that includes a rounding process that reduces the number of digits of the mantissa according to a pre-specified rounding mode when the number of digits is greater than a predetermined number, and the mantissa before the normalization is taken in A part of the rounding process is executed by using a unit, and then the normalizing process and the rounding process are performed in parallel. 5. Taking two floating-point operands, obtaining the absolute value of the difference between the exponent parts of both operands, and shifting the mantissa part of the operand with the smaller exponent part to the lower side by the obtained absolute value. A digit alignment process for aligning the mantissa parts of both operands, an addition / subtraction process for adding or subtracting the mantissa parts of both operands after the digit alignment process, and an addition or subtraction to obtain a new highest digit. Normalization processing that shifts the mantissa part so that the digit is in a predetermined position and corrects the exponent part according to the number of shifts, and if the mantissa part after addition or subtraction has more than the predetermined digit number, In a floating-point arithmetic method including rounding processing for reducing the number of digits of the mantissa according to a specified rounding mode, the shift of the mantissa when performing the normalization processing is 1 bit to the lower side and 0 to the upper side. Assuming that there are three types of cases where there is 1 bit to the upper side, and in each case whether or not the correction for adding +1 to the mantissa part is necessary in the rounding process, Before the normalization process, it is determined whether the rounding correction determination process is performed using the mantissa part, and whether the shift of the mantissa part in the normalization process is one of the three types or is other than the three types. Rounding position determination processing for determining using the mantissa part of, and based on the determination result of the rounding position determination processing, one of three types of the rounding correction determination processing is enabled,
Alternatively, the floating point arithmetic method is characterized in that the normalizing process and the rounding process are performed in parallel by executing a selection process for invalidating all three ways.