JPH03102519A - Divider - Google Patents

Abstract

PURPOSE:To speed up entire division between the complement display numbers of '2' directly with use of hardware by improving algorithm in each step of the division, and extending the calculation rule of a redundance binary adder/ subtracter in one part. CONSTITUTION:In a redundant binary adder/subtracter 3, the calculation rule is extended only to the redundant binary adder/subtracter cell of the most significant bit in order to make correspondence to the negative division. In this calculation rule, regularity is disturbed concerning a transmission digit. However, since this redundant binary adder/subtracter cell is set in the most significant position, the carry is not propagated any more. A quotient determining circuit 4 determines arithmetic in the step and a value for the digit of a quotient while observing high-order three digits and the code of a divisor Y in the arithmetic result of the redundant binary adder/subtracter 3 in the preceding step. When the quotients corresponding to all n-steps and the arithmetic result of the redundant binary adder/subtracter 3 in the (n+1) step are calculated, the quotient and a remainder can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a subtractive shift type divider based on a cell arrangement method that performs division between two's complement numbers or between unsigned numbers.

Conventional technology Conventional dividers include, for example, Takagi, Yasuura, Yajima 2''
High-speed divider for VLSI using redundant binary representation, Transactions of the Institute of Electronics and Communication Engineers (D), J67-D, No.
4, pp4 50-457 (Sho 59-04).

In the following description, a redundant binary number is enclosed in [ ]SD2, an unsigned binary number is enclosed in [ko, and a two's complement representation number is enclosed in [ko2c]. For example, each digit of a numerical value represented by an uppercase letter symbol is expressed as X”[:Xll.XIX2 ・=Xn]sD2
It is represented by lowercase English letters followed by a subscript number. Table 1 also lists the explanations of the symbols used in the following description.

FIG. 5 shows a block diagram of a conventional divider.
In the example shown in the figure, n=6 in particular. In the same figure, 1
is a divisor converter that converts a positive or negative divisor in normalized two's complement representation into a redundant binary number; 2 is a dividend converter that converts a dividend in positive or negative two's complement representation into a redundant binary number;
3 is a redundant binary adder/subtractor that performs addition or subtraction between redundant binary numbers; 4 is a redundant binary adder/subtractor that determines whether addition or subtraction should be performed in the redundant binary adder/subtracter of the corresponding stage, and corresponds to that stage. A quotient determination circuit that determines the digit of the quotient; 5 a quotient converter that converts the quotient in redundant binary representation into a two's complement representation; and 6 a redundant 2 which is the calculation result of the redundant binary adder/subtractor in the final stage. This is a remainder converter that converts a base number to a two's complement representation number. In the drawings below, common numbers are used for the same parts.

The principle and operation of the conventional divider configured as described above will be explained below. Dividend X and divisor Y are given in unsigned binary representation by carving them into a conventional divider,
It is assumed that both have been normalized in advance. First, the dividend X and the divisor Y are converted into two redundant numbers R[0] and D by the dividend converter 2 and the divisor converter 1, respectively.

Here, the conversion rules from unsigned binary representation to redundant binary representation are shown below.

Conversion rules from unsigned binary representation to redundant binary representation> [
Xco2=[O. XIX2...'Xnl2[Xkos
nz ← [X ko2, then [X]12=[○. XIX2 ゜"Xn"sn2
Here, ← represents conversion of number expression. That is, an unsigned binary representation number is a redundant binary representation number as it is as a value.

Next, Rfil+ is input as the minuend to the redundant binary adder/subtractor 3 in the first stage, and D is input as the number of operations (addend or subtractor) to the redundant binary adder/subtracter 3 as shown in FIG. The signals are supplied to the binary adder/subtractor 3 all at once. The redundant binary adder/subtractor 3 at the first stage performs subtraction. In the redundant binary adder/subtractor 3 after the first stage, either addition or subtraction is performed according to the judgment of the quotient determination circuit 4 corresponding to that stage. The quotient determination circuit 4 looks at the upper three digits of the operation result of the redundant binary adder/subtractor 3 in the previous stage and determines the operation at that stage and the value of the quotient digit. When the quotient corresponding to all n stages and the operation result of the redundant binary adder/subtractor 3 of the (n+1)th stage are obtained, the quotient and remainder of the redundant binary representation are obtained as the calculation result. The quotient of the redundant binary representation is converted into a quotient converter 5, and the remainder is converted into a two's complement representation number by a remainder converter 6.

Here, the conversion rules from the redundant two-inferential representation to the two's complement representation are shown below.

<Conversion rules from redundant binary representation to two's complement representation> [X cosn2=[0 . XIX2 ・= xn]su2
If [Xko2c ← [XkoSD2], the conversion from the redundant two vertebra representation to the abstract representation of 2 is 2
This can be done by subtracting two unsigned binary numbers.

By looking at each digit of a redundant binary number and collecting only the 1 digit and setting the other digits as O's, we can subtract the binary number by selecting the 1's digit and setting it as 1 and the other digits as 0. can be converted to a two's complement representation number. This conversion uses two input selectors for each digit.
It can also be realized by using an abstract adder.

The contents of the processing described above, the calculation in #5 in the quotient determining circuit, and the algorithm for determining the quotient are summarized as follows.

Conventional division algorithm> Step 1 [R ”” lsn2←[X ] 2 [D SD2 ← [: Y Co2 Step 2 [Qe]snz :2 1 [R”'lsn2: =[:R”'lsn2[:l'
)] sn2 step 3 [Qj] sn2:: O jf [rg”.r
, +1'r2'j' KoSD2 ” OI I
f [re' ノ 1.1-, fll r2 C
Il KoSD2 〉 0[R””']s l
llp:= 2X [:R'ノ'E sn 2
- [' q+ cosn 2X [D]sc2en
d Step 4 Q: : [:q2. QIQ2 =゜ qn]sn2[z]2 ← [Q]sn2 [Rco2 ← [R tn”'] SD2 As shown in Table 2, the range of input values for the conventional divider is limited. The range of Z values is also shown in Table 2. for j:=l to n begin l if Ire (ノ) .
L I l p 2 mouth”Jsn 2 ( 0
II 12-1/2≦Z<2. If the values X and Y given are arbitrary integers, then X and Y must be taken as absolute fractions and normalized.

Addition and subtraction between redundant binary numbers are defined as shown in Tables 3 and 4, respectively. In the case of this conventional divider, the possible values of the arithmetic number (addend or subtraction) are limited to non-negative values, so there are the following advantages.

ul+ Vl+ Sh jl+ Wl({11
01 Hsj: Sum (difference) digit t1: Transfer digit w1: Intermediate sum (difference) That is, the transfer digit has the same meaning as a carry or borrow in addition and subtraction of two's complement numbers.

(1) Calculation rules become simpler.

(2) The transmitted digit propagates at most one digit.

Here, the transmitted digit ti is defined as follows.

In addition or subtraction of redundant binary numbers U and ■, U and ■
When the i-th digit of is uL vl, respectively, old ±V 2t +W S w1+ t In general addition and subtraction between redundant binary numbers, the transmitted digit propagates up to two digits, but as mentioned in (2) If the number of operations (addend or subtrahend) is limited to non-negative, the transmitted digits will only propagate to the highest possible digits. Therefore, the above addition and subtraction can be performed in a constant time without carry propagation, regardless of the number of digits of the operation number.

As described above, the conventional divider can only divide normalized unsigned binary numbers. That is, the range of values that the dividend X and the divisor Y can take are limited as shown in Table 2.

This range of values matches the conditions for the mantissa part of floating-point numbers, and in fact the division table 3. Note) Each column is written as a combination of (transmission digit, Chinese Dowa).

Table 4. Note) Each column is (transmission value) It is written in

The combination I5 (intermediate difference) was devised for dividing the mantissas of floating-point numbers.

Problems to be Solved by the Invention However, in the above configuration, for example, when an integer dividend X1 expressed as a two's complement and an integer divisor Y are given, R is an integer. The quotient Z is rounded down to the decimal point. The sign of the remainder R does not matter.

It cannot be applied to integer division. When attempting to perform integer division by extending a conventional divider, the dividend X1 before division, the absolute value and normalization of the divisor Y, and the quotient Z after division
It is necessary to correct the sign of R, the decimal point position, and the decimal point position of the remainder R. As a result, the amount of hardware and calculation time for the entire divider increases.

In view of this, it is an object of the present invention to provide a cell array type divider that can perform I6 division between integers as well as division between normalized numbers.

Means for Solving the Problems In order to solve the above problems, the inventions according to claims 1 and 3 provide a dividend converter that converts a dividend in positive or negative two's complement representation into a redundant binary number, and a normalized A divisor converter converts a positive or negative divisor in two's complement representation into a redundant binary number, and a ternary value {-1. 0. 1}, and the possible values of each digit other than the MSB of the addend or subtractor are expressed as binary {0. a first-stage redundant binary adder/subtractor that performs addition and subtraction between the redundant binary number outputted from the dividend converter and the redundant two-digit number outputted from the divisor converter; MS of expressed addend or subtrahend
3 values 1-L 0. 1}, the possible values of each digit other than the MSB of the addend or subtractor are limited to 2{Nff(0.11), and the redundant binary number output from the divisor converter and the redundant 2 The redundant binary adder/subtractor is stacked in n stages after the first stage redundant binary adder/subtracter, which performs addition and subtraction between the redundant binary adder and subtracter, which outputs the output from the base adder/subtractor to the left by 1 bit, 1 bit, and 1. Based on the adder/subtractor array, the operation result of the redundant binary adder/subtracter in the previous stage, and the sign of the divisor, it is determined whether addition or subtraction should be performed in the redundant binary adder/subtracter in the next stage, and the operation corresponding to that stage is determined. a quotient determination circuit that determines the digit of the quotient;
a quotient converter that converts the quotient of a redundant binary representation obtained by adding up each digit of the quotient determined by the quotient determining circuit in each stage into a number expressed as 1111 of 2; and a redundant binary adder/subtracter in the final stage. and a remainder converter that converts the redundant binary number that is the result of the operation into a two's complement representation number, and in the quotient determination circuit, when the divisor is positive, if A is negative, it is -1, if O is negative, it is 01, and if positive, it is earth. is the value of the corresponding quotient digit, and when the divisor is negative, it is determined that if A is negative, 1, if O is 0, and if positive, -1 is the value of the corresponding quotient digit. It is a vessel.

Further, the invention according to claims 2 and 4 provides a 1's complementer that takes the Iilt number of 1 of the divisor when the normalized divisor of the 2's complement representation is negative, and allows the decimal of the divisor to pass through when it is not negative; a dividend converter that converts a positive or negative dividend expressed as a 2's draw number into a redundant binary number; a divisor converter that converts the output from the 1's complementer into a redundant binary number; and an adder that is expressed as a redundant binary number. The possible values of all digits of a number or subtraction are expressed as binary {0.1}
The first stage performs addition and subtraction between the redundant binary number output from the dividend converter and the redundant binary number output from the divisor converter and to which 1 is added when the divisor is negative. A redundant binary adder/subtractor and the possible values of all digits of the addend or subtractor expressed in redundant binary are expressed as binary {0, 1
} and a redundant binary number obtained by shifting the output from the redundant binary adder/subtracter in the previous stage by 1 bit to the left, and a redundant binary number output from the divisor converter and further adding 1 when the divisor is negative. A redundant binary adder/subtractor array in which n stages of redundant binary adders/subtracters that perform addition/subtraction with base numbers are stacked after the redundant binary adder/subtracter in the first stage, and a next stage based on the operation results of the redundant binary adder/subtracter in the previous stage. A quotient determining circuit that determines whether addition or subtraction is to be performed in the redundant binary adder/subtractor and determines the digit of the quotient corresponding to that stage, and the quotient determining circuit in each stage. A quotient converter that combines each digit of the determined quotient to form a quotient in redundant binary representation, inverts the sign of this quotient when the divisor is negative, and converts the quotient in redundant binary representation to a number in two's complement representation. And, the operation result of the redundant binary addition/subtraction "Aa" in the final stage is redundant 2.
and a remainder converter for converting a base number into a two's complement representation number,
In the circuit for determining the quotient, if A is negative, -1, if ○, o
There is a divider characterized in that, if 1 is positive, 1 is determined as the value of the corresponding quotient digit.

By the means described in "Action" 2, the invention claimed in claim 1 is redundant.
A base adder/subtractor can be used to generate redundant binary representations of addends or subtractors (
7) Three values for MSB {-1. 0. 1}, and the number of possible values of each digit other than the MSB of the addend or subtraction is limited to only two values {0.1}. However, in the circuit for determining the quotient, if the divisor is positive , if A is negative, then -LO, then 01, if positive, then 1 is the value of the corresponding quotient, and when the divisor 20 is negative, if A is negative, L is O, then 01, and if positive, -1 is the corresponding quotient. By making a judgment that the value is a value of digits, it is possible to allow any integer expressed as a two's complement number for the dividend, and to allow a negative number by dividing it into the divisor.

The invention according to claim 3 further includes a normalizer, a quotient barrel shifter, and a remainder barrel shifter, so that in addition to the invention according to claim 1, an arbitrary two's complement integer can be used for the divisor. is possible.

The invention as set forth in claim 2 provides a numerator of 1 and the possible values of all digits of the addend or subtractive expressed in redundant 2 in binary {0.
1} and performs addition and subtraction between the redundant binary number outputted from the dividend converter and the redundant binary number outputted from the divisor converter and to which 1 is added when the divisor is negative. By providing a base adder/subtractor and a quotient converter that inverts the sign of the quotient expressed in redundant binary when the divisor is negative, any integer expressed in two's complement can be used as the dividend, and the divisor can be It is possible to allow negative numbers.

The invention according to claim 4 further includes a normalizer, a quotient barrel shifter, and a remainder barrel shifter, so that in addition to the invention according to claim 2, an arbitrary two's complement integer can be used for the divisor. is possible.

EXAMPLES Below, dividers according to four embodiments of the present invention will be described with reference to the drawings.

The first embodiment is a configuration example of a divider according to claim 1 of the present invention. FIG. 1 is a block diagram of a divider with n=6 in the same embodiment.

In the figure, 1 is a divisor converter that converts a positive or negative divisor in normalized two's complement representation into a redundant binary number, and 2 is a dividend that converts a dividend in positive or negative two's complement representation into a redundant binary number. Converter 3 is a redundant binary adder/subtractor that performs addition or subtraction between redundant binary numbers; 4 is a redundant binary adder/subtracter that determines whether addition or subtraction should be performed in the redundant binary adder/subtractor 3 of the corresponding stage; Determine the quotient digit corresponding to the column [q'']s[l222[R4・1)ko,,2 end if [rg (''). r+"'r2"' KoSD2
” 01 1f [r8fll .r, [”
}r%I)ko812 〉0: 2X[R'l']sn
2 - [q+] sn2 Apply. The other cells (indicated by openings without diagonal lines in the figure) are the same as the conventional divider.

Step 4 Q: [Zko2c [Rco2c [Qll. Q [Q]SDR [Rfn”1 ]SD2 q　ncoSD2 Table 6. Table 5. Note 1) Each column is (transmission digit, It is written in

Note 1) Each column is written as a combination of (transmitted digit, intermediate difference).

Note 2) M'SB (left end,
This is applied to the redundant binary adder/subtractor cell (indicated by the hatched opening in the figure). Other cells (indicated by openings without diagonal lines in the figure)
Same as conventional divider 28 calculator.

Table 7. Step 2 correction table 8. A second modified embodiment of the step 3 is a +I'4 example of the divider according to the present invention. Figure 2 shows n=6 in the same example.
FIG. 2 is a block configuration diagram of a divider in the case of FIG.

In the figure, 1 is a divisor converter that converts a positive or negative divisor in normalized two's complement representation into a redundant binary number, and 2 is a dividend that converts a dividend in positive or negative two's complement representation into a redundant binary number. Converter, 3 is a redundant binary adder/subtractor that performs addition or subtraction between redundant binary numbers; 4 is a redundant binary adder/subtractor that determines whether addition or subtraction should be performed in the redundant binary adder/subtractor of the corresponding stage; A quotient determination circuit 5 determines the digit of the quotient corresponding to that stage, and 5 corrects the sign of the quotient obtained by the quotient determination circuit 4 and converts the quotient in redundant binary representation to a two's complement representation number. The quotient converter 6 is a remainder converter that converts the redundant binary number, which is the operation result of the redundant binary adder/subtractor at the final stage, into a two's complement representation number.

Regarding the divider of this embodiment configured as shown below,
The principle and operation will be explained below.

It is assumed that a dividend X and a divisor Y in two's complement representation are given to the divider of this embodiment, and the divisor Y is normalized in advance. First, if Y is negative, it is converted to the one's complement of Y by the divisor Y. The dividend X and the output of the 1's complementer are converted into redundant binary numbers R(8) and D by a dividend converter 2 and a divisor converter 1, respectively. Next, R[0> is entered manually as the operand (articendant or minuend) to be inscribed in the redundant binary adder/subtractor in the first stage, and D is the operand to be inscribed in the redundant binary adder/subtractor as shown in Fig. It is supplied all at once to the redundant binary adder/subtractor 3 of each stage as an addend or subtractor. The redundant binary adder/subtractor 3 at each stage performs either addition or subtraction according to the judgment of the quotient determination circuit 4 corresponding to that stage.

Here, if the divisor Y is negative, the divisor Y is already 1
Since it has been converted to the complement of , in order to convert it to the 2's complement of the divisor Y, a correction is performed by carving it into D and adding j. This correction is performed simultaneously when addition and subtraction are performed in the redundant binary adder/subtractor 3 of each stage.

As shown in Tables 9 and 10, this correction is realized by modifying the calculation rule for the LSB of the redundant binary adder/subtractor 3 in each stage. Even if the LSB calculation rules are modified in this way, there is no carry (transmission) from lower than the LSB, so digit propagation from LSB31 to the upper side will not occur.

The quotient determination circuit 4 looks at the upper three digits of the operation result of the redundant binary adder/subtractor 3 in the previous stage and determines the operation at that stage and the value of the quotient digit. When the quotient corresponding to all n stages and the operation result of the redundant binary adder/subtractor 3 of the (n+1)th stage are obtained, the quotient and remainder of the redundant binary representation are obtained as the calculation result. The quotient of the redundant binary representation is converted into a quotient converter 5, and the remainder is converted into a two's complement representation number by a remainder converter 6. In this embodiment, the quotient converter 5 also corrects the sign of the quotient.

This is because the absolute value of the divisor is taken first, so if the divisor is negative, the sign of the quotient will be reversed. Therefore, if the divisor is negative, the sign of the quotient can be inverted. This is a subtraction performed when the quotient in redundant binary representation is converted into a two's complement representation in the quotient converter 5, and can be realized by exchanging the minuend and the subtrahend. Table 12 lists the algorithm for quotient conversion in the quotient converter 5.

The contents of the processing described above, the calculations in the quotient determining circuit, and the algorithm for determining the quotient are summarized as follows32.

Division algorithm of the second embodiment> Step 1 [Rfill SD2 = [X]2CH
Y>O then [D]SD2'- [:'Y ko2ce
lse [DkoSD2 ← [Y]2C Step 2 1 1 f [ r9 +21 . r, (
l! +p2 (9) koSD2 ku 0[q@
koSD2 ” O If [rl]”'
．． r+ L'''l'2IQ']sn2'' OI
If [p,ll. r, flll) r2([ll koS
D2〉0[R[L]koSD2 ” [R”']
S[+2 − [qlllsn2X [D+IkoS
D2 Step 3 for j::1 to n 1 If [r2f1+ . r+"r2":]sn
2< 0[qj]so2 := O If
[r2”.r1(”r2” KoSD2” OI
If [r8(1.,%jl r2i11 koSD2
〉0[11if1411 cosn2:=2X[R”
]sn2-[qjkoso2X [:D+1koSD2en
d Step 4 Q: ” [q[1.Ql q2
゜-QnkoSD2If Y>O then [Z ko2c ← [QkoSD2else [Z ko2c'-[QkoSD2 [R]2C = [R'''koSD2 Here, Y is Y
It shows the one's complement of , that is, the numerical value with the bits of each digit inverted. The modified step 2 is listed in Table 11, and the operation table of the quotient converter of the second embodiment is listed in Table 12.

begin Table 9. Table 10. Note 1) Each column is written as a combination of (transmitted digit, intermediate sum).

Note 2) Applies to the redundant binary adder/subtractor cell of each redundant binary adder/subtractor in Figure 2, LSB (right end, indicated by the opening with a broken line in the figure). The other cells (indicated by openings without diagonal lines in the figure) are the same as conventional dividers.

Note 3) +O indicates that the divisor is positive, and +1 indicates that the divisor is negative.

35 Note 1) Each column is written as a combination of (transmission digit, intermediate difference).

Note 2) LSB of each redundant binary adder/subtractor in Figure 2 (right end,
This is applied to the redundant binary adder/subtractor cells (indicated by diagonally hatched openings in the figure). The other cells (indicated by openings without diagonal lines in the figure) are the same as conventional dividers.

Note 3) +O indicates that the divisor is positive, and +1 indicates that the divisor is negative.

36 Table 11. It becomes possible to directly calculate a two's complement representation number as a number. Furthermore, since negative numbers can be calculated for the divisor, the preprocessing for the division of this embodiment has the effect that it is only necessary to normalize the divisor before inputting it to the divider of this embodiment. have

In addition, in the divider of this embodiment, the bit 1/length of the dividend is 2n, so Table 12. (2n bits) ÷ (n bits) = (n bits 1.) This means that a multiplier division is performed, such as the remainder (n bits).

The reason why the sign of the remainder of the operation result is not concerned in the first and second embodiments is that it often depends on the standard of the entire arithmetic processing device including the divider.

According to the first and second embodiments as shown in 12 below, when performing dividend single-precision division (n bits) ÷ (n bits) = (n bits) remainder (n bits), simply divide n bits. It is sufficient to sign-extend the dividend to 2n bits.

The third embodiment is an example of the structure of the divider according to claim 3 of the present invention.

FIG. 3 is a block diagram of the divider in the same embodiment. In the figure, 8 is a divisor normalizer, 9 is a divider of the first embodiment, 10 is a quotient barrel shifter, and 11 is a remainder barrel shifter. The normalizer 8 includes, for example, a priority encoder that searches rightward from bit i to the right of the MSB of the divisor to first find the position of bit 1 that is different from the MSB, and a priority encoder that moves the divisor to the left by the number of bits counted. Consists of a barrel shifter that shifts to

The principle of the divider of the third embodiment is the same as that of the first embodiment. The operation of the third embodiment will be explained below.

(1) Normalize the divisor Y.

(2) Execute the division according to the first embodiment and obtain a provisional quotient Z and a provisional remainder R.

(3) Move the decimal point of the obtained quotient 2 to the correct position. The amount of movement of the quotient decimal point, ie, the shift number, is determined from the shift number when the divisor Y is normalized.

(4) Move the decimal point of the obtained remainder R to the correct position. The number of shifts at this time is the same as that in (3).

As described above, by normalizing the divisor as a preprocessing of the division by the divider of the first embodiment and correcting the quotient and remainder as a postprocessing, any two's complement number can be used as a divisor. . FIG. 6 is a flowchart illustrating the operation flow of the division step in this embodiment.

The fourth embodiment is an example of the structure of the divider according to claim 4 of the present invention. FIG. 4 is a block diagram of the divider in the same embodiment. In the same figure, 7 is the complement of I, 8
is a normalizer, 1o is a quotient barrel shifter, 11 is a remainder barrel shifter, and 12 is a divider obtained by removing the 1's complement from the divider of the second embodiment. The normalizer 8, for example, uses the MS of the divisor
Priority encoder 40 that searches rightward from the bit to the right of B and first finds the position of the bit different from the MSB.
- Consists of a coder and a barrel shifter that shifts the divisor to the left by the number of bits counted by the coder.

The principle of the divider in the fourth embodiment is the same as in the second embodiment. The operation of the fourth embodiment will be explained below.

(1) If the divisor Y is negative, take the number 1 of Y.

(2) Normalize the divisor Y.

(3) Execute the division according to the second embodiment (however, 1 of Y
To take the complement of , divide <) and find a provisional quotient Z and a provisional remainder R.

(4) Move the decimal point of the obtained quotient 2 to the correct position. The amount of movement of the quotient decimal point, that is, the shift number, is determined from the shift number when the divisor Y is normalized. At the same time, if the divisor Y is negative, the sign of the quotient Z is inverted.

(5) Move the decimal point of the obtained remainder R to the correct position. The number of shifts at this time is the same as that in (4).

By correcting the divisor before and after the division by the divider of the second embodiment as described above, any two's complement number can be used as the divisor.

FIG. 7 is a flowchart illustrating the operation flow of the division step in this embodiment.

As explained above, the dividers of the third and fourth embodiments can be used to express numbers in unsigned binary numbers, two's complement numbers, normalized numbers, denormalized numbers, double-precision integers, and single-precision integers. Upward division is also possible. When the divider of the third and fourth embodiments is incorporated, for example, as part of an arithmetic processing unit, it can function as both an integer divider and a mantissa divider of a floating-point arithmetic unit. Therefore, it is possible to speed up both integer division and floating point division with almost no increase in the amount of hardware.

In addition, in the case of this implementation method, the divisor input to the divider of the first and second embodiments can be selected from either the normalizer or the already normalized mantissa, so that the mantissa does not pass through the transformer. Table 13. Note: ○ indicates that the number can be input to the divider as an arithmetic number and calculated correctly.

× indicates that it cannot be input to the divider as an arithmetic number.

−43 It is also possible to further speed up the execution time of floating point division.

Table 13 summarizes the effects of expanding the range of operable numbers handled by the four embodiments.

Effects of the Invention As explained in 2, the present invention improves the algorithm in each step of division and expands the calculation rules of some redundant binary adders/subtractors to directly convert numbers in two's complement representation. This has the effect of allowing all divisions to be calculated quickly by hardware. Compared to a conventional divider with a cell array structure in which hardware is added to directly perform division between two's complement numbers, the present invention significantly reduces the amount of hardware and speeds up calculations. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a divider in a first embodiment of the present invention, FIG. 2 is a block diagram of a divider in a second embodiment of the present invention, and FIG. 3 is a block diagram of a divider in a third embodiment of the present invention. FIG. 4 is a block diagram of a divider in the fourth embodiment of the present invention,
FIG. 5 is a block diagram of a conventional divider, FIG. 6 is a flowchart showing the operation flow of the division step in the third embodiment of the present invention, and FIG. 7 is the division step in the fourth embodiment of the present invention. 2 is a flowchart showing the flow of the operation.

Claims (4)

[Claims] (1) Where n is the bit length of the divisor, the dividend in positive or negative two's complement representation has a base of 2 and each digit has redundancy represented by one of the elements {-1, 0, 1}. A dividend converter that converts the signed digit number (hereinafter referred to as redundant binary number) to a signed digit number (hereinafter referred to as redundant binary number), and a positive or A divisor converter that converts a negative divisor into a redundant binary number, and a ternary value {-1, 0, 1} for the most significant bit (hereinafter abbreviated as MSB) of an addend or subtractor expressed in redundant binary. The possible values of each digit other than the MSB of the addend or subtractor are limited to only binary {0, 1}, and the redundant binary number output from the dividend converter and the redundant binary number output from the divisor converter are The first-stage redundant binary adder/subtractor performs addition and subtraction with redundant binary numbers, and the adder allows the MSB of the addend or subtractor expressed in redundant binary to take ternary values {-1, 0, 1}. The possible values of each digit other than the MSB of a number or subtrahend are expressed as binary {0,
1} and performs addition and subtraction between the redundant binary number output from the divisor converter and the redundant binary number obtained by shifting the output from the redundant binary adder/subtracter in the preceding stage by one bit to the left. A redundant binary adder/subtractor array in which n stages are stacked after the redundant binary adder/subtractor in the first stage, and a redundant 2 in the corresponding stage based on the value of the dividend or the operation result of the redundant binary adder/subtracter in the previous stage and the sign of the divisor. a quotient determination circuit that determines whether addition or subtraction should be performed in the base adder/subtractor and determines the digit of the quotient corresponding to that stage; and a quotient determination circuit that determines the quotient digit corresponding to that stage; A quotient converter that converts the quotient of the redundant binary representation of each digit into a two's complement representation number, and a redundant binary number that is the operation result of the redundant binary adder/subtractor in the final stage is converted into a two's complement representation number. In the quotient determination circuit, when the divisor is positive, the first-stage redundant binary adder/subtractor converts the upper three bits of the dividend, and the redundant binary adder/subtractor after the first stage converts the upper three bits of the dividend to the first stage. If the upper 3 bits (hereinafter referred to as A) of the operation result of the redundant binary adder/subtractor are negative, -1, 0 if 0, and 1 if positive.
is the value of the corresponding quotient digit, and when the divisor is negative, it is determined that if A is negative, 1 is 0, if it is positive, -1 is the value of the corresponding quotient digit. vessel. (2) A 1's complementer that takes the 1's complement of the divisor when the normalized divisor in the 2's complement representation is negative and passes the divisor value directly when it is not negative; a dividend converter that converts the dividend into a redundant binary number; a divisor converter that converts the output from the one's complementer into a redundant binary number; and possible values of all digits of the addend or subtractive expressed in redundant binary. between the redundant binary number output from the dividend converter and the redundant binary number output from the divisor converter and to which 1 is added when the divisor is negative. The redundant binary adder/subtractor in the first stage performs addition and subtraction in
The possible values of all digits of the addend or subtractive expressed in decimal are 2
It is limited to only values {0, 1}, and a redundant binary number is obtained by shifting the output from the redundant binary adder/subtracter in the previous stage by 1 bit to the left, and the redundant binary number output from the divisor converter and further adding 1 when the divisor is negative. a redundant binary adder/subtractor array in which n stages of redundant binary adders/subtracters are stacked after the redundant binary adder/subtractor in the first stage, and a redundant binary adder/subtracter array that performs addition/subtraction with the redundant binary numbers obtained by adding or subtracting the value of the dividend or the redundant binary adder/subtracter in the previous stage; a quotient determination circuit that determines whether addition or subtraction should be performed in the redundant binary adder/subtractor of the corresponding stage based on the operation result of the unit, and also determines the digit of the quotient corresponding to that stage; The digits of the quotient determined by the quotient determination circuit are combined to form a quotient in redundant binary representation, and when the divisor is negative, the sign of this quotient is inverted, and the quotient in redundant binary representation is converted into a two's complement representation number. and a remainder converter that converts the redundant binary number, which is the operation result of the redundant binary adder/subtracter at the final stage, into a two's complement representation number, in the quotient determining circuit, -1 if negative;
A divider characterized in that it determines that the value of the corresponding quotient digit is 0 if it is 0, and 1 if it is positive. (3) a normalizer that normalizes the divisor in positive or negative two's complement representation by shifting it to the left or right, inputs the resulting value to the divisor converter, and counts the number of bits shifted at that time; a quotient barrel shifter that shifts the output of the quotient converter by the number of shifts counted by the normalizer and in the opposite direction to the direction shifted by the normalizer; 2. The divider according to claim 1, further comprising a remainder barrel shifter that shifts the output of the remainder converter in a direction opposite to the direction in which the output is shifted by the normalizer. (4) a normalizer that normalizes the output of the 1's complementer by shifting it to the left or right, inputs the resulting value to the divisor converter, and counts the number of bits shifted at that time; a quotient barrel shifter that shifts the output of the quotient converter by the number of shifts counted and in the opposite direction to the direction shifted by the normalizer; and the normalizer by the number of shifts counted by the normalizer. 3. The divider according to claim 2, further comprising a remainder barrel shifter for shifting the output of the remainder converter in a direction opposite to the direction in which the output of the remainder converter is shifted.