JPS6325506B2 - - Google Patents
Info
- Publication number
- JPS6325506B2 JPS6325506B2 JP54150344A JP15034479A JPS6325506B2 JP S6325506 B2 JPS6325506 B2 JP S6325506B2 JP 54150344 A JP54150344 A JP 54150344A JP 15034479 A JP15034479 A JP 15034479A JP S6325506 B2 JPS6325506 B2 JP S6325506B2
- Authority
- JP
- Japan
- Prior art keywords
- opening
- electrode
- shot
- metal layer
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920005989 resin Polymers 0.000 claims description 19
- 239000011347 resin Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000992 sputter etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- -1 argon ions Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特に超高周波
デバイスの微細電極の形成方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming fine electrodes for ultra-high frequency devices.
超高周波デバイス、特に電極面積が直接素子の
遮断周波数を決めるMOS−FETや、シヨツト
キ・バリア・ダイオードでは、いかに精度良く微
細電極を形成するかが重要なポイントとなる。 For ultra-high frequency devices, especially MOS-FETs and shotgun barrier diodes, where the electrode area directly determines the cutoff frequency of the element, an important point is how precisely to form fine electrodes.
シヨツトキ・バリア・ダイオードを例に従来の
電極形成プロセスの問題点について述べる。従来
の電極形成方法は、メツキ法とエツチング法の２
種が代表的な方法である。 We will discuss the problems of the conventional electrode formation process using a shotgun barrier diode as an example. There are two conventional electrode forming methods: plating method and etching method.
Seeds are a typical method.
現在、GaAsシヨツトキ・バリア・ダイオード
は、その特性上の要求からシヨツトキ面積が増々
小さくなり、数百ＧHzの遮断周波数の素子では、
シヨツトキ面積をその直径に換算して1.5〜
1.0μφ、シヨツトキ容量として3/1000pF程度のも
のが必要になつて来ている。 Currently, GaAs shot barrier diodes have increasingly smaller shot areas due to their characteristic requirements, and devices with a cutoff frequency of several hundred GHz are
Convert the surface area to its diameter and it will be 1.5~
A capacitance of 1.0 μφ and a shot capacitance of about 3/1000 pF is becoming necessary.
その様な素子を従来プロセスで形成しようとし
た場合、最初にエツチング法について第１図ａ〜
ｅを参照して述べると、まず半導体基板（例えば
GaAs基板）１上に、スパツタ又はCVD法で酸化
シリコンの様な絶縁膜を厚さ3000〜5000Å程度形
成し、写真食刻技術で前記絶縁膜を選択的に除去
して直径1.0〜1.5μφのシヨツトキ開口部を形成す
る（第１図ａ）。 When attempting to form such an element using a conventional process, first the etching method is described in Figures 1a to 1.
Referring to e, first, a semiconductor substrate (e.g.
An insulating film such as silicon oxide with a thickness of about 3000 to 5000 Å is formed on GaAs substrate 1 by sputtering or CVD method, and the insulating film is selectively removed by photolithography to form a 1.0 to 1.5 μφ diameter insulating film. Form a shot opening (FIG. 1a).
次に、シヨツトキ・バリア形成用金属として例
えばTiを蒸着し、その上に電極金属としてTi−
Pt−Auをスパツタ法により被着する（第１図
ｂ）。これらの金属の代表的な膜厚としては、
Ti：500Å、Pt：1500Å、Au：2000Å程度であ
る。 Next, for example, Ti is vapor-deposited as a shot barrier forming metal, and on top of that Ti is deposited as an electrode metal.
Pt-Au is deposited by sputtering (Fig. 1b). Typical film thicknesses for these metals are:
Ti: about 500 Å, Pt: 1500 Å, Au: about 2000 Å.
次に、シヨツトキ開口部の上に感光性樹脂材料
のパターン４を形成する（第１図ｃ）。この時、
現在の各パターン間の重ね合わせ精度では、最低
限士0.5〜1.0μのマージンを必要とする為、前記
開口部直径が例えば1.5μφの場合、上部電極パタ
ーン径を2.5〜3.5μφにする必要がある。 Next, a pattern 4 of photosensitive resin material is formed over the shot opening (FIG. 1c). At this time,
The current overlay accuracy between each pattern requires a minimum margin of 0.5 to 1.0μ, so if the opening diameter is, for example, 1.5μφ, the upper electrode pattern diameter needs to be 2.5 to 3.5μφ. be.
次に、前記感光性樹脂膜パターンをマスクにイ
オンミリング法（アルゴンイオン等によるスパツ
タエツチング法）等のエツチング技術により、不
要な金属を除去する（第１図ｄ）。 Next, using the photosensitive resin film pattern as a mask, unnecessary metal is removed by an etching technique such as ion milling (sputter etching using argon ions, etc.) (FIG. 1d).
最後に、前記感光性樹脂膜パターンを除去して
シヨツトキ・バリア・ダイオード素子が完成する
（第１図ｅ）。 Finally, the photosensitive resin film pattern is removed to complete the shot barrier diode element (FIG. 1e).
しかし、この製法では、実際のシヨツトキ面積
（径1.0〜1.5μφ）に対して電極全体の面積（径2.5
〜3.5μφ）が５〜６倍と大きくなり、絶縁膜を介
して、上部電極と基板間に発生するいわゆるオー
バーレイ容量が大きくなりすぎて、良好な素子性
能を得ることができないという欠点があつた。 However, with this manufacturing method, the area of the entire electrode (diameter 2.5
~3.5μφ) becomes 5 to 6 times larger, and the so-called overlay capacitance that occurs between the upper electrode and the substrate through the insulating film becomes too large, making it impossible to obtain good device performance. .
このオーバーレイ容量をさける電極形成方法と
してメツキ法がある。 There is a plating method as an electrode forming method that avoids this overlay capacitance.
メツキ法は、第１図ａのシヨツトキ開口部にの
み金属をメツキする方法であるが、メツキ可能な
電極構造としては、Ni−Auの様な構造しか採れ
ず、Ti−Pt−Au電極にくらべ耐熱性の点で大幅
に信頼度が劣る上に、シヨツトキ開口部の面積が
1.0〜1.5μφと小さくなるにつれ、均一なメツキが
非常にむずかしくなるという欠点があつた。 The plating method is a method in which metal is plated only on the shot opening shown in Figure 1a, but the only electrode structure that can be plated is a structure like Ni-Au, and compared to the Ti-Pt-Au electrode. In addition to being significantly less reliable in terms of heat resistance, the area of the shot opening is
As the diameter becomes smaller, from 1.0 to 1.5 μφ, it becomes extremely difficult to achieve uniform plating.
本発明は、上記従来のプロセスの欠点であつた
オーバーレイ容量をなくし、Ti−Pt−Au等の高
信頼度電極材料による微細電極の形成を可能なら
しめる目的で成されたものである。 The present invention was accomplished with the aim of eliminating overlay capacitance, which was a drawback of the conventional process, and making it possible to form fine electrodes using highly reliable electrode materials such as Ti--Pt--Au.
本発明の製造プロセスを第２図Ａ〜Ｅを参照し
て上記同様シヨツトキ・バリア・ダイオードを例
にとり説明する。 The manufacturing process of the present invention will be described with reference to FIGS. 2A to 2E, taking a shot barrier diode as an example as described above.
まず、従来プロセスと同様にGaAs基板１上の
酸化シリコン膜２に径1.0〜1.5μφのシヨツトキ開
口を開け、Ti−Pt−Auの順に金属層３を形成す
る（第１図Ａ及びＢ）。 First, in the same way as in the conventional process, a hole opening with a diameter of 1.0 to 1.5 .mu..phi. is opened in the silicon oxide film 2 on the GaAs substrate 1, and a metal layer 3 is formed in the order of Ti-Pt-Au (FIGS. 1A and B).
次に、シヨツトキ開口部の凹部をなるべく平か
つにうめる材料、例としてシリコン樹脂や感光性
樹脂膜４′を前記金属層３上全面に被着する（第
２図ｃ）。このとき、例えば前記凹部の径が1.0〜
1.5μφで深さが4000〜5000Åの場合には、感光性
樹脂膜を平坦部における厚さが約2000Åになる様
に形成してやれば、前記凹部にも十分に該樹脂が
充填される。 Next, a material such as a silicone resin or a photosensitive resin film 4' is deposited on the entire surface of the metal layer 3 (FIG. 2c) to fill the recessed portion of the shot opening as flatly as possible. At this time, for example, the diameter of the recess is 1.0~
In the case of a diameter of 1.5 μφ and a depth of 4,000 to 5,000 Å, if the photosensitive resin film is formed to have a thickness of about 2,000 Å at the flat portion, the resin will be sufficiently filled in the recess.
次に、イオンミリング法を用いて前記樹脂膜
４′及び金属層３をなるべく平かつになるように
エツチング除去し、シヨツトキ開口部に充填され
た樹脂はできるだけ残すようにする（第２図Ｄ）。
なお、前記樹脂膜が開口部上において平坦でな
く、窪みを有する場合は、イオンビームの入射角
度を調整して開口部上の樹脂膜のエツチング速度
を遅くし、過度にエツチング除去されてしまわな
いようにする必要がある。例えば、アルゴンイオ
ンを用い、加速電圧500eV、電流密度0.6ｍＡ／
cm2の条件でエツチングする場合、感光性樹脂膜
（米国シツプレー社製のAZ−1350を使用）のエツ
チング速度は、イオンビームを垂直に入射させた
とき200Å／minであるが、入射角度を25〜30゜に
すると400Å／minと２倍の速さになる。したが
つて、基板を回転させながらイオンビームを照射
し、イオンビームが前記窪みの部分ではなるべく
垂直に近く、その他の部分では角度をもつて入射
するようにしてやれば、開口部上の樹脂を最後ま
で残すことが可能である。なお、上記条件での
Ti、Pt、Auのエツチング速度はそれぞれ180
Å／min、300Å／min、450Å／minである。 Next, the resin film 4' and metal layer 3 are etched and removed using ion milling to make them as flat as possible, leaving as much of the resin filled in the shot openings as possible (Figure 2D). .
Note that if the resin film is not flat on the opening and has a depression, the incident angle of the ion beam is adjusted to slow down the etching speed of the resin film on the opening to prevent it from being excessively etched away. It is necessary to do so. For example, using argon ions, acceleration voltage 500eV, current density 0.6mA/
When etching under the condition of cm 2 , the etching rate of the photosensitive resin film (AZ-1350 manufactured by Shipley, USA) is 200 Å/min when the ion beam is incident perpendicularly, but when the incident angle is changed to 25 If the angle is set to ~30°, the speed will be doubled to 400Å/min. Therefore, by rotating the substrate and irradiating the ion beam so that the ion beam is incident as close to perpendicular to the recessed area as possible and at an angle to the other areas, the resin above the opening can be completely removed. It is possible to leave it until In addition, under the above conditions
The etching speed of Ti, Pt, and Au is 180 each.
Å/min, 300 Å/min, and 450 Å/min.
次に、前記開口部内に残存する樹脂膜を除去す
れば、所望の電極が形成され、シヨツトキ・バリ
ア・ダイオード素子が完成する（第２図Ｅ）。 Next, by removing the resin film remaining in the opening, a desired electrode is formed and a shot barrier diode element is completed (FIG. 2E).
上記のように、本発明によれば、Ti−Pt−Au
等の高信頼性の電極材料を用いてシヨツトキ開口
部内に電極を形成することができるので、信頼性
を低下させることなく、オーバーレイ容量をなく
すことができ、超音周波デバイスの性能を大幅に
向上させることができる。 As mentioned above, according to the present invention, Ti-Pt-Au
Since the electrode can be formed inside the shot opening using highly reliable electrode materials such as, overlay capacitance can be eliminated without reducing reliability, greatly improving the performance of ultrasound devices. can be done.
尚、本発明は上記実施例に限らず、例えばシヨ
ツトキ・ゲートFETのゲート電極の形成に使え
ることはもちろん、絶縁膜の微細な開口部内に金
属を形成する必要のある半導体装置の製造に広く
適用することができる。また、電極金属は上記
Ti−Pt−Auに限らず、必要に応じてAlやその他
の金属を使用できることはもちろんである。 It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be used, for example, to form gate electrodes of shotgun gate FETs, and can also be widely applied to the manufacture of semiconductor devices that require the formation of metal within minute openings in insulating films. can do. In addition, the electrode metal is
Of course, it is not limited to Ti-Pt-Au, and Al or other metals can be used as necessary.
尚、上記実施例に示したシヨツトキ・バリア・
ダイオード素子は、電極の表面が絶縁膜よりも低
く形成され、かつ中央部が窪んでいるが、通常は
該電極に針を立ててダイオード装置を組立てるの
で、このような形状の方が好ましい。しかしなが
ら他の半導体装置に本発明を適用する場合で、電
極表面が低くなつていては都合が悪いこともある
が、その場合は上記電極表面に金属をメツキする
ことにより、電極表面を絶縁膜よりも盛り上げる
ことができる。 In addition, the shotgun barrier shown in the above example
In the diode element, the surface of the electrode is formed lower than the insulating film, and the center part is depressed, but such a shape is preferable because the diode device is usually assembled by placing a needle on the electrode. However, when applying the present invention to other semiconductor devices, it may be inconvenient if the electrode surface is low. You can also liven it up.
第１図ａ〜ｅは従来方法を説明する為の断面
図、第２図Ａ〜Ｅは本発明の一実施例を説明する
為の断面図である。
１……半導体基板（GaAs）、２……絶縁膜
（SiO2）、３……シヨツトキ・バリア金属及び電
極金属（Ti−Pt−Au）、４，４′……感光性樹脂
膜、５……オーバーレイ金属部。
1A to 1E are sectional views for explaining the conventional method, and FIGS. 2A to 2E are sectional views for explaining one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate (GaAs), 2...Insulating film ( SiO2 ), 3...Shot barrier metal and electrode metal (Ti-Pt-Au), 4,4'...Photosensitive resin film, 5... ...Overlay metal part.
Claims (1)
記絶縁膜に開口部を形成する工程と、前記開口部
を含む全面に前記絶縁膜よりも薄い金属層を被着
して前記開口部にシヨツトキ・バリアを形成する
工程と、前記金属層上に樹脂膜を形成するととも
に前記開口部における凹部に前記樹脂を充填する
工程と、イオンミリング法により前記樹脂膜およ
び前記金属層をほぼ平坦にエツチングし前記開口
部にのみ金属層および樹脂を残す工程と、前記開
口部に残る樹脂を除去して中央部の窪んだ電極を
形成する工程を含むことを特徴とする半導体装置
の製造方法。1. A step of forming an insulating film on a semiconductor substrate, a step of forming an opening in the insulating film, and a step of depositing a metal layer thinner than the insulating film on the entire surface including the opening, and then shot-covering the opening.・A step of forming a barrier, a step of forming a resin film on the metal layer and filling the recess in the opening with the resin, and etching the resin film and the metal layer almost flat by an ion milling method. A method for manufacturing a semiconductor device, comprising the steps of leaving a metal layer and resin only in the opening, and removing the resin remaining in the opening to form a recessed electrode in the center.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15034479A JPS5673435A (en) | 1979-11-20 | 1979-11-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15034479A JPS5673435A (en) | 1979-11-20 | 1979-11-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5673435A JPS5673435A (en) | 1981-06-18 |
| JPS6325506B2 true JPS6325506B2 (en) | 1988-05-25 |
Family
ID=15494934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15034479A Granted JPS5673435A (en) | 1979-11-20 | 1979-11-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5673435A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5330879A (en) * | 1992-07-16 | 1994-07-19 | Micron Technology, Inc. | Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer |
| JP4718587B2 (en) * | 2008-07-25 | 2011-07-06 | 株式会社本庄厨房機器製作所 | Folding table |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249772A (en) * | 1975-10-18 | 1977-04-21 | Hitachi Ltd | Process for production of semiconductor device |
-
1979
- 1979-11-20 JP JP15034479A patent/JPS5673435A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249772A (en) * | 1975-10-18 | 1977-04-21 | Hitachi Ltd | Process for production of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5673435A (en) | 1981-06-18 |
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