JPS63254549A - Check system for control memory - Google Patents

Abstract

PURPOSE:To improve the reliability of a check system for control memory by realizing the switching of the processor working state between a normal mode and a patrol mode, producing repetitively and forcibly continuance instructions in a patrol mode to scan the reading of a control memory, and carrying out a patrol diagnosis. CONSTITUTION:When a normal mode is set, a multiplexer 7 selects an operation field 4 to apply it to a sequencer 2 and the sequencer 2 performs an action designated by the field 4. While the multiplexer 7 selects a continuation instruction and applies it to the sequencer 2 in a patrol mode. Then the sequencer 2 produces an address to give access to a position following the position which received access immediately before a control memory 1. Then the period of the patrol mode is continued for the reading scan of the memory 1 and the patrol diagnosis is carried out. As a result, an error area is cleared before shift to the normal mode and therefore the chances where the errors are detected when a microprogram is executed can be extremely decreased.

Description

[Detailed Description of the Invention] [Summary] The present invention makes it possible to switch the operating state of the processor between a normal mode and a patrol mode in a pipelined processor, and in the patrol mode, forcefully issues a continuation instruction repeatedly. The system reads and scans the control memory to perform patrol diagnosis and improve reliability.

[Industrial application field]

The present invention relates to a pipeline type processor such as a binotomasobu processor used for image processing, and more particularly to a control memory check method used in a microprogram control device therein.

In a pipelined processor, a microprogram stored in a control memory is read out and processed by a pipeline. If an error occurs when accessing the control memory, it will cause a major problem in processing, so error checking is necessary.

[Conventional technology]

FIG. 3 shows an example of the configuration of a conventional microprogram control device for a pipelined processor.

In FIG. 3, 1 is a control memory in which a microprogram to be executed in a pipeline is stored.

2 is a sequencer that generates the next access address of the control memory l.

3 is a pipeline register at the first stage of the pipeline in which data (in this case, microinstructions) read from the control memory 1 is set.

Reference numeral 4 denotes an operation field containing information for providing operating conditions to the sequencer 2, such as whether the next access address should be the next address or the jump destination address. Note that the remaining fields are control information fields for realizing the contents of the command.

Reference numeral 5 denotes a parity check circuit that checks for errors in data (microinstructions) read from the control memory l.

In operation, when the sequencer 2 generates an access address, it is applied to the control memory l and one microinstruction is read from that address location.

The read microinstruction is stored in pipeline register 3.
The parity check circuit 5 checks for errors. If no error is detected here, the microinstruction in the pipeline register 3 is assumed to be valid and pipeline processing is executed based on it.

If the microinstruction is valid, the information in the operation field 4 is passed to the sequencer 2,
Used to generate the address of the next microinstruction to access.

In this way, the microprogram in the control memory 1 is read out and executed by the sequencer according to the operating conditions.

On the other hand, if an error is detected in a microinstruction read from control memory 1, the microinstruction is invalidated and recovery processing is performed. A method is adopted in which two or more stages are provided and the microinstruction is transferred to the execution stage after error detection and recovery processing are completed.

In addition, there are methods that detect and recover from errors, then input microinstructions into the pipeline and execute them.
Rather than performing error detection and recovery processing for each individual microinstruction, the operation mode is switched at regular time intervals to supply continuous addresses for read scanning to control memory, and error detection and recovery processing is performed by performing patrol diagnosis. Some have adopted a method of doing so.

[Problem that the invention seeks to solve]

The conventional method in which error detection and recovery processing are performed after microinstructions read from a control memory are input into a pipeline has the disadvantage that the pipeline control mechanism becomes complicated and the amount of hardware increases.

Furthermore, the conventional method of inputting a microinstruction to a pipeline after performing error detection and recovery processing has the drawback that the overhead increases the cycle time of the pipeline and reduces the execution speed.

Furthermore, the conventional method of performing patrol diagnosis of the control memory by switching the operation mode has the disadvantage that it is necessary to provide a dedicated register for generating addresses in place of the sequencer for supplying continuous addresses to the control memory.

Means for Solving Problem c] The present invention sets a patrol mode while the processor is in operation and performs patrol diagnosis on the control memory, thereby detecting a failure in the control memory at an early stage. This reduces the chance of failure occurring during line control operations.

The present invention will be explained in detail with reference to FIG.

FIG. 1 shows the basic configuration of a microprogram control device for a pipelined processor according to the present invention. In the figure, l is a control memory in which a microprogram to be executed in a pipeline is stored.

2 is a sequencer which controls the execution order of the microprograms stored in the control memory 1 by specifying the next reading position.

3 is a pipeline register in which microinstructions read from the control memory 1 are set.

Reference numeral 4 denotes an operation field within the microinstruction, which contains information for determining the position of the microinstruction to be executed next, and is given to the sequencer 2.

Reference numeral 5 denotes a parity check circuit, which checks the microinstructions read from the control memory 1 for errors.

6 is a continuation instruction generation circuit that generates a continuation instruction that causes the sequencer 2 to select the next address.

A multiplexer 7 selects whether the operation field in the read microinstruction is a continuation instruction, depending on whether the operation mode is a normal mode or a patrol mode, and supplies the selected multiplexer to the sequencer 2.

[Effect]

The processor switches the operating mode between the normal mode and the patrol mode at regular intervals or when an appropriate operating state occurs.

When the processor is operating in the normal mode, the multiplexer 7 is set to select the operation field 4 of the microinstruction and provide it to the sequencer 2.

In this normal mode, the microinstructions of the microprogram stored in the control memory 1 are sequentially read out by the sequencer 2 which is controlled by the operation field 4 of the execution microinstruction.

Each microinstruction read from the control memory 1 is manually input to the pipeline register 3 and executed, and is checked for errors by the parity check circuit 5.

Next, when the processor is operating in the patrol mode, the multiplexer 7 selects the continuation instruction generated by the continuation instruction generation circuit 6 and supplies it to the sequencer 2.

When the sequencer 2 identifies the input of a continuation instruction, it operates to create an address obtained by adding 1 to the immediately previous access address, that is, the next address on the physical address array.

The address created by the sequencer 2 in patrol mode is supplied to the control memory 1, and the corresponding microinstruction is read out. This read microinstruction is checked for errors in the parity check circuit 5, but is not set in the pipeline register 3.

As long as the patrol mode continues, a continuation command is given to the sequencer 2 every cycle, so the sequencer 2 creates access addresses that are sequentially increased by 1, and reads and scans the control memory I.

In this way, the contents of the control memory 1 are sequentially read out and subjected to patrol diagnosis by the parity check circuit 5. If an error is detected at this stage, recovery processing is performed. As a result, since the error portion is cleared before switching to the normal mode, it is possible to significantly reduce the chances of errors being detected during execution of the microprogram.

〔Example〕

The configuration of one embodiment of the present invention will be explained with reference to FIG.

FIG. 2 shows the basic configuration of the microprogram control device according to the present invention shown in FIG.
This is a concrete example. The newly added parts in FIG. 2 are 8 control registers, 9 mode control bits, 10 NAND gates, 11 CPUs, 12 decoders, and 13 buses.

In this embodiment, the control memory I has a capacity of 4 words, for example, and its address is given by 12 bits AO to All. The bit length of operation field 4 and continuation instruction is 4 bits.

The continuation instruction generation circuit 6 is constituted by hardware such as a resistor circuit, a latch, a gate circuit, etc. connected to a power supply potential or a ground potential so as to indicate the operation code of the four pins of the continuation instruction.

The control register 8 is write-controlled by the CPU II via the bus 13 and the decoder 12, and includes a mode control bit 9 for controlling the operating mode of the processor.
is assigned.

While operating in the normal mode, the cpuit sets the mode control bit 9 to "l" and sets the mode control bit 9 to "0" by a timer interrupt or by the end of a certain process.
Update to ゛ and switch to patrol mode.

The multiplexer 7 selects the output of the operation field 4 of the pipeline register 3 and sends it to the sequencer 2 when the mode control bit 9 is "1" (normal mode), and when the mode control bit 9 is "O" ( (patrol mode), the output of the continuation command generation circuit 6 is selected and sent to the sequencer 2.

While operating in normal mode, the output of NAND gate lO is
It changes to 0"/"■" every cycle, that is, every time a clock is input, and as a result, the microinstruction read from the control memory 1 every cycle is written into the pipeline register 3. That is, A microinstruction is input into the pipeline.

On the other hand, in patrol mode, NAND game)
The output of 10 is always "1" regardless of the presence or absence of clock input, and the pipeline register 3 is maintained in a cleared state. On the other hand, since the continuation command continues to be applied to sequencer 2 during patrol mode, sequencer 2
It operates as if it were given a new continuation instruction every clock.

As a result, in the sequencer 2, the access address is updated from (previous access address) + 1 to (next access address) every cycle.
A scan of control memory is performed.

Parity check circuit 5 performs a parity check each time control memory I is read, both in normal mode and patrol mode.

(Effects of the Invention) According to the present invention, it is not necessary to include the time for error detection and recovery processing in the pipeline cycle time, so high-speed processing is possible, and there is no need to specially prepare an address register for scanning. With a relatively simple hardware configuration and simple control means, it becomes possible to easily check the control memory, and system reliability can be efficiently improved.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram for explaining the present invention in detail;
FIG. 2 is a block diagram of one embodiment, and FIG. 3 is a block diagram of a conventional example. In Figure 1, control memory 2: sequencer 3: pipeline register 4: operation field 5: parity check circuit 6: continuation instruction generation circuit 7: multiplexer

Claims (1)

[Claims] In a pipelined processor, a control memory (1) in which a microprogram is stored.
and a sequencer (2) that controls the read position in the control memory.
), a continuation instruction generation circuit (6) that generates a continuation instruction that instructs the sequencer (2) to read the next location in the control memory (1), and a microinstruction read out from the control memory (1). a multiplexer (7) that selects either an operation field (4) that specifies the operation of the sequencer included in the sequencer or a continuation instruction generated by the continuation instruction generation circuit (6);
In addition, two operating modes, normal mode and patrol mode, can be set as the operating state of the processor. When the normal mode is set, the multiplexer (7) selects the operation field (4) and operates the sequencer. (2) to perform the operation specified by its operation field (4), and when patrol mode is set, the multiplexer (
7) selects a continuation instruction and gives it to the sequencer (2), generates an address that accesses the location following the location that was accessed immediately before in the control memory (1), and maintains the period of patrol mode. (1) A control memory check method characterized in that a patrol diagnosis is performed by reading and scanning.