JPS63253657A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63253657A JPS63253657A JP8805687A JP8805687A JPS63253657A JP S63253657 A JPS63253657 A JP S63253657A JP 8805687 A JP8805687 A JP 8805687A JP 8805687 A JP8805687 A JP 8805687A JP S63253657 A JPS63253657 A JP S63253657A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- insulating substrate
- hole
- substrate
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000010931 gold Substances 0.000 claims abstract description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052737 gold Inorganic materials 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000007747 plating Methods 0.000 abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 10
- 239000000919 ceramic Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 5
- 229910052759 nickel Inorganic materials 0.000 abstract description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract description 4
- 239000005394 sealing glass Substances 0.000 abstract description 4
- 238000005245 sintering Methods 0.000 abstract description 4
- 239000000843 powder Substances 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 8
- 229920000954 Polyglycolide Polymers 0.000 description 5
- 235000010409 propane-1,2-diol alginate Nutrition 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 229910000833 kovar Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000004663 powder metallurgy Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、安価で気密封止が可能な半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that is inexpensive and can be hermetically sealed.
従来の半導体装置のパッケージ構造をガラスで封止した
気密封止型を例にとって、第２図に示した０
この気密封止型半導体装置はピングリッドアレイ（ＰＧ
Ａ）と呼ばれるもので、１００ビン以上の多ビンを要求
されるゲートアレイやマイクロコンビエータの進展に伴
なって多用されてさている。Taking as an example the hermetic sealing type in which the conventional semiconductor device package structure is sealed with glass, this hermetic sealing type semiconductor device is shown in Figure 2.
It is called A) and is being used frequently with the development of gate arrays and micro combinators that require a large number of bins of 100 or more.
特に、第２図に示すような配線層が一層のＰＧＡは配線
パターンの変更のみでピンのレイアウトや使用ビン数の
調整が可能であることから、益々納期が短かくなってい
る半導体装置にとって有用になっている。In particular, PGAs with one wiring layer, as shown in Figure 2, are useful for semiconductor devices whose delivery times are becoming shorter and shorter, as the pin layout and number of bins used can be adjusted simply by changing the wiring pattern. It has become.
かかるＰＧＡの基板としては、使用実績の高いアルミナ
（ｉ ０ ）等のセラミックスが主流であるが、気密封
止が不要な用途では安価なガラスエポキシ等の基板も使
用されている。主流であるセラミックス基板の場合、ス
ルーホールを設けたグリーンシートを形成し、各スルー
ホール内にタングステン等をスクリーン印刷により充填
した後、このグリーンシート３〜５枚を積層して同時焼
成する複雑な工程により基板を製造している。As substrates for such PGAs, ceramics such as alumina (i 0 ), which have a good track record of use, are mainstream, but inexpensive substrates such as glass epoxy are also used in applications where hermetic sealing is not required. In the case of ceramic substrates, which are the mainstream, green sheets with through holes are formed, each through hole is filled with tungsten, etc. by screen printing, and then three to five of these green sheets are laminated and fired at the same time. The board is manufactured through a process.
このようにして形成した積層基板２の裏面から露出した
タングステンメタライズ４に、第２図に示す如くピン３
を銀ロウ５で固着し、表面にはりングステンメタライズ
４に接続して配線層８を形ＪＥＴる。ビン３はコバール
合金等の高強度低熱膨張金属を用い、基板２の裏面に銀
ロウ５で接続した後、耐食性及び半田付性を改善するた
め、ロウ付部を含めて基板裏面からのビン３の突出部分
にニッケルメッキ層６及びその上に金めつき層７が順次
施される。又、配線層８はアルミニウム又はアルミニウ
ム合金が主であって、基板表面に全面被着させた後フォ
トリソグラフィーによりパターニングし、エツチングし
て形成下る。As shown in FIG.
is fixed with silver solder 5, and connected to ringsten metallization 4 on the surface to form a wiring layer 8. The pin 3 is made of a high-strength, low-thermal-expansion metal such as Kovar alloy, and is connected to the back side of the board 2 with silver solder 5. In order to improve corrosion resistance and solderability, the pin 3 is made of a high-strength, low-thermal-expansion metal such as Kovar alloy. A nickel plating layer 6 and a gold plating layer 7 are sequentially applied to the protruding portion. The wiring layer 8 is mainly made of aluminum or an aluminum alloy, and is formed by coating the entire surface of the substrate, patterning it by photolithography, and etching it.
その後、積層基板２のほぼ中央にＸＣ等の半導体素子９
を銀入ガラスペーストを焼成した銀入ガラス１０で塔載
し、半導体素子９の各電極と配線層８はアルミワイヤ１
１等で結線される。最後に、積層基板２の上にセラミッ
クス製のキャップ１２を載せ、半導体素子９とアルミワ
イヤ１１を収容するようにその周囲を低融点の封止ガラ
ス１３で気密封止してＰＧＡが構成される。Thereafter, a semiconductor element 9 such as an XC is placed approximately in the center of the laminated substrate 2.
is mounted on a silver-containing glass 10 prepared by firing a silver-containing glass paste, and each electrode of the semiconductor element 9 and the wiring layer 8 are made of aluminum wire 1.
Connected with 1st class. Finally, a ceramic cap 12 is placed on the laminated substrate 2, and the periphery thereof is hermetically sealed with a low melting point sealing glass 13 so as to accommodate the semiconductor element 9 and aluminum wire 11, thereby constructing a PGA. .
しかし、従来のセラミックス積層基板を用いたＰＧＡ等
の半導体装置では、３〜５層のグリーンシートに夫々ス
ルホールメタライズし、これを積層して同時焼成して基
板を製造するため工数が多く、シかも基板裏面のヌタラ
イズ部分にビンを精度よくロウ付けする必要があるうえ
、基板表面には薄膜技術を用いて配線層を形成するので
、得られる半導体装置が極めて高価なものになっていた
。However, in semiconductor devices such as PGA that use conventional ceramic laminated substrates, the number of man-hours is large because the substrate is manufactured by through-hole metallizing each of three to five layers of green sheets, and then laminating and firing them at the same time. The bottle must be precisely brazed to the nutarized portion on the back of the substrate, and a wiring layer is formed on the surface of the substrate using thin film technology, making the resulting semiconductor device extremely expensive.
本発明は上記した従来の事情に鑑み、構造が簡単であっ
て、気密封止が可能であり、しかも安価な半導体装置を
提供することを目的とする。SUMMARY OF THE INVENTION In view of the above-mentioned conventional circumstances, it is an object of the present invention to provide a semiconductor device that has a simple structure, can be hermetically sealed, and is inexpensive.
本発明の半導体装置は、貫通孔を有する穴開き絶縁基板
と、穴開き絶縁基板の表面に形成した配線層と、穴開き
絶縁基板の表面に塔載され配線層と結線された半導体素
子と、穴開き絶縁基板の貫通孔に基板表面で配線層と接
続し且つ基板裏面から突出するように挿入され、貫通孔
内で金ロウＣ（Ｔより固着された表面に金めつき層を有
する金属製のビンとを具えたことを特徴とする。A semiconductor device of the present invention includes a perforated insulating substrate having a through hole, a wiring layer formed on the surface of the perforated insulating substrate, and a semiconductor element mounted on the surface of the perforated insulating substrate and connected to the wiring layer. A metal material having a gold plating layer on its surface is inserted into a through hole of a perforated insulating substrate so as to be connected to the wiring layer on the surface of the substrate and protrude from the back surface of the substrate, and is fixed with gold solder C (T) in the through hole. It is characterized by having a bottle.
穴開き絶縁基板としては、従来からのガラスエポキシや
セラミックスでよいが、気密封止を確保する為には低融
点ガラスとの濡れ性が非常に良好で熱膨張係数が近似し
ているアルミナ等のセラミックを使用することが好まし
く、特に粉末冶金法により一体的に成形し焼結して製造
した基板が製造上並びに特性上望ましい。Conventional glass epoxy or ceramics can be used as the perforated insulating substrate, but to ensure an airtight seal, alumina or other materials with very good wettability with low melting point glass and similar thermal expansion coefficients can be used. It is preferable to use ceramic, and in particular, a substrate manufactured by integrally molding and sintering by powder metallurgy is desirable from the viewpoint of manufacturing and properties.
ビンはコバール合金等の高強度低熱膨張の金属を用い、
金ロウとの接合性を得るために表面に予め金めつきを施
丁必要があり、従って好ましくは耐食性及び半田付性の
改善と併せて、ビン全体にニッケルめっき層及びその上
に金めつき層を予め形成しておくことが都合良い。The bottle is made of high-strength, low-thermal-expansion metal such as Kovar alloy.
It is necessary to apply gold plating on the surface in advance in order to obtain bondability with gold solder. Therefore, in addition to improving corrosion resistance and solderability, it is preferable to apply a nickel plating layer to the entire bottle and gold plating on top of it. It is convenient to form the layers beforehand.
又、配線層は高密度配線が可能な高導電性の材料であれ
ばよいが、特にアルミニウム又はアルミニウム合金が低
融点ガラスとの濡れ性がよく気密封止性を確保しやすい
。この配線層と半導体素子の電極とを結線するボンディ
ングワイヤも配線層と同質の材料を使用すれば、結線個
所に媒体となる被覆層を特に設けなくても直接に接続さ
せることが可能となる利点がある。Further, the wiring layer may be made of a highly conductive material that enables high-density wiring, but aluminum or an aluminum alloy in particular has good wettability with low-melting glass and can easily ensure hermetic sealing. If the bonding wire that connects this wiring layer and the electrode of the semiconductor element is also made of the same material as the wiring layer, the advantage is that it can be directly connected without providing a covering layer as a medium at the connection point. There is.
本発明においては、穴開き絶縁基板を使用し、配線層と
外部とを連絡する導電媒体として、表面に金めつき層を
有する金属製のビンを穴開き絶縁基板の貫通孔内に挿入
し、その内部で金ロウにより固着しである。従って、基
板を貫通し内部の配線層と外部とを連絡する導電媒体と
して、従来の如く複数のグリーンシートにいちいちスル
ホールメタライズを形成する必要がない。その結果、粉
末冶金法により一体的に成形し焼結して製造したセラミ
ックスの穴開き絶縁基板を用いることが可能になり、製
造工数を大幅に削減でさる。In the present invention, a perforated insulating substrate is used, and a metal bottle having a gold-plated layer on the surface is inserted into a through hole of the perforated insulating substrate as a conductive medium that connects the wiring layer and the outside. It is fixed inside with gold solder. Therefore, it is not necessary to form through-hole metallization on a plurality of green sheets one by one as a conductive medium that penetrates the substrate and connects the internal wiring layer with the outside, as in the conventional method. As a result, it becomes possible to use a ceramic perforated insulating substrate manufactured by integrally molding and sintering using a powder metallurgy method, and the number of manufacturing steps can be significantly reduced.
更に、金属製のビンの穴開き絶縁基板への固着は、貫通
孔内に表面に金めつき層を有するビンを挿入して両者の
隙間に金ロウを浸透流入させるだけで良好な結合が得ら
れ、従来の如く基板裏面のメタライズ部にビンを精度よ
くロウ付けするよりも簡単である。使用する金ロウの組
成はビンや基板の材質にもよるが、通常は高真空機器用
ＢＡｕ−２Ｖ（Ａｕ ８０％−Ｃｕ２０％）が好ましい
。又、金ロウによるピンの固着には、ピンへのＡｕめつ
さが予めバレルめつき等の安価なプロセスで行なえる等
の利点がある。Furthermore, a good bond can be achieved by simply inserting a bottle with a gold-plated layer on its surface into a through-hole and allowing gold solder to penetrate and flow into the gap between the two. This is easier than the conventional method of accurately brazing the bottle to the metallized portion on the back surface of the substrate. The composition of the gold solder used depends on the material of the bottle and the substrate, but BAu-2V (80% Au-20% Cu) for high vacuum equipment is usually preferred. Furthermore, fixing the pin with gold solder has the advantage that Au plating to the pin can be performed in advance by an inexpensive process such as barrel plating.
第１図に示すように、通常の粉末冶金法により成形及び
焼結して製造したアルミナ製の穴開き絶縁基板１の各貫
通孔内に、全体にニッケルめっき層６及びその上に金め
つき層７を予め形成したコバール製のピン３をそれぞれ
挿入した。次に、貫通孔の隙間に基板裏面から流入させ
た金ロウ１４でピン３を穴開き絶縁基板１に固着させた
。As shown in FIG. 1, a nickel plating layer 6 is applied throughout each through hole of an alumina perforated insulating substrate 1 manufactured by molding and sintering using a normal powder metallurgy method, and gold plating is applied thereon. A pin 3 made of Kovar, on which a layer 7 was previously formed, was inserted in each case. Next, the pin 3 was fixed to the perforated insulating substrate 1 with gold solder 14 which was introduced into the gap between the through holes from the back surface of the substrate.
その後、従来と同様に基板表面にアルミニウムの配線層
８を形成して各ピン３と接続させ、半導体素子９を所定
位置に塔載してから、半導体素子９の各電極と配線層８
とをアルミワイヤ１１で結線した。最後に、半導体素子
９及びアルミワイヤ１１を収容するセラミックスのキャ
ップ１２を封止ガラス１３で通常の如く封着し、気密封
止したＰＧＡを製造することがでさた。Thereafter, as in the conventional case, an aluminum wiring layer 8 is formed on the surface of the substrate and connected to each pin 3, and a semiconductor element 9 is mounted on a predetermined position.
and were connected with aluminum wire 11. Finally, the ceramic cap 12 that accommodates the semiconductor element 9 and the aluminum wire 11 is sealed with a sealing glass 13 in the usual manner to produce a hermetically sealed PGA.
Ｃ発明の効果〕
本発明によれば、構造が簡単で′あって、高密度配線及
び気密封止が可能であり、しかも安価な半導体装置を提
供することができる。C. Effects of the Invention] According to the present invention, it is possible to provide a semiconductor device that has a simple structure, enables high-density wiring and hermetic sealing, and is inexpensive.
第１図は本発明の半導体装置の断面図であり、第２図は
従来の半導体装置の断面図である。
１・・穴開き絶縁基板 ２・・積層基板 ３・・ピン４
・・タングステンメタライズ ５・・銀ロウ６・・ニッ
ケルめっき層 ７・・金めっさ層８・・配線層 ９・・
半導体素子
１０・・銀入ガラス １１・・アルミワイヤ１２・・キ
ャップ １３・・封止ガラス１４・・金ロウFIG. 1 is a sectional view of a semiconductor device of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1. Hole insulating board 2. Laminated board 3. Pin 4
...Tungsten metallization 5..Silver solder 6..Nickel plating layer 7..Gold plating layer 8..Wiring layer 9..
Semiconductor element 10... Silver-filled glass 11... Aluminum wire 12... Cap 13... Sealing glass 14... Gold solder
Claims (1)
板の表面に形成した配線層と、穴開き絶縁基板の表面に
塔載され配線層と結線された半導体素子と、穴開き絶縁
基板の貫通孔に基板表面で配線層と接続し且つ基板裏面
から突出するように挿入され、貫通孔内で金ロウにより
固着された表面に金めつき層を有する金属製のピンとを
具えたことを特徴とする半導体装置。(1) A perforated insulating substrate having a through hole, a wiring layer formed on the surface of the perforated insulating substrate, a semiconductor element mounted on the surface of the perforated insulating substrate and connected to the wiring layer, and a perforated insulating substrate A metal pin is inserted into the through-hole so as to connect to the wiring layer on the surface of the board and protrude from the back of the board, and is fixed in the through-hole with gold solder and has a gold-plated layer on the surface. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8805687A JPS63253657A (en) | 1987-04-10 | 1987-04-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8805687A JPS63253657A (en) | 1987-04-10 | 1987-04-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63253657A true JPS63253657A (en) | 1988-10-20 |
Family
ID=13932184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8805687A Pending JPS63253657A (en) | 1987-04-10 | 1987-04-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63253657A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5006922A (en) * | 1990-02-14 | 1991-04-09 | Motorola, Inc. | Packaged semiconductor device having a low cost ceramic PGA package |
-
1987
- 1987-04-10 JP JP8805687A patent/JPS63253657A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5006922A (en) * | 1990-02-14 | 1991-04-09 | Motorola, Inc. | Packaged semiconductor device having a low cost ceramic PGA package |
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